1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for sunxi SD/MMC host controllers 4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 9 * (C) Copyright 2017 Sootech SA 10 */ 11 12#include <linux/clk.h> 13#include <linux/clk/sunxi-ng.h> 14#include <linux/delay.h> 15#include <linux/device.h> 16#include <linux/dma-mapping.h> 17#include <linux/err.h> 18#include <linux/interrupt.h> 19#include <linux/io.h> 20#include <linux/kernel.h> 21#include <linux/mmc/card.h> 22#include <linux/mmc/core.h> 23#include <linux/mmc/host.h> 24#include <linux/mmc/mmc.h> 25#include <linux/mmc/sd.h> 26#include <linux/mmc/sdio.h> 27#include <linux/mmc/slot-gpio.h> 28#include <linux/module.h> 29#include <linux/of_address.h> 30#include <linux/of_platform.h> 31#include <linux/platform_device.h> 32#include <linux/pm_runtime.h> 33#include <linux/regulator/consumer.h> 34#include <linux/reset.h> 35#include <linux/scatterlist.h> 36#include <linux/slab.h> 37#include <linux/spinlock.h> 38 39/* register offset definitions */ 40#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 41#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 42#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 43#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 44#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 45#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 46#define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 47#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 48#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 49#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 50#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 51#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 52#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 53#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 54#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 55#define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 56#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 57#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 58#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 59#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 60#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 61#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 62#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 63#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 64#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 65#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 66#define SDXC_REG_CHDA (0x90) 67#define SDXC_REG_CBDA (0x94) 68 69/* New registers introduced in A64 */ 70#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 71#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 72#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 73#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 74#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 75 76#define mmc_readl(host, reg) \ 77 readl((host)->reg_base + SDXC_##reg) 78#define mmc_writel(host, reg, value) \ 79 writel((value), (host)->reg_base + SDXC_##reg) 80 81/* global control register bits */ 82#define SDXC_SOFT_RESET BIT(0) 83#define SDXC_FIFO_RESET BIT(1) 84#define SDXC_DMA_RESET BIT(2) 85#define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 86#define SDXC_DMA_ENABLE_BIT BIT(5) 87#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 88#define SDXC_POSEDGE_LATCH_DATA BIT(9) 89#define SDXC_DDR_MODE BIT(10) 90#define SDXC_MEMORY_ACCESS_DONE BIT(29) 91#define SDXC_ACCESS_DONE_DIRECT BIT(30) 92#define SDXC_ACCESS_BY_AHB BIT(31) 93#define SDXC_ACCESS_BY_DMA (0 << 31) 94#define SDXC_HARDWARE_RESET \ 95 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 96 97/* clock control bits */ 98#define SDXC_MASK_DATA0 BIT(31) 99#define SDXC_CARD_CLOCK_ON BIT(16) 100#define SDXC_LOW_POWER_ON BIT(17) 101 102/* bus width */ 103#define SDXC_WIDTH1 0 104#define SDXC_WIDTH4 1 105#define SDXC_WIDTH8 2 106 107/* smc command bits */ 108#define SDXC_RESP_EXPIRE BIT(6) 109#define SDXC_LONG_RESPONSE BIT(7) 110#define SDXC_CHECK_RESPONSE_CRC BIT(8) 111#define SDXC_DATA_EXPIRE BIT(9) 112#define SDXC_WRITE BIT(10) 113#define SDXC_SEQUENCE_MODE BIT(11) 114#define SDXC_SEND_AUTO_STOP BIT(12) 115#define SDXC_WAIT_PRE_OVER BIT(13) 116#define SDXC_STOP_ABORT_CMD BIT(14) 117#define SDXC_SEND_INIT_SEQUENCE BIT(15) 118#define SDXC_UPCLK_ONLY BIT(21) 119#define SDXC_READ_CEATA_DEV BIT(22) 120#define SDXC_CCS_EXPIRE BIT(23) 121#define SDXC_ENABLE_BIT_BOOT BIT(24) 122#define SDXC_ALT_BOOT_OPTIONS BIT(25) 123#define SDXC_BOOT_ACK_EXPIRE BIT(26) 124#define SDXC_BOOT_ABORT BIT(27) 125#define SDXC_VOLTAGE_SWITCH BIT(28) 126#define SDXC_USE_HOLD_REGISTER BIT(29) 127#define SDXC_START BIT(31) 128 129/* interrupt bits */ 130#define SDXC_RESP_ERROR BIT(1) 131#define SDXC_COMMAND_DONE BIT(2) 132#define SDXC_DATA_OVER BIT(3) 133#define SDXC_TX_DATA_REQUEST BIT(4) 134#define SDXC_RX_DATA_REQUEST BIT(5) 135#define SDXC_RESP_CRC_ERROR BIT(6) 136#define SDXC_DATA_CRC_ERROR BIT(7) 137#define SDXC_RESP_TIMEOUT BIT(8) 138#define SDXC_DATA_TIMEOUT BIT(9) 139#define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 140#define SDXC_FIFO_RUN_ERROR BIT(11) 141#define SDXC_HARD_WARE_LOCKED BIT(12) 142#define SDXC_START_BIT_ERROR BIT(13) 143#define SDXC_AUTO_COMMAND_DONE BIT(14) 144#define SDXC_END_BIT_ERROR BIT(15) 145#define SDXC_SDIO_INTERRUPT BIT(16) 146#define SDXC_CARD_INSERT BIT(30) 147#define SDXC_CARD_REMOVE BIT(31) 148#define SDXC_INTERRUPT_ERROR_BIT \ 149 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 150 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 151 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 152#define SDXC_INTERRUPT_DONE_BIT \ 153 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 154 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 155 156/* status */ 157#define SDXC_RXWL_FLAG BIT(0) 158#define SDXC_TXWL_FLAG BIT(1) 159#define SDXC_FIFO_EMPTY BIT(2) 160#define SDXC_FIFO_FULL BIT(3) 161#define SDXC_CARD_PRESENT BIT(8) 162#define SDXC_CARD_DATA_BUSY BIT(9) 163#define SDXC_DATA_FSM_BUSY BIT(10) 164#define SDXC_DMA_REQUEST BIT(31) 165#define SDXC_FIFO_SIZE 16 166 167/* Function select */ 168#define SDXC_CEATA_ON (0xceaa << 16) 169#define SDXC_SEND_IRQ_RESPONSE BIT(0) 170#define SDXC_SDIO_READ_WAIT BIT(1) 171#define SDXC_ABORT_READ_DATA BIT(2) 172#define SDXC_SEND_CCSD BIT(8) 173#define SDXC_SEND_AUTO_STOPCCSD BIT(9) 174#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 175 176/* IDMA controller bus mod bit field */ 177#define SDXC_IDMAC_SOFT_RESET BIT(0) 178#define SDXC_IDMAC_FIX_BURST BIT(1) 179#define SDXC_IDMAC_IDMA_ON BIT(7) 180#define SDXC_IDMAC_REFETCH_DES BIT(31) 181 182/* IDMA status bit field */ 183#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 184#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 185#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 186#define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 187#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 188#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 189#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 190#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 191#define SDXC_IDMAC_IDLE (0 << 13) 192#define SDXC_IDMAC_SUSPEND (1 << 13) 193#define SDXC_IDMAC_DESC_READ (2 << 13) 194#define SDXC_IDMAC_DESC_CHECK (3 << 13) 195#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 196#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 197#define SDXC_IDMAC_READ (6 << 13) 198#define SDXC_IDMAC_WRITE (7 << 13) 199#define SDXC_IDMAC_DESC_CLOSE (8 << 13) 200 201/* 202* If the idma-des-size-bits of property is ie 13, bufsize bits are: 203* Bits 0-12: buf1 size 204* Bits 13-25: buf2 size 205* Bits 26-31: not used 206* Since we only ever set buf1 size, we can simply store it directly. 207*/ 208#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 209#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 210#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 211#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 212#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 213#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 214#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 215 216#define SDXC_CLK_400K 0 217#define SDXC_CLK_25M 1 218#define SDXC_CLK_50M 2 219#define SDXC_CLK_50M_DDR 3 220#define SDXC_CLK_50M_DDR_8BIT 4 221 222#define SDXC_2X_TIMING_MODE BIT(31) 223 224#define SDXC_CAL_START BIT(15) 225#define SDXC_CAL_DONE BIT(14) 226#define SDXC_CAL_DL_SHIFT 8 227#define SDXC_CAL_DL_SW_EN BIT(7) 228#define SDXC_CAL_DL_SW_SHIFT 0 229#define SDXC_CAL_DL_MASK 0x3f 230 231#define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 232 233struct sunxi_mmc_clk_delay { 234 u32 output; 235 u32 sample; 236}; 237 238struct sunxi_idma_des { 239 __le32 config; 240 __le32 buf_size; 241 __le32 buf_addr_ptr1; 242 __le32 buf_addr_ptr2; 243}; 244 245struct sunxi_mmc_cfg { 246 u32 idma_des_size_bits; 247 const struct sunxi_mmc_clk_delay *clk_delays; 248 249 /* does the IP block support autocalibration? */ 250 bool can_calibrate; 251 252 /* Does DATA0 needs to be masked while the clock is updated */ 253 bool mask_data0; 254 255 /* 256 * hardware only supports new timing mode, either due to lack of 257 * a mode switch in the clock controller, or the mmc controller 258 * is permanently configured in the new timing mode, without the 259 * NTSR mode switch. 260 */ 261 bool needs_new_timings; 262 263 /* clock hardware can switch between old and new timing modes */ 264 bool ccu_has_timings_switch; 265}; 266 267struct sunxi_mmc_host { 268 struct device *dev; 269 struct mmc_host *mmc; 270 struct reset_control *reset; 271 const struct sunxi_mmc_cfg *cfg; 272 273 /* IO mapping base */ 274 void __iomem *reg_base; 275 276 /* clock management */ 277 struct clk *clk_ahb; 278 struct clk *clk_mmc; 279 struct clk *clk_sample; 280 struct clk *clk_output; 281 282 /* irq */ 283 spinlock_t lock; 284 int irq; 285 u32 int_sum; 286 u32 sdio_imask; 287 288 /* dma */ 289 dma_addr_t sg_dma; 290 void *sg_cpu; 291 bool wait_dma; 292 293 struct mmc_request *mrq; 294 struct mmc_request *manual_stop_mrq; 295 int ferror; 296 297 /* vqmmc */ 298 bool vqmmc_enabled; 299 300 /* timings */ 301 bool use_new_timings; 302}; 303 304static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 305{ 306 unsigned long expire = jiffies + msecs_to_jiffies(250); 307 u32 rval; 308 309 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 310 do { 311 rval = mmc_readl(host, REG_GCTRL); 312 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 313 314 if (rval & SDXC_HARDWARE_RESET) { 315 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 316 return -EIO; 317 } 318 319 return 0; 320} 321 322static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) 323{ 324 u32 rval; 325 326 if (sunxi_mmc_reset_host(host)) 327 return -EIO; 328 329 /* 330 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 331 * 332 * TODO: sun9i has a larger FIFO and supports higher trigger values 333 */ 334 mmc_writel(host, REG_FTRGL, 0x20070008); 335 /* Maximum timeout value */ 336 mmc_writel(host, REG_TMOUT, 0xffffffff); 337 /* Unmask SDIO interrupt if needed */ 338 mmc_writel(host, REG_IMASK, host->sdio_imask); 339 /* Clear all pending interrupts */ 340 mmc_writel(host, REG_RINTR, 0xffffffff); 341 /* Debug register? undocumented */ 342 mmc_writel(host, REG_DBGC, 0xdeb); 343 /* Enable CEATA support */ 344 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 345 /* Set DMA descriptor list base address */ 346 mmc_writel(host, REG_DLBA, host->sg_dma); 347 348 rval = mmc_readl(host, REG_GCTRL); 349 rval |= SDXC_INTERRUPT_ENABLE_BIT; 350 /* Undocumented, but found in Allwinner code */ 351 rval &= ~SDXC_ACCESS_DONE_DIRECT; 352 mmc_writel(host, REG_GCTRL, rval); 353 354 return 0; 355} 356 357static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 358 struct mmc_data *data) 359{ 360 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 361 dma_addr_t next_desc = host->sg_dma; 362 int i, max_len = (1 << host->cfg->idma_des_size_bits); 363 364 for (i = 0; i < data->sg_len; i++) { 365 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 366 SDXC_IDMAC_DES0_OWN | 367 SDXC_IDMAC_DES0_DIC); 368 369 if (data->sg[i].length == max_len) 370 pdes[i].buf_size = 0; /* 0 == max_len */ 371 else 372 pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 373 374 next_desc += sizeof(struct sunxi_idma_des); 375 pdes[i].buf_addr_ptr1 = 376 cpu_to_le32(sg_dma_address(&data->sg[i])); 377 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 378 } 379 380 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 381 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 382 SDXC_IDMAC_DES0_ER); 383 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 384 pdes[i - 1].buf_addr_ptr2 = 0; 385 386 /* 387 * Avoid the io-store starting the idmac hitting io-mem before the 388 * descriptors hit the main-mem. 389 */ 390 wmb(); 391} 392 393static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 394 struct mmc_data *data) 395{ 396 u32 i, dma_len; 397 struct scatterlist *sg; 398 399 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 400 mmc_get_dma_dir(data)); 401 if (dma_len == 0) { 402 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 403 return -ENOMEM; 404 } 405 406 for_each_sg(data->sg, sg, data->sg_len, i) { 407 if (sg->offset & 3 || sg->length & 3) { 408 dev_err(mmc_dev(host->mmc), 409 "unaligned scatterlist: os %x length %d\n", 410 sg->offset, sg->length); 411 return -EINVAL; 412 } 413 } 414 415 return 0; 416} 417 418static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 419 struct mmc_data *data) 420{ 421 u32 rval; 422 423 sunxi_mmc_init_idma_des(host, data); 424 425 rval = mmc_readl(host, REG_GCTRL); 426 rval |= SDXC_DMA_ENABLE_BIT; 427 mmc_writel(host, REG_GCTRL, rval); 428 rval |= SDXC_DMA_RESET; 429 mmc_writel(host, REG_GCTRL, rval); 430 431 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 432 433 if (!(data->flags & MMC_DATA_WRITE)) 434 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 435 436 mmc_writel(host, REG_DMAC, 437 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 438} 439 440static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 441 struct mmc_request *req) 442{ 443 u32 arg, cmd_val, ri; 444 unsigned long expire = jiffies + msecs_to_jiffies(1000); 445 446 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 447 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 448 449 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 450 cmd_val |= SD_IO_RW_DIRECT; 451 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 452 ((req->cmd->arg >> 28) & 0x7); 453 } else { 454 cmd_val |= MMC_STOP_TRANSMISSION; 455 arg = 0; 456 } 457 458 mmc_writel(host, REG_CARG, arg); 459 mmc_writel(host, REG_CMDR, cmd_val); 460 461 do { 462 ri = mmc_readl(host, REG_RINTR); 463 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 464 time_before(jiffies, expire)); 465 466 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 467 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 468 if (req->stop) 469 req->stop->resp[0] = -ETIMEDOUT; 470 } else { 471 if (req->stop) 472 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 473 } 474 475 mmc_writel(host, REG_RINTR, 0xffff); 476} 477 478static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 479{ 480 struct mmc_command *cmd = host->mrq->cmd; 481 struct mmc_data *data = host->mrq->data; 482 483 /* For some cmds timeout is normal with sd/mmc cards */ 484 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 485 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 486 cmd->opcode == SD_IO_RW_DIRECT)) 487 return; 488 489 dev_dbg(mmc_dev(host->mmc), 490 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 491 host->mmc->index, cmd->opcode, 492 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 493 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 494 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 495 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 496 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 497 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 498 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 499 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 500 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 501 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 502 ); 503} 504 505/* Called in interrupt context! */ 506static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 507{ 508 struct mmc_request *mrq = host->mrq; 509 struct mmc_data *data = mrq->data; 510 u32 rval; 511 512 mmc_writel(host, REG_IMASK, host->sdio_imask); 513 mmc_writel(host, REG_IDIE, 0); 514 515 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 516 sunxi_mmc_dump_errinfo(host); 517 mrq->cmd->error = -ETIMEDOUT; 518 519 if (data) { 520 data->error = -ETIMEDOUT; 521 host->manual_stop_mrq = mrq; 522 } 523 524 if (mrq->stop) 525 mrq->stop->error = -ETIMEDOUT; 526 } else { 527 if (mrq->cmd->flags & MMC_RSP_136) { 528 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 529 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 530 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 531 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 532 } else { 533 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 534 } 535 536 if (data) 537 data->bytes_xfered = data->blocks * data->blksz; 538 } 539 540 if (data) { 541 mmc_writel(host, REG_IDST, 0x337); 542 mmc_writel(host, REG_DMAC, 0); 543 rval = mmc_readl(host, REG_GCTRL); 544 rval |= SDXC_DMA_RESET; 545 mmc_writel(host, REG_GCTRL, rval); 546 rval &= ~SDXC_DMA_ENABLE_BIT; 547 mmc_writel(host, REG_GCTRL, rval); 548 rval |= SDXC_FIFO_RESET; 549 mmc_writel(host, REG_GCTRL, rval); 550 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 551 mmc_get_dma_dir(data)); 552 } 553 554 mmc_writel(host, REG_RINTR, 0xffff); 555 556 host->mrq = NULL; 557 host->int_sum = 0; 558 host->wait_dma = false; 559 560 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 561} 562 563static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 564{ 565 struct sunxi_mmc_host *host = dev_id; 566 struct mmc_request *mrq; 567 u32 msk_int, idma_int; 568 bool finalize = false; 569 bool sdio_int = false; 570 irqreturn_t ret = IRQ_HANDLED; 571 572 spin_lock(&host->lock); 573 574 idma_int = mmc_readl(host, REG_IDST); 575 msk_int = mmc_readl(host, REG_MISTA); 576 577 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 578 host->mrq, msk_int, idma_int); 579 580 mrq = host->mrq; 581 if (mrq) { 582 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 583 host->wait_dma = false; 584 585 host->int_sum |= msk_int; 586 587 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 588 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 589 !(host->int_sum & SDXC_COMMAND_DONE)) 590 mmc_writel(host, REG_IMASK, 591 host->sdio_imask | SDXC_COMMAND_DONE); 592 /* Don't wait for dma on error */ 593 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 594 finalize = true; 595 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 596 !host->wait_dma) 597 finalize = true; 598 } 599 600 if (msk_int & SDXC_SDIO_INTERRUPT) 601 sdio_int = true; 602 603 mmc_writel(host, REG_RINTR, msk_int); 604 mmc_writel(host, REG_IDST, idma_int); 605 606 if (finalize) 607 ret = sunxi_mmc_finalize_request(host); 608 609 spin_unlock(&host->lock); 610 611 if (finalize && ret == IRQ_HANDLED) 612 mmc_request_done(host->mmc, mrq); 613 614 if (sdio_int) 615 mmc_signal_sdio_irq(host->mmc); 616 617 return ret; 618} 619 620static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 621{ 622 struct sunxi_mmc_host *host = dev_id; 623 struct mmc_request *mrq; 624 unsigned long iflags; 625 626 spin_lock_irqsave(&host->lock, iflags); 627 mrq = host->manual_stop_mrq; 628 spin_unlock_irqrestore(&host->lock, iflags); 629 630 if (!mrq) { 631 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 632 return IRQ_HANDLED; 633 } 634 635 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 636 637 /* 638 * We will never have more than one outstanding request, 639 * and we do not complete the request until after 640 * we've cleared host->manual_stop_mrq so we do not need to 641 * spin lock this function. 642 * Additionally we have wait states within this function 643 * so having it in a lock is a very bad idea. 644 */ 645 sunxi_mmc_send_manual_stop(host, mrq); 646 647 spin_lock_irqsave(&host->lock, iflags); 648 host->manual_stop_mrq = NULL; 649 spin_unlock_irqrestore(&host->lock, iflags); 650 651 mmc_request_done(host->mmc, mrq); 652 653 return IRQ_HANDLED; 654} 655 656static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 657{ 658 unsigned long expire = jiffies + msecs_to_jiffies(750); 659 u32 rval; 660 661 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 662 oclk_en ? "en" : "dis"); 663 664 rval = mmc_readl(host, REG_CLKCR); 665 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 666 667 if (oclk_en) 668 rval |= SDXC_CARD_CLOCK_ON; 669 if (host->cfg->mask_data0) 670 rval |= SDXC_MASK_DATA0; 671 672 mmc_writel(host, REG_CLKCR, rval); 673 674 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 675 mmc_writel(host, REG_CMDR, rval); 676 677 do { 678 rval = mmc_readl(host, REG_CMDR); 679 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 680 681 /* clear irq status bits set by the command */ 682 mmc_writel(host, REG_RINTR, 683 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 684 685 if (rval & SDXC_START) { 686 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 687 return -EIO; 688 } 689 690 if (host->cfg->mask_data0) { 691 rval = mmc_readl(host, REG_CLKCR); 692 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 693 } 694 695 return 0; 696} 697 698static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 699{ 700 if (!host->cfg->can_calibrate) 701 return 0; 702 703 /* 704 * FIXME: 705 * This is not clear how the calibration is supposed to work 706 * yet. The best rate have been obtained by simply setting the 707 * delay to 0, as Allwinner does in its BSP. 708 * 709 * The only mode that doesn't have such a delay is HS400, that 710 * is in itself a TODO. 711 */ 712 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 713 714 return 0; 715} 716 717static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 718 struct mmc_ios *ios, u32 rate) 719{ 720 int index; 721 722 /* clk controller delays not used under new timings mode */ 723 if (host->use_new_timings) 724 return 0; 725 726 /* some old controllers don't support delays */ 727 if (!host->cfg->clk_delays) 728 return 0; 729 730 /* determine delays */ 731 if (rate <= 400000) { 732 index = SDXC_CLK_400K; 733 } else if (rate <= 25000000) { 734 index = SDXC_CLK_25M; 735 } else if (rate <= 52000000) { 736 if (ios->timing != MMC_TIMING_UHS_DDR50 && 737 ios->timing != MMC_TIMING_MMC_DDR52) { 738 index = SDXC_CLK_50M; 739 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 740 index = SDXC_CLK_50M_DDR_8BIT; 741 } else { 742 index = SDXC_CLK_50M_DDR; 743 } 744 } else { 745 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 746 return -EINVAL; 747 } 748 749 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 750 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 751 752 return 0; 753} 754 755static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 756 struct mmc_ios *ios) 757{ 758 struct mmc_host *mmc = host->mmc; 759 long rate; 760 u32 rval, clock = ios->clock, div = 1; 761 int ret; 762 763 ret = sunxi_mmc_oclk_onoff(host, 0); 764 if (ret) 765 return ret; 766 767 /* Our clock is gated now */ 768 mmc->actual_clock = 0; 769 770 if (!ios->clock) 771 return 0; 772 773 /* 774 * Under the old timing mode, 8 bit DDR requires the module 775 * clock to be double the card clock. Under the new timing 776 * mode, all DDR modes require a doubled module clock. 777 * 778 * We currently only support the standard MMC DDR52 mode. 779 * This block should be updated once support for other DDR 780 * modes is added. 781 */ 782 if (ios->timing == MMC_TIMING_MMC_DDR52 && 783 (host->use_new_timings || 784 ios->bus_width == MMC_BUS_WIDTH_8)) { 785 div = 2; 786 clock <<= 1; 787 } 788 789 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { 790 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 791 if (ret) { 792 dev_err(mmc_dev(mmc), 793 "error setting new timing mode\n"); 794 return ret; 795 } 796 } 797 798 rate = clk_round_rate(host->clk_mmc, clock); 799 if (rate < 0) { 800 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 801 clock, rate); 802 return rate; 803 } 804 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 805 clock, rate); 806 807 /* setting clock rate */ 808 ret = clk_set_rate(host->clk_mmc, rate); 809 if (ret) { 810 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 811 rate, ret); 812 return ret; 813 } 814 815 /* set internal divider */ 816 rval = mmc_readl(host, REG_CLKCR); 817 rval &= ~0xff; 818 rval |= div - 1; 819 mmc_writel(host, REG_CLKCR, rval); 820 821 /* update card clock rate to account for internal divider */ 822 rate /= div; 823 824 /* 825 * Configure the controller to use the new timing mode if needed. 826 * On controllers that only support the new timing mode, such as 827 * the eMMC controller on the A64, this register does not exist, 828 * and any writes to it are ignored. 829 */ 830 if (host->use_new_timings) { 831 /* Don't touch the delay bits */ 832 rval = mmc_readl(host, REG_SD_NTSR); 833 rval |= SDXC_2X_TIMING_MODE; 834 mmc_writel(host, REG_SD_NTSR, rval); 835 } 836 837 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 838 ret = sunxi_mmc_clk_set_phase(host, ios, rate); 839 if (ret) 840 return ret; 841 842 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 843 if (ret) 844 return ret; 845 846 /* 847 * FIXME: 848 * 849 * In HS400 we'll also need to calibrate the data strobe 850 * signal. This should only happen on the MMC2 controller (at 851 * least on the A64). 852 */ 853 854 ret = sunxi_mmc_oclk_onoff(host, 1); 855 if (ret) 856 return ret; 857 858 /* And we just enabled our clock back */ 859 mmc->actual_clock = rate; 860 861 return 0; 862} 863 864static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, 865 unsigned char width) 866{ 867 switch (width) { 868 case MMC_BUS_WIDTH_1: 869 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 870 break; 871 case MMC_BUS_WIDTH_4: 872 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 873 break; 874 case MMC_BUS_WIDTH_8: 875 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 876 break; 877 } 878} 879 880static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) 881{ 882 u32 rval; 883 884 /* set ddr mode */ 885 rval = mmc_readl(host, REG_GCTRL); 886 if (ios->timing == MMC_TIMING_UHS_DDR50 || 887 ios->timing == MMC_TIMING_MMC_DDR52) 888 rval |= SDXC_DDR_MODE; 889 else 890 rval &= ~SDXC_DDR_MODE; 891 mmc_writel(host, REG_GCTRL, rval); 892 893 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 894 /* Android code had a usleep_range(50000, 55000); here */ 895} 896 897static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, 898 struct mmc_ios *ios) 899{ 900 struct mmc_host *mmc = host->mmc; 901 902 switch (ios->power_mode) { 903 case MMC_POWER_UP: 904 dev_dbg(mmc_dev(mmc), "Powering card up\n"); 905 906 if (!IS_ERR(mmc->supply.vmmc)) { 907 host->ferror = mmc_regulator_set_ocr(mmc, 908 mmc->supply.vmmc, 909 ios->vdd); 910 if (host->ferror) 911 return; 912 } 913 914 if (!IS_ERR(mmc->supply.vqmmc)) { 915 host->ferror = regulator_enable(mmc->supply.vqmmc); 916 if (host->ferror) { 917 dev_err(mmc_dev(mmc), 918 "failed to enable vqmmc\n"); 919 return; 920 } 921 host->vqmmc_enabled = true; 922 } 923 break; 924 925 case MMC_POWER_OFF: 926 dev_dbg(mmc_dev(mmc), "Powering card off\n"); 927 928 if (!IS_ERR(mmc->supply.vmmc)) 929 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 930 931 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 932 regulator_disable(mmc->supply.vqmmc); 933 934 host->vqmmc_enabled = false; 935 break; 936 937 default: 938 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); 939 break; 940 } 941} 942 943static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 944{ 945 struct sunxi_mmc_host *host = mmc_priv(mmc); 946 947 sunxi_mmc_card_power(host, ios); 948 sunxi_mmc_set_bus_width(host, ios->bus_width); 949 sunxi_mmc_set_clk(host, ios); 950} 951 952static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 953{ 954 int ret; 955 956 /* vqmmc regulator is available */ 957 if (!IS_ERR(mmc->supply.vqmmc)) { 958 ret = mmc_regulator_set_vqmmc(mmc, ios); 959 return ret < 0 ? ret : 0; 960 } 961 962 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 963 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 964 return 0; 965 966 return -EINVAL; 967} 968 969static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 970{ 971 struct sunxi_mmc_host *host = mmc_priv(mmc); 972 unsigned long flags; 973 u32 imask; 974 975 if (enable) 976 pm_runtime_get_noresume(host->dev); 977 978 spin_lock_irqsave(&host->lock, flags); 979 980 imask = mmc_readl(host, REG_IMASK); 981 if (enable) { 982 host->sdio_imask = SDXC_SDIO_INTERRUPT; 983 imask |= SDXC_SDIO_INTERRUPT; 984 } else { 985 host->sdio_imask = 0; 986 imask &= ~SDXC_SDIO_INTERRUPT; 987 } 988 mmc_writel(host, REG_IMASK, imask); 989 spin_unlock_irqrestore(&host->lock, flags); 990 991 if (!enable) 992 pm_runtime_put_noidle(host->mmc->parent); 993} 994 995static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 996{ 997 struct sunxi_mmc_host *host = mmc_priv(mmc); 998 mmc_writel(host, REG_HWRST, 0); 999 udelay(10); 1000 mmc_writel(host, REG_HWRST, 1); 1001 udelay(300); 1002} 1003 1004static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 1005{ 1006 struct sunxi_mmc_host *host = mmc_priv(mmc); 1007 struct mmc_command *cmd = mrq->cmd; 1008 struct mmc_data *data = mrq->data; 1009 unsigned long iflags; 1010 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 1011 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 1012 bool wait_dma = host->wait_dma; 1013 int ret; 1014 1015 /* Check for set_ios errors (should never happen) */ 1016 if (host->ferror) { 1017 mrq->cmd->error = host->ferror; 1018 mmc_request_done(mmc, mrq); 1019 return; 1020 } 1021 1022 if (data) { 1023 ret = sunxi_mmc_map_dma(host, data); 1024 if (ret < 0) { 1025 dev_err(mmc_dev(mmc), "map DMA failed\n"); 1026 cmd->error = ret; 1027 data->error = ret; 1028 mmc_request_done(mmc, mrq); 1029 return; 1030 } 1031 } 1032 1033 if (cmd->opcode == MMC_GO_IDLE_STATE) { 1034 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 1035 imask |= SDXC_COMMAND_DONE; 1036 } 1037 1038 if (cmd->flags & MMC_RSP_PRESENT) { 1039 cmd_val |= SDXC_RESP_EXPIRE; 1040 if (cmd->flags & MMC_RSP_136) 1041 cmd_val |= SDXC_LONG_RESPONSE; 1042 if (cmd->flags & MMC_RSP_CRC) 1043 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 1044 1045 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 1046 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 1047 1048 if (cmd->data->stop) { 1049 imask |= SDXC_AUTO_COMMAND_DONE; 1050 cmd_val |= SDXC_SEND_AUTO_STOP; 1051 } else { 1052 imask |= SDXC_DATA_OVER; 1053 } 1054 1055 if (cmd->data->flags & MMC_DATA_WRITE) 1056 cmd_val |= SDXC_WRITE; 1057 else 1058 wait_dma = true; 1059 } else { 1060 imask |= SDXC_COMMAND_DONE; 1061 } 1062 } else { 1063 imask |= SDXC_COMMAND_DONE; 1064 } 1065 1066 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 1067 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 1068 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 1069 1070 spin_lock_irqsave(&host->lock, iflags); 1071 1072 if (host->mrq || host->manual_stop_mrq) { 1073 spin_unlock_irqrestore(&host->lock, iflags); 1074 1075 if (data) 1076 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1077 mmc_get_dma_dir(data)); 1078 1079 dev_err(mmc_dev(mmc), "request already pending\n"); 1080 mrq->cmd->error = -EBUSY; 1081 mmc_request_done(mmc, mrq); 1082 return; 1083 } 1084 1085 if (data) { 1086 mmc_writel(host, REG_BLKSZ, data->blksz); 1087 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 1088 sunxi_mmc_start_dma(host, data); 1089 } 1090 1091 host->mrq = mrq; 1092 host->wait_dma = wait_dma; 1093 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 1094 mmc_writel(host, REG_CARG, cmd->arg); 1095 mmc_writel(host, REG_CMDR, cmd_val); 1096 1097 spin_unlock_irqrestore(&host->lock, iflags); 1098} 1099 1100static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1101{ 1102 struct sunxi_mmc_host *host = mmc_priv(mmc); 1103 1104 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1105} 1106 1107static const struct mmc_host_ops sunxi_mmc_ops = { 1108 .request = sunxi_mmc_request, 1109 .set_ios = sunxi_mmc_set_ios, 1110 .get_ro = mmc_gpio_get_ro, 1111 .get_cd = mmc_gpio_get_cd, 1112 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1113 .start_signal_voltage_switch = sunxi_mmc_volt_switch, 1114 .hw_reset = sunxi_mmc_hw_reset, 1115 .card_busy = sunxi_mmc_card_busy, 1116}; 1117 1118static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 1119 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1120 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1121 [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 1122 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 1123 /* Value from A83T "new timing mode". Works but might not be right. */ 1124 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 1125}; 1126 1127static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 1128 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1129 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1130 [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 1131 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 1132 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 1133}; 1134 1135static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 1136 .idma_des_size_bits = 13, 1137 .clk_delays = NULL, 1138 .can_calibrate = false, 1139}; 1140 1141static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 1142 .idma_des_size_bits = 16, 1143 .clk_delays = NULL, 1144 .can_calibrate = false, 1145}; 1146 1147static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1148 .idma_des_size_bits = 16, 1149 .clk_delays = sunxi_mmc_clk_delays, 1150 .can_calibrate = false, 1151}; 1152 1153static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1154 .idma_des_size_bits = 16, 1155 .clk_delays = sunxi_mmc_clk_delays, 1156 .can_calibrate = false, 1157 .ccu_has_timings_switch = true, 1158}; 1159 1160static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 1161 .idma_des_size_bits = 16, 1162 .clk_delays = sun9i_mmc_clk_delays, 1163 .can_calibrate = false, 1164}; 1165 1166static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1167 .idma_des_size_bits = 16, 1168 .clk_delays = NULL, 1169 .can_calibrate = true, 1170 .mask_data0 = true, 1171 .needs_new_timings = true, 1172}; 1173 1174static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 1175 .idma_des_size_bits = 13, 1176 .clk_delays = NULL, 1177 .can_calibrate = true, 1178 .needs_new_timings = true, 1179}; 1180 1181static const struct of_device_id sunxi_mmc_of_match[] = { 1182 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 1183 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1184 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1185 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 1186 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1187 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 1188 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 1189 { /* sentinel */ } 1190}; 1191MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 1192 1193static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1194{ 1195 int ret; 1196 1197 if (!IS_ERR(host->reset)) { 1198 ret = reset_control_reset(host->reset); 1199 if (ret) { 1200 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1201 ret); 1202 return ret; 1203 } 1204 } 1205 1206 ret = clk_prepare_enable(host->clk_ahb); 1207 if (ret) { 1208 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1209 goto error_assert_reset; 1210 } 1211 1212 ret = clk_prepare_enable(host->clk_mmc); 1213 if (ret) { 1214 dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1215 goto error_disable_clk_ahb; 1216 } 1217 1218 ret = clk_prepare_enable(host->clk_output); 1219 if (ret) { 1220 dev_err(host->dev, "Enable output clk err %d\n", ret); 1221 goto error_disable_clk_mmc; 1222 } 1223 1224 ret = clk_prepare_enable(host->clk_sample); 1225 if (ret) { 1226 dev_err(host->dev, "Enable sample clk err %d\n", ret); 1227 goto error_disable_clk_output; 1228 } 1229 1230 /* 1231 * Sometimes the controller asserts the irq on boot for some reason, 1232 * make sure the controller is in a sane state before enabling irqs. 1233 */ 1234 ret = sunxi_mmc_reset_host(host); 1235 if (ret) 1236 goto error_disable_clk_sample; 1237 1238 return 0; 1239 1240error_disable_clk_sample: 1241 clk_disable_unprepare(host->clk_sample); 1242error_disable_clk_output: 1243 clk_disable_unprepare(host->clk_output); 1244error_disable_clk_mmc: 1245 clk_disable_unprepare(host->clk_mmc); 1246error_disable_clk_ahb: 1247 clk_disable_unprepare(host->clk_ahb); 1248error_assert_reset: 1249 if (!IS_ERR(host->reset)) 1250 reset_control_assert(host->reset); 1251 return ret; 1252} 1253 1254static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1255{ 1256 sunxi_mmc_reset_host(host); 1257 1258 clk_disable_unprepare(host->clk_sample); 1259 clk_disable_unprepare(host->clk_output); 1260 clk_disable_unprepare(host->clk_mmc); 1261 clk_disable_unprepare(host->clk_ahb); 1262 1263 if (!IS_ERR(host->reset)) 1264 reset_control_assert(host->reset); 1265} 1266 1267static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 1268 struct platform_device *pdev) 1269{ 1270 int ret; 1271 1272 host->cfg = of_device_get_match_data(&pdev->dev); 1273 if (!host->cfg) 1274 return -EINVAL; 1275 1276 ret = mmc_regulator_get_supply(host->mmc); 1277 if (ret) 1278 return ret; 1279 1280 host->reg_base = devm_platform_ioremap_resource(pdev, 0); 1281 if (IS_ERR(host->reg_base)) 1282 return PTR_ERR(host->reg_base); 1283 1284 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1285 if (IS_ERR(host->clk_ahb)) { 1286 dev_err(&pdev->dev, "Could not get ahb clock\n"); 1287 return PTR_ERR(host->clk_ahb); 1288 } 1289 1290 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 1291 if (IS_ERR(host->clk_mmc)) { 1292 dev_err(&pdev->dev, "Could not get mmc clock\n"); 1293 return PTR_ERR(host->clk_mmc); 1294 } 1295 1296 if (host->cfg->clk_delays) { 1297 host->clk_output = devm_clk_get(&pdev->dev, "output"); 1298 if (IS_ERR(host->clk_output)) { 1299 dev_err(&pdev->dev, "Could not get output clock\n"); 1300 return PTR_ERR(host->clk_output); 1301 } 1302 1303 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 1304 if (IS_ERR(host->clk_sample)) { 1305 dev_err(&pdev->dev, "Could not get sample clock\n"); 1306 return PTR_ERR(host->clk_sample); 1307 } 1308 } 1309 1310 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1311 "ahb"); 1312 if (PTR_ERR(host->reset) == -EPROBE_DEFER) 1313 return PTR_ERR(host->reset); 1314 1315 ret = sunxi_mmc_enable(host); 1316 if (ret) 1317 return ret; 1318 1319 host->irq = platform_get_irq(pdev, 0); 1320 if (host->irq < 0) { 1321 ret = host->irq; 1322 goto error_disable_mmc; 1323 } 1324 1325 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 1326 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 1327 1328error_disable_mmc: 1329 sunxi_mmc_disable(host); 1330 return ret; 1331} 1332 1333static int sunxi_mmc_probe(struct platform_device *pdev) 1334{ 1335 struct sunxi_mmc_host *host; 1336 struct mmc_host *mmc; 1337 int ret; 1338 1339 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1340 if (!mmc) { 1341 dev_err(&pdev->dev, "mmc alloc host failed\n"); 1342 return -ENOMEM; 1343 } 1344 platform_set_drvdata(pdev, mmc); 1345 1346 host = mmc_priv(mmc); 1347 host->dev = &pdev->dev; 1348 host->mmc = mmc; 1349 spin_lock_init(&host->lock); 1350 1351 ret = sunxi_mmc_resource_request(host, pdev); 1352 if (ret) 1353 goto error_free_host; 1354 1355 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1356 &host->sg_dma, GFP_KERNEL); 1357 if (!host->sg_cpu) { 1358 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1359 ret = -ENOMEM; 1360 goto error_free_host; 1361 } 1362 1363 if (host->cfg->ccu_has_timings_switch) { 1364 /* 1365 * Supports both old and new timing modes. 1366 * Try setting the clk to new timing mode. 1367 */ 1368 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1369 1370 /* And check the result */ 1371 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1372 if (ret < 0) { 1373 /* 1374 * For whatever reason we were not able to get 1375 * the current active mode. Default to old mode. 1376 */ 1377 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1378 host->use_new_timings = false; 1379 } else { 1380 host->use_new_timings = !!ret; 1381 } 1382 } else if (host->cfg->needs_new_timings) { 1383 /* Supports new timing mode only */ 1384 host->use_new_timings = true; 1385 } 1386 1387 mmc->ops = &sunxi_mmc_ops; 1388 mmc->max_blk_count = 8192; 1389 mmc->max_blk_size = 4096; 1390 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 1391 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 1392 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1393 /* 400kHz ~ 52MHz */ 1394 mmc->f_min = 400000; 1395 mmc->f_max = 52000000; 1396 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1397 MMC_CAP_SDIO_IRQ; 1398 1399 /* 1400 * Some H5 devices do not have signal traces precise enough to 1401 * use HS DDR mode for their eMMC chips. 1402 * 1403 * We still enable HS DDR modes for all the other controller 1404 * variants that support them. 1405 */ 1406 if ((host->cfg->clk_delays || host->use_new_timings) && 1407 !of_device_is_compatible(pdev->dev.of_node, 1408 "allwinner,sun50i-h5-emmc")) 1409 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1410 1411 ret = mmc_of_parse(mmc); 1412 if (ret) 1413 goto error_free_dma; 1414 1415 /* 1416 * If we don't support delay chains in the SoC, we can't use any 1417 * of the higher speed modes. Mask them out in case the device 1418 * tree specifies the properties for them, which gets added to 1419 * the caps by mmc_of_parse() above. 1420 */ 1421 if (!(host->cfg->clk_delays || host->use_new_timings)) { 1422 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | 1423 MMC_CAP_1_2V_DDR | MMC_CAP_UHS); 1424 mmc->caps2 &= ~MMC_CAP2_HS200; 1425 } 1426 1427 /* TODO: This driver doesn't support HS400 mode yet */ 1428 mmc->caps2 &= ~MMC_CAP2_HS400; 1429 1430 ret = sunxi_mmc_init_host(host); 1431 if (ret) 1432 goto error_free_dma; 1433 1434 pm_runtime_set_active(&pdev->dev); 1435 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1436 pm_runtime_use_autosuspend(&pdev->dev); 1437 pm_runtime_enable(&pdev->dev); 1438 1439 ret = mmc_add_host(mmc); 1440 if (ret) 1441 goto error_free_dma; 1442 1443 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", 1444 mmc->max_req_size >> 10, 1445 host->use_new_timings ? ", uses new timings mode" : ""); 1446 1447 return 0; 1448 1449error_free_dma: 1450 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1451error_free_host: 1452 mmc_free_host(mmc); 1453 return ret; 1454} 1455 1456static int sunxi_mmc_remove(struct platform_device *pdev) 1457{ 1458 struct mmc_host *mmc = platform_get_drvdata(pdev); 1459 struct sunxi_mmc_host *host = mmc_priv(mmc); 1460 1461 mmc_remove_host(mmc); 1462 pm_runtime_disable(&pdev->dev); 1463 if (!pm_runtime_status_suspended(&pdev->dev)) { 1464 disable_irq(host->irq); 1465 sunxi_mmc_disable(host); 1466 } 1467 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1468 mmc_free_host(mmc); 1469 1470 return 0; 1471} 1472 1473#ifdef CONFIG_PM 1474static int sunxi_mmc_runtime_resume(struct device *dev) 1475{ 1476 struct mmc_host *mmc = dev_get_drvdata(dev); 1477 struct sunxi_mmc_host *host = mmc_priv(mmc); 1478 int ret; 1479 1480 ret = sunxi_mmc_enable(host); 1481 if (ret) 1482 return ret; 1483 1484 sunxi_mmc_init_host(host); 1485 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); 1486 sunxi_mmc_set_clk(host, &mmc->ios); 1487 enable_irq(host->irq); 1488 1489 return 0; 1490} 1491 1492static int sunxi_mmc_runtime_suspend(struct device *dev) 1493{ 1494 struct mmc_host *mmc = dev_get_drvdata(dev); 1495 struct sunxi_mmc_host *host = mmc_priv(mmc); 1496 1497 /* 1498 * When clocks are off, it's possible receiving 1499 * fake interrupts, which will stall the system. 1500 * Disabling the irq will prevent this. 1501 */ 1502 disable_irq(host->irq); 1503 sunxi_mmc_reset_host(host); 1504 sunxi_mmc_disable(host); 1505 1506 return 0; 1507} 1508#endif 1509 1510static const struct dev_pm_ops sunxi_mmc_pm_ops = { 1511 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, 1512 sunxi_mmc_runtime_resume, 1513 NULL) 1514}; 1515 1516static struct platform_driver sunxi_mmc_driver = { 1517 .driver = { 1518 .name = "sunxi-mmc", 1519 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1520 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1521 .pm = &sunxi_mmc_pm_ops, 1522 }, 1523 .probe = sunxi_mmc_probe, 1524 .remove = sunxi_mmc_remove, 1525}; 1526module_platform_driver(sunxi_mmc_driver); 1527 1528MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1529MODULE_LICENSE("GPL v2"); 1530MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 1531MODULE_ALIAS("platform:sunxi-mmc"); 1532