1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7#include <linux/module.h> 8#include <linux/clk.h> 9#include <linux/delay.h> 10#include <linux/dma-mapping.h> 11#include <linux/iopoll.h> 12#include <linux/ioport.h> 13#include <linux/irq.h> 14#include <linux/of_address.h> 15#include <linux/of_device.h> 16#include <linux/of_irq.h> 17#include <linux/of_gpio.h> 18#include <linux/pinctrl/consumer.h> 19#include <linux/platform_device.h> 20#include <linux/pm.h> 21#include <linux/pm_runtime.h> 22#include <linux/regulator/consumer.h> 23#include <linux/slab.h> 24#include <linux/spinlock.h> 25#include <linux/interrupt.h> 26#include <linux/reset.h> 27 28#include <linux/mmc/card.h> 29#include <linux/mmc/core.h> 30#include <linux/mmc/host.h> 31#include <linux/mmc/mmc.h> 32#include <linux/mmc/sd.h> 33#include <linux/mmc/sdio.h> 34#include <linux/mmc/slot-gpio.h> 35 36#include "cqhci.h" 37 38#define MAX_BD_NUM 1024 39 40/*--------------------------------------------------------------------------*/ 41/* Common Definition */ 42/*--------------------------------------------------------------------------*/ 43#define MSDC_BUS_1BITS 0x0 44#define MSDC_BUS_4BITS 0x1 45#define MSDC_BUS_8BITS 0x2 46 47#define MSDC_BURST_64B 0x6 48 49/*--------------------------------------------------------------------------*/ 50/* Register Offset */ 51/*--------------------------------------------------------------------------*/ 52#define MSDC_CFG 0x0 53#define MSDC_IOCON 0x04 54#define MSDC_PS 0x08 55#define MSDC_INT 0x0c 56#define MSDC_INTEN 0x10 57#define MSDC_FIFOCS 0x14 58#define SDC_CFG 0x30 59#define SDC_CMD 0x34 60#define SDC_ARG 0x38 61#define SDC_STS 0x3c 62#define SDC_RESP0 0x40 63#define SDC_RESP1 0x44 64#define SDC_RESP2 0x48 65#define SDC_RESP3 0x4c 66#define SDC_BLK_NUM 0x50 67#define SDC_ADV_CFG0 0x64 68#define EMMC_IOCON 0x7c 69#define SDC_ACMD_RESP 0x80 70#define DMA_SA_H4BIT 0x8c 71#define MSDC_DMA_SA 0x90 72#define MSDC_DMA_CTRL 0x98 73#define MSDC_DMA_CFG 0x9c 74#define MSDC_PATCH_BIT 0xb0 75#define MSDC_PATCH_BIT1 0xb4 76#define MSDC_PATCH_BIT2 0xb8 77#define MSDC_PAD_TUNE 0xec 78#define MSDC_PAD_TUNE0 0xf0 79#define PAD_DS_TUNE 0x188 80#define PAD_CMD_TUNE 0x18c 81#define EMMC50_CFG0 0x208 82#define EMMC50_CFG3 0x220 83#define SDC_FIFO_CFG 0x228 84 85/*--------------------------------------------------------------------------*/ 86/* Top Pad Register Offset */ 87/*--------------------------------------------------------------------------*/ 88#define EMMC_TOP_CONTROL 0x00 89#define EMMC_TOP_CMD 0x04 90#define EMMC50_PAD_DS_TUNE 0x0c 91 92/*--------------------------------------------------------------------------*/ 93/* Register Mask */ 94/*--------------------------------------------------------------------------*/ 95 96/* MSDC_CFG mask */ 97#define MSDC_CFG_MODE (0x1 << 0) /* RW */ 98#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 99#define MSDC_CFG_RST (0x1 << 2) /* RW */ 100#define MSDC_CFG_PIO (0x1 << 3) /* RW */ 101#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 102#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 103#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 104#define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 105#define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 106#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 107#define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 108#define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 109#define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 110#define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 111 112/* MSDC_IOCON mask */ 113#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 114#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 115#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 116#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 117#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 118#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 119#define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 120#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 121#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 122#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 123#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 124#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 125#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 126#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 127#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 128#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 129 130/* MSDC_PS mask */ 131#define MSDC_PS_CDEN (0x1 << 0) /* RW */ 132#define MSDC_PS_CDSTS (0x1 << 1) /* R */ 133#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 134#define MSDC_PS_DAT (0xff << 16) /* R */ 135#define MSDC_PS_DATA1 (0x1 << 17) /* R */ 136#define MSDC_PS_CMD (0x1 << 24) /* R */ 137#define MSDC_PS_WP (0x1 << 31) /* R */ 138 139/* MSDC_INT mask */ 140#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 141#define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 142#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 143#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 144#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 145#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 146#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 147#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 148#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 149#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 150#define MSDC_INT_CSTA (0x1 << 11) /* R */ 151#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 152#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 153#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 154#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 155#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 156#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 157#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 158#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 159#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 160 161/* MSDC_INTEN mask */ 162#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 163#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 164#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 165#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 166#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 167#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 168#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 169#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 170#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 171#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 172#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 173#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 174#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 175#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 176#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 177#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 178#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 179#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 180#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 181 182/* MSDC_FIFOCS mask */ 183#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 184#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 185#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 186 187/* SDC_CFG mask */ 188#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 189#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 190#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 191#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 192#define SDC_CFG_SDIO (0x1 << 19) /* RW */ 193#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 194#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 195#define SDC_CFG_DTOC (0xff << 24) /* RW */ 196 197/* SDC_STS mask */ 198#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 199#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 200#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 201 202#define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 203/* SDC_ADV_CFG0 mask */ 204#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 205 206/* DMA_SA_H4BIT mask */ 207#define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 208 209/* MSDC_DMA_CTRL mask */ 210#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 211#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 212#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 213#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 214#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 215#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 216 217/* MSDC_DMA_CFG mask */ 218#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 219#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 220#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 221#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 222#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 223 224/* MSDC_PATCH_BIT mask */ 225#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 226#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 227#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 228#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 229#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 230#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 231#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 232#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 233#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 234#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 235#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 236#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 237 238#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 239#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 240#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 241 242#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 243#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 244#define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 245#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 246#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 247#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 248 249#define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 250#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 251#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 252#define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 253#define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 254#define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 255#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 256#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 257 258#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 259#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 260#define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 261 262#define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 263 264#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 265#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 266#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 267 268#define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 269 270#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 271#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 272 273/* EMMC_TOP_CONTROL mask */ 274#define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 275#define DELAY_EN (0x1 << 1) /* RW */ 276#define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 277#define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 278#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 279#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 280#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 281#define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 282 283/* EMMC_TOP_CMD mask */ 284#define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 285#define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 286#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 287#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 288#define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 289 290#define REQ_CMD_EIO (0x1 << 0) 291#define REQ_CMD_TMO (0x1 << 1) 292#define REQ_DAT_ERR (0x1 << 2) 293#define REQ_STOP_EIO (0x1 << 3) 294#define REQ_STOP_TMO (0x1 << 4) 295#define REQ_CMD_BUSY (0x1 << 5) 296 297#define MSDC_PREPARE_FLAG (0x1 << 0) 298#define MSDC_ASYNC_FLAG (0x1 << 1) 299#define MSDC_MMAP_FLAG (0x1 << 2) 300 301#define MTK_MMC_AUTOSUSPEND_DELAY 50 302#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 303#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 304 305#define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 306 307#define PAD_DELAY_MAX 32 /* PAD delay cells */ 308/*--------------------------------------------------------------------------*/ 309/* Descriptor Structure */ 310/*--------------------------------------------------------------------------*/ 311struct mt_gpdma_desc { 312 u32 gpd_info; 313#define GPDMA_DESC_HWO (0x1 << 0) 314#define GPDMA_DESC_BDP (0x1 << 1) 315#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 316#define GPDMA_DESC_INT (0x1 << 16) 317#define GPDMA_DESC_NEXT_H4 (0xf << 24) 318#define GPDMA_DESC_PTR_H4 (0xf << 28) 319 u32 next; 320 u32 ptr; 321 u32 gpd_data_len; 322#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 323#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 324 u32 arg; 325 u32 blknum; 326 u32 cmd; 327}; 328 329struct mt_bdma_desc { 330 u32 bd_info; 331#define BDMA_DESC_EOL (0x1 << 0) 332#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 333#define BDMA_DESC_BLKPAD (0x1 << 17) 334#define BDMA_DESC_DWPAD (0x1 << 18) 335#define BDMA_DESC_NEXT_H4 (0xf << 24) 336#define BDMA_DESC_PTR_H4 (0xf << 28) 337 u32 next; 338 u32 ptr; 339 u32 bd_data_len; 340#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 341#define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 342}; 343 344struct msdc_dma { 345 struct scatterlist *sg; /* I/O scatter list */ 346 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 347 struct mt_bdma_desc *bd; /* pointer to bd array */ 348 dma_addr_t gpd_addr; /* the physical address of gpd array */ 349 dma_addr_t bd_addr; /* the physical address of bd array */ 350}; 351 352struct msdc_save_para { 353 u32 msdc_cfg; 354 u32 iocon; 355 u32 sdc_cfg; 356 u32 pad_tune; 357 u32 patch_bit0; 358 u32 patch_bit1; 359 u32 patch_bit2; 360 u32 pad_ds_tune; 361 u32 pad_cmd_tune; 362 u32 emmc50_cfg0; 363 u32 emmc50_cfg3; 364 u32 sdc_fifo_cfg; 365 u32 emmc_top_control; 366 u32 emmc_top_cmd; 367 u32 emmc50_pad_ds_tune; 368}; 369 370struct mtk_mmc_compatible { 371 u8 clk_div_bits; 372 bool recheck_sdio_irq; 373 bool hs400_tune; /* only used for MT8173 */ 374 u32 pad_tune_reg; 375 bool async_fifo; 376 bool data_tune; 377 bool busy_check; 378 bool stop_clk_fix; 379 bool enhance_rx; 380 bool support_64g; 381 bool use_internal_cd; 382}; 383 384struct msdc_tune_para { 385 u32 iocon; 386 u32 pad_tune; 387 u32 pad_cmd_tune; 388 u32 emmc_top_control; 389 u32 emmc_top_cmd; 390}; 391 392struct msdc_delay_phase { 393 u8 maxlen; 394 u8 start; 395 u8 final_phase; 396}; 397 398struct msdc_host { 399 struct device *dev; 400 const struct mtk_mmc_compatible *dev_comp; 401 int cmd_rsp; 402 403 spinlock_t lock; 404 struct mmc_request *mrq; 405 struct mmc_command *cmd; 406 struct mmc_data *data; 407 int error; 408 409 void __iomem *base; /* host base address */ 410 void __iomem *top_base; /* host top register base address */ 411 412 struct msdc_dma dma; /* dma channel */ 413 u64 dma_mask; 414 415 u32 timeout_ns; /* data timeout ns */ 416 u32 timeout_clks; /* data timeout clks */ 417 418 struct pinctrl *pinctrl; 419 struct pinctrl_state *pins_default; 420 struct pinctrl_state *pins_uhs; 421 struct delayed_work req_timeout; 422 int irq; /* host interrupt */ 423 struct reset_control *reset; 424 425 struct clk *src_clk; /* msdc source clock */ 426 struct clk *h_clk; /* msdc h_clk */ 427 struct clk *bus_clk; /* bus clock which used to access register */ 428 struct clk *src_clk_cg; /* msdc source clock control gate */ 429 u32 mclk; /* mmc subsystem clock frequency */ 430 u32 src_clk_freq; /* source clock frequency */ 431 unsigned char timing; 432 bool vqmmc_enabled; 433 u32 latch_ck; 434 u32 hs400_ds_delay; 435 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 436 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 437 bool hs400_cmd_resp_sel_rising; 438 /* cmd response sample selection for HS400 */ 439 bool hs400_mode; /* current eMMC will run at hs400 mode */ 440 bool internal_cd; /* Use internal card-detect logic */ 441 bool cqhci; /* support eMMC hw cmdq */ 442 struct msdc_save_para save_para; /* used when gate HCLK */ 443 struct msdc_tune_para def_tune_para; /* default tune setting */ 444 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 445 struct cqhci_host *cq_host; 446}; 447 448static const struct mtk_mmc_compatible mt8135_compat = { 449 .clk_div_bits = 8, 450 .recheck_sdio_irq = true, 451 .hs400_tune = false, 452 .pad_tune_reg = MSDC_PAD_TUNE, 453 .async_fifo = false, 454 .data_tune = false, 455 .busy_check = false, 456 .stop_clk_fix = false, 457 .enhance_rx = false, 458 .support_64g = false, 459}; 460 461static const struct mtk_mmc_compatible mt8173_compat = { 462 .clk_div_bits = 8, 463 .recheck_sdio_irq = true, 464 .hs400_tune = true, 465 .pad_tune_reg = MSDC_PAD_TUNE, 466 .async_fifo = false, 467 .data_tune = false, 468 .busy_check = false, 469 .stop_clk_fix = false, 470 .enhance_rx = false, 471 .support_64g = false, 472}; 473 474static const struct mtk_mmc_compatible mt8183_compat = { 475 .clk_div_bits = 12, 476 .recheck_sdio_irq = false, 477 .hs400_tune = false, 478 .pad_tune_reg = MSDC_PAD_TUNE0, 479 .async_fifo = true, 480 .data_tune = true, 481 .busy_check = true, 482 .stop_clk_fix = true, 483 .enhance_rx = true, 484 .support_64g = true, 485}; 486 487static const struct mtk_mmc_compatible mt2701_compat = { 488 .clk_div_bits = 12, 489 .recheck_sdio_irq = true, 490 .hs400_tune = false, 491 .pad_tune_reg = MSDC_PAD_TUNE0, 492 .async_fifo = true, 493 .data_tune = true, 494 .busy_check = false, 495 .stop_clk_fix = false, 496 .enhance_rx = false, 497 .support_64g = false, 498}; 499 500static const struct mtk_mmc_compatible mt2712_compat = { 501 .clk_div_bits = 12, 502 .recheck_sdio_irq = false, 503 .hs400_tune = false, 504 .pad_tune_reg = MSDC_PAD_TUNE0, 505 .async_fifo = true, 506 .data_tune = true, 507 .busy_check = true, 508 .stop_clk_fix = true, 509 .enhance_rx = true, 510 .support_64g = true, 511}; 512 513static const struct mtk_mmc_compatible mt7622_compat = { 514 .clk_div_bits = 12, 515 .recheck_sdio_irq = true, 516 .hs400_tune = false, 517 .pad_tune_reg = MSDC_PAD_TUNE0, 518 .async_fifo = true, 519 .data_tune = true, 520 .busy_check = true, 521 .stop_clk_fix = true, 522 .enhance_rx = true, 523 .support_64g = false, 524}; 525 526static const struct mtk_mmc_compatible mt8516_compat = { 527 .clk_div_bits = 12, 528 .recheck_sdio_irq = true, 529 .hs400_tune = false, 530 .pad_tune_reg = MSDC_PAD_TUNE0, 531 .async_fifo = true, 532 .data_tune = true, 533 .busy_check = true, 534 .stop_clk_fix = true, 535}; 536 537static const struct mtk_mmc_compatible mt7620_compat = { 538 .clk_div_bits = 8, 539 .recheck_sdio_irq = true, 540 .hs400_tune = false, 541 .pad_tune_reg = MSDC_PAD_TUNE, 542 .async_fifo = false, 543 .data_tune = false, 544 .busy_check = false, 545 .stop_clk_fix = false, 546 .enhance_rx = false, 547 .use_internal_cd = true, 548}; 549 550static const struct mtk_mmc_compatible mt6779_compat = { 551 .clk_div_bits = 12, 552 .recheck_sdio_irq = false, 553 .hs400_tune = false, 554 .pad_tune_reg = MSDC_PAD_TUNE0, 555 .async_fifo = true, 556 .data_tune = true, 557 .busy_check = true, 558 .stop_clk_fix = true, 559 .enhance_rx = true, 560 .support_64g = true, 561}; 562 563static const struct of_device_id msdc_of_ids[] = { 564 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 565 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 566 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 567 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 568 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 569 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 570 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 571 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 572 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 573 {} 574}; 575MODULE_DEVICE_TABLE(of, msdc_of_ids); 576 577static void sdr_set_bits(void __iomem *reg, u32 bs) 578{ 579 u32 val = readl(reg); 580 581 val |= bs; 582 writel(val, reg); 583} 584 585static void sdr_clr_bits(void __iomem *reg, u32 bs) 586{ 587 u32 val = readl(reg); 588 589 val &= ~bs; 590 writel(val, reg); 591} 592 593static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 594{ 595 unsigned int tv = readl(reg); 596 597 tv &= ~field; 598 tv |= ((val) << (ffs((unsigned int)field) - 1)); 599 writel(tv, reg); 600} 601 602static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 603{ 604 unsigned int tv = readl(reg); 605 606 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 607} 608 609static void msdc_reset_hw(struct msdc_host *host) 610{ 611 u32 val; 612 613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 614 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 615 cpu_relax(); 616 617 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 618 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 619 cpu_relax(); 620 621 val = readl(host->base + MSDC_INT); 622 writel(val, host->base + MSDC_INT); 623} 624 625static void msdc_cmd_next(struct msdc_host *host, 626 struct mmc_request *mrq, struct mmc_command *cmd); 627static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 628 629static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 630 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 631 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 632static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 633 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 634 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 635 636static u8 msdc_dma_calcs(u8 *buf, u32 len) 637{ 638 u32 i, sum = 0; 639 640 for (i = 0; i < len; i++) 641 sum += buf[i]; 642 return 0xff - (u8) sum; 643} 644 645static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 646 struct mmc_data *data) 647{ 648 unsigned int j, dma_len; 649 dma_addr_t dma_address; 650 u32 dma_ctrl; 651 struct scatterlist *sg; 652 struct mt_gpdma_desc *gpd; 653 struct mt_bdma_desc *bd; 654 655 sg = data->sg; 656 657 gpd = dma->gpd; 658 bd = dma->bd; 659 660 /* modify gpd */ 661 gpd->gpd_info |= GPDMA_DESC_HWO; 662 gpd->gpd_info |= GPDMA_DESC_BDP; 663 /* need to clear first. use these bits to calc checksum */ 664 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 665 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 666 667 /* modify bd */ 668 for_each_sg(data->sg, sg, data->sg_count, j) { 669 dma_address = sg_dma_address(sg); 670 dma_len = sg_dma_len(sg); 671 672 /* init bd */ 673 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 674 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 675 bd[j].ptr = lower_32_bits(dma_address); 676 if (host->dev_comp->support_64g) { 677 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 678 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 679 << 28; 680 } 681 682 if (host->dev_comp->support_64g) { 683 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 684 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 685 } else { 686 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 687 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 688 } 689 690 if (j == data->sg_count - 1) /* the last bd */ 691 bd[j].bd_info |= BDMA_DESC_EOL; 692 else 693 bd[j].bd_info &= ~BDMA_DESC_EOL; 694 695 /* checksume need to clear first */ 696 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 697 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 698 } 699 700 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 701 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 702 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 703 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 704 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 705 if (host->dev_comp->support_64g) 706 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 707 upper_32_bits(dma->gpd_addr) & 0xf); 708 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 709} 710 711static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 712{ 713 struct mmc_data *data = mrq->data; 714 715 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 716 data->host_cookie |= MSDC_PREPARE_FLAG; 717 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 718 mmc_get_dma_dir(data)); 719 } 720} 721 722static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 723{ 724 struct mmc_data *data = mrq->data; 725 726 if (data->host_cookie & MSDC_ASYNC_FLAG) 727 return; 728 729 if (data->host_cookie & MSDC_PREPARE_FLAG) { 730 dma_unmap_sg(host->dev, data->sg, data->sg_len, 731 mmc_get_dma_dir(data)); 732 data->host_cookie &= ~MSDC_PREPARE_FLAG; 733 } 734} 735 736static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 737{ 738 struct mmc_host *mmc = mmc_from_priv(host); 739 u64 timeout, clk_ns; 740 u32 mode = 0; 741 742 if (mmc->actual_clock == 0) { 743 timeout = 0; 744 } else { 745 clk_ns = 1000000000ULL; 746 do_div(clk_ns, mmc->actual_clock); 747 timeout = ns + clk_ns - 1; 748 do_div(timeout, clk_ns); 749 timeout += clks; 750 /* in 1048576 sclk cycle unit */ 751 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 752 if (host->dev_comp->clk_div_bits == 8) 753 sdr_get_field(host->base + MSDC_CFG, 754 MSDC_CFG_CKMOD, &mode); 755 else 756 sdr_get_field(host->base + MSDC_CFG, 757 MSDC_CFG_CKMOD_EXTRA, &mode); 758 /*DDR mode will double the clk cycles for data timeout */ 759 timeout = mode >= 2 ? timeout * 2 : timeout; 760 timeout = timeout > 1 ? timeout - 1 : 0; 761 } 762 return timeout; 763} 764 765/* clock control primitives */ 766static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 767{ 768 u64 timeout; 769 770 host->timeout_ns = ns; 771 host->timeout_clks = clks; 772 773 timeout = msdc_timeout_cal(host, ns, clks); 774 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 775 (u32)(timeout > 255 ? 255 : timeout)); 776} 777 778static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 779{ 780 u64 timeout; 781 782 timeout = msdc_timeout_cal(host, ns, clks); 783 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 784 (u32)(timeout > 8191 ? 8191 : timeout)); 785} 786 787static void msdc_gate_clock(struct msdc_host *host) 788{ 789 clk_disable_unprepare(host->src_clk_cg); 790 clk_disable_unprepare(host->src_clk); 791 clk_disable_unprepare(host->bus_clk); 792 clk_disable_unprepare(host->h_clk); 793} 794 795static void msdc_ungate_clock(struct msdc_host *host) 796{ 797 clk_prepare_enable(host->h_clk); 798 clk_prepare_enable(host->bus_clk); 799 clk_prepare_enable(host->src_clk); 800 clk_prepare_enable(host->src_clk_cg); 801 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 802 cpu_relax(); 803} 804 805static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 806{ 807 struct mmc_host *mmc = mmc_from_priv(host); 808 u32 mode; 809 u32 flags; 810 u32 div; 811 u32 sclk; 812 u32 tune_reg = host->dev_comp->pad_tune_reg; 813 814 if (!hz) { 815 dev_dbg(host->dev, "set mclk to 0\n"); 816 host->mclk = 0; 817 mmc->actual_clock = 0; 818 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 819 return; 820 } 821 822 flags = readl(host->base + MSDC_INTEN); 823 sdr_clr_bits(host->base + MSDC_INTEN, flags); 824 if (host->dev_comp->clk_div_bits == 8) 825 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 826 else 827 sdr_clr_bits(host->base + MSDC_CFG, 828 MSDC_CFG_HS400_CK_MODE_EXTRA); 829 if (timing == MMC_TIMING_UHS_DDR50 || 830 timing == MMC_TIMING_MMC_DDR52 || 831 timing == MMC_TIMING_MMC_HS400) { 832 if (timing == MMC_TIMING_MMC_HS400) 833 mode = 0x3; 834 else 835 mode = 0x2; /* ddr mode and use divisor */ 836 837 if (hz >= (host->src_clk_freq >> 2)) { 838 div = 0; /* mean div = 1/4 */ 839 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 840 } else { 841 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 842 sclk = (host->src_clk_freq >> 2) / div; 843 div = (div >> 1); 844 } 845 846 if (timing == MMC_TIMING_MMC_HS400 && 847 hz >= (host->src_clk_freq >> 1)) { 848 if (host->dev_comp->clk_div_bits == 8) 849 sdr_set_bits(host->base + MSDC_CFG, 850 MSDC_CFG_HS400_CK_MODE); 851 else 852 sdr_set_bits(host->base + MSDC_CFG, 853 MSDC_CFG_HS400_CK_MODE_EXTRA); 854 sclk = host->src_clk_freq >> 1; 855 div = 0; /* div is ignore when bit18 is set */ 856 } 857 } else if (hz >= host->src_clk_freq) { 858 mode = 0x1; /* no divisor */ 859 div = 0; 860 sclk = host->src_clk_freq; 861 } else { 862 mode = 0x0; /* use divisor */ 863 if (hz >= (host->src_clk_freq >> 1)) { 864 div = 0; /* mean div = 1/2 */ 865 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 866 } else { 867 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 868 sclk = (host->src_clk_freq >> 2) / div; 869 } 870 } 871 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 872 /* 873 * As src_clk/HCLK use the same bit to gate/ungate, 874 * So if want to only gate src_clk, need gate its parent(mux). 875 */ 876 if (host->src_clk_cg) 877 clk_disable_unprepare(host->src_clk_cg); 878 else 879 clk_disable_unprepare(clk_get_parent(host->src_clk)); 880 if (host->dev_comp->clk_div_bits == 8) 881 sdr_set_field(host->base + MSDC_CFG, 882 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 883 (mode << 8) | div); 884 else 885 sdr_set_field(host->base + MSDC_CFG, 886 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 887 (mode << 12) | div); 888 if (host->src_clk_cg) 889 clk_prepare_enable(host->src_clk_cg); 890 else 891 clk_prepare_enable(clk_get_parent(host->src_clk)); 892 893 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 894 cpu_relax(); 895 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 896 mmc->actual_clock = sclk; 897 host->mclk = hz; 898 host->timing = timing; 899 /* need because clk changed. */ 900 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 901 sdr_set_bits(host->base + MSDC_INTEN, flags); 902 903 /* 904 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 905 * tune result of hs200/200Mhz is not suitable for 50Mhz 906 */ 907 if (mmc->actual_clock <= 52000000) { 908 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 909 if (host->top_base) { 910 writel(host->def_tune_para.emmc_top_control, 911 host->top_base + EMMC_TOP_CONTROL); 912 writel(host->def_tune_para.emmc_top_cmd, 913 host->top_base + EMMC_TOP_CMD); 914 } else { 915 writel(host->def_tune_para.pad_tune, 916 host->base + tune_reg); 917 } 918 } else { 919 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 920 writel(host->saved_tune_para.pad_cmd_tune, 921 host->base + PAD_CMD_TUNE); 922 if (host->top_base) { 923 writel(host->saved_tune_para.emmc_top_control, 924 host->top_base + EMMC_TOP_CONTROL); 925 writel(host->saved_tune_para.emmc_top_cmd, 926 host->top_base + EMMC_TOP_CMD); 927 } else { 928 writel(host->saved_tune_para.pad_tune, 929 host->base + tune_reg); 930 } 931 } 932 933 if (timing == MMC_TIMING_MMC_HS400 && 934 host->dev_comp->hs400_tune) 935 sdr_set_field(host->base + tune_reg, 936 MSDC_PAD_TUNE_CMDRRDLY, 937 host->hs400_cmd_int_delay); 938 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 939 timing); 940} 941 942static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 943 struct mmc_request *mrq, struct mmc_command *cmd) 944{ 945 u32 resp; 946 947 switch (mmc_resp_type(cmd)) { 948 /* Actually, R1, R5, R6, R7 are the same */ 949 case MMC_RSP_R1: 950 resp = 0x1; 951 break; 952 case MMC_RSP_R1B: 953 resp = 0x7; 954 break; 955 case MMC_RSP_R2: 956 resp = 0x2; 957 break; 958 case MMC_RSP_R3: 959 resp = 0x3; 960 break; 961 case MMC_RSP_NONE: 962 default: 963 resp = 0x0; 964 break; 965 } 966 967 return resp; 968} 969 970static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 971 struct mmc_request *mrq, struct mmc_command *cmd) 972{ 973 struct mmc_host *mmc = mmc_from_priv(host); 974 /* rawcmd : 975 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 976 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 977 */ 978 u32 opcode = cmd->opcode; 979 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 980 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 981 982 host->cmd_rsp = resp; 983 984 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 985 opcode == MMC_STOP_TRANSMISSION) 986 rawcmd |= (0x1 << 14); 987 else if (opcode == SD_SWITCH_VOLTAGE) 988 rawcmd |= (0x1 << 30); 989 else if (opcode == SD_APP_SEND_SCR || 990 opcode == SD_APP_SEND_NUM_WR_BLKS || 991 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 992 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 993 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 994 rawcmd |= (0x1 << 11); 995 996 if (cmd->data) { 997 struct mmc_data *data = cmd->data; 998 999 if (mmc_op_multi(opcode)) { 1000 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1001 !(mrq->sbc->arg & 0xFFFF0000)) 1002 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1003 } 1004 1005 rawcmd |= ((data->blksz & 0xFFF) << 16); 1006 if (data->flags & MMC_DATA_WRITE) 1007 rawcmd |= (0x1 << 13); 1008 if (data->blocks > 1) 1009 rawcmd |= (0x2 << 11); 1010 else 1011 rawcmd |= (0x1 << 11); 1012 /* Always use dma mode */ 1013 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1014 1015 if (host->timeout_ns != data->timeout_ns || 1016 host->timeout_clks != data->timeout_clks) 1017 msdc_set_timeout(host, data->timeout_ns, 1018 data->timeout_clks); 1019 1020 writel(data->blocks, host->base + SDC_BLK_NUM); 1021 } 1022 return rawcmd; 1023} 1024 1025static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1026 struct mmc_command *cmd, struct mmc_data *data) 1027{ 1028 bool read; 1029 1030 WARN_ON(host->data); 1031 host->data = data; 1032 read = data->flags & MMC_DATA_READ; 1033 1034 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1035 msdc_dma_setup(host, &host->dma, data); 1036 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1037 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1038 dev_dbg(host->dev, "DMA start\n"); 1039 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1040 __func__, cmd->opcode, data->blocks, read); 1041} 1042 1043static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1044 struct mmc_command *cmd) 1045{ 1046 u32 *rsp = cmd->resp; 1047 1048 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1049 1050 if (events & MSDC_INT_ACMDRDY) { 1051 cmd->error = 0; 1052 } else { 1053 msdc_reset_hw(host); 1054 if (events & MSDC_INT_ACMDCRCERR) { 1055 cmd->error = -EILSEQ; 1056 host->error |= REQ_STOP_EIO; 1057 } else if (events & MSDC_INT_ACMDTMO) { 1058 cmd->error = -ETIMEDOUT; 1059 host->error |= REQ_STOP_TMO; 1060 } 1061 dev_err(host->dev, 1062 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1063 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1064 } 1065 return cmd->error; 1066} 1067 1068/* 1069 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1070 * 1071 * Host controller may lost interrupt in some special case. 1072 * Add SDIO irq recheck mechanism to make sure all interrupts 1073 * can be processed immediately 1074 */ 1075static void msdc_recheck_sdio_irq(struct msdc_host *host) 1076{ 1077 struct mmc_host *mmc = mmc_from_priv(host); 1078 u32 reg_int, reg_inten, reg_ps; 1079 1080 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1081 reg_inten = readl(host->base + MSDC_INTEN); 1082 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1083 reg_int = readl(host->base + MSDC_INT); 1084 reg_ps = readl(host->base + MSDC_PS); 1085 if (!(reg_int & MSDC_INT_SDIOIRQ || 1086 reg_ps & MSDC_PS_DATA1)) { 1087 __msdc_enable_sdio_irq(host, 0); 1088 sdio_signal_irq(mmc); 1089 } 1090 } 1091 } 1092} 1093 1094static void msdc_track_cmd_data(struct msdc_host *host, 1095 struct mmc_command *cmd, struct mmc_data *data) 1096{ 1097 if (host->error) 1098 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1099 __func__, cmd->opcode, cmd->arg, host->error); 1100} 1101 1102static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1103{ 1104 unsigned long flags; 1105 1106 /* 1107 * No need check the return value of cancel_delayed_work, as only ONE 1108 * path will go here! 1109 */ 1110 cancel_delayed_work(&host->req_timeout); 1111 1112 spin_lock_irqsave(&host->lock, flags); 1113 host->mrq = NULL; 1114 spin_unlock_irqrestore(&host->lock, flags); 1115 1116 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1117 if (mrq->data) 1118 msdc_unprepare_data(host, mrq); 1119 if (host->error) 1120 msdc_reset_hw(host); 1121 mmc_request_done(mmc_from_priv(host), mrq); 1122 if (host->dev_comp->recheck_sdio_irq) 1123 msdc_recheck_sdio_irq(host); 1124} 1125 1126/* returns true if command is fully handled; returns false otherwise */ 1127static bool msdc_cmd_done(struct msdc_host *host, int events, 1128 struct mmc_request *mrq, struct mmc_command *cmd) 1129{ 1130 bool done = false; 1131 bool sbc_error; 1132 unsigned long flags; 1133 u32 *rsp; 1134 1135 if (mrq->sbc && cmd == mrq->cmd && 1136 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1137 | MSDC_INT_ACMDTMO))) 1138 msdc_auto_cmd_done(host, events, mrq->sbc); 1139 1140 sbc_error = mrq->sbc && mrq->sbc->error; 1141 1142 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1143 | MSDC_INT_RSPCRCERR 1144 | MSDC_INT_CMDTMO))) 1145 return done; 1146 1147 spin_lock_irqsave(&host->lock, flags); 1148 done = !host->cmd; 1149 host->cmd = NULL; 1150 spin_unlock_irqrestore(&host->lock, flags); 1151 1152 if (done) 1153 return true; 1154 rsp = cmd->resp; 1155 1156 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1157 1158 if (cmd->flags & MMC_RSP_PRESENT) { 1159 if (cmd->flags & MMC_RSP_136) { 1160 rsp[0] = readl(host->base + SDC_RESP3); 1161 rsp[1] = readl(host->base + SDC_RESP2); 1162 rsp[2] = readl(host->base + SDC_RESP1); 1163 rsp[3] = readl(host->base + SDC_RESP0); 1164 } else { 1165 rsp[0] = readl(host->base + SDC_RESP0); 1166 } 1167 } 1168 1169 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1170 if (events & MSDC_INT_CMDTMO || 1171 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1172 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1173 /* 1174 * should not clear fifo/interrupt as the tune data 1175 * may have alreay come when cmd19/cmd21 gets response 1176 * CRC error. 1177 */ 1178 msdc_reset_hw(host); 1179 if (events & MSDC_INT_RSPCRCERR) { 1180 cmd->error = -EILSEQ; 1181 host->error |= REQ_CMD_EIO; 1182 } else if (events & MSDC_INT_CMDTMO) { 1183 cmd->error = -ETIMEDOUT; 1184 host->error |= REQ_CMD_TMO; 1185 } 1186 } 1187 if (cmd->error) 1188 dev_dbg(host->dev, 1189 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1190 __func__, cmd->opcode, cmd->arg, rsp[0], 1191 cmd->error); 1192 1193 msdc_cmd_next(host, mrq, cmd); 1194 return true; 1195} 1196 1197/* It is the core layer's responsibility to ensure card status 1198 * is correct before issue a request. but host design do below 1199 * checks recommended. 1200 */ 1201static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1202 struct mmc_request *mrq, struct mmc_command *cmd) 1203{ 1204 /* The max busy time we can endure is 20ms */ 1205 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1206 1207 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1208 time_before(jiffies, tmo)) 1209 cpu_relax(); 1210 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1211 dev_err(host->dev, "CMD bus busy detected\n"); 1212 host->error |= REQ_CMD_BUSY; 1213 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1214 return false; 1215 } 1216 1217 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1218 tmo = jiffies + msecs_to_jiffies(20); 1219 /* R1B or with data, should check SDCBUSY */ 1220 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1221 time_before(jiffies, tmo)) 1222 cpu_relax(); 1223 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1224 dev_err(host->dev, "Controller busy detected\n"); 1225 host->error |= REQ_CMD_BUSY; 1226 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1227 return false; 1228 } 1229 } 1230 return true; 1231} 1232 1233static void msdc_start_command(struct msdc_host *host, 1234 struct mmc_request *mrq, struct mmc_command *cmd) 1235{ 1236 u32 rawcmd; 1237 unsigned long flags; 1238 1239 WARN_ON(host->cmd); 1240 host->cmd = cmd; 1241 1242 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1243 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1244 return; 1245 1246 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1247 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1248 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1249 msdc_reset_hw(host); 1250 } 1251 1252 cmd->error = 0; 1253 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1254 1255 spin_lock_irqsave(&host->lock, flags); 1256 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1257 spin_unlock_irqrestore(&host->lock, flags); 1258 1259 writel(cmd->arg, host->base + SDC_ARG); 1260 writel(rawcmd, host->base + SDC_CMD); 1261} 1262 1263static void msdc_cmd_next(struct msdc_host *host, 1264 struct mmc_request *mrq, struct mmc_command *cmd) 1265{ 1266 if ((cmd->error && 1267 !(cmd->error == -EILSEQ && 1268 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1269 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1270 (mrq->sbc && mrq->sbc->error)) 1271 msdc_request_done(host, mrq); 1272 else if (cmd == mrq->sbc) 1273 msdc_start_command(host, mrq, mrq->cmd); 1274 else if (!cmd->data) 1275 msdc_request_done(host, mrq); 1276 else 1277 msdc_start_data(host, mrq, cmd, cmd->data); 1278} 1279 1280static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1281{ 1282 struct msdc_host *host = mmc_priv(mmc); 1283 1284 host->error = 0; 1285 WARN_ON(host->mrq); 1286 host->mrq = mrq; 1287 1288 if (mrq->data) 1289 msdc_prepare_data(host, mrq); 1290 1291 /* if SBC is required, we have HW option and SW option. 1292 * if HW option is enabled, and SBC does not have "special" flags, 1293 * use HW option, otherwise use SW option 1294 */ 1295 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1296 (mrq->sbc->arg & 0xFFFF0000))) 1297 msdc_start_command(host, mrq, mrq->sbc); 1298 else 1299 msdc_start_command(host, mrq, mrq->cmd); 1300} 1301 1302static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1303{ 1304 struct msdc_host *host = mmc_priv(mmc); 1305 struct mmc_data *data = mrq->data; 1306 1307 if (!data) 1308 return; 1309 1310 msdc_prepare_data(host, mrq); 1311 data->host_cookie |= MSDC_ASYNC_FLAG; 1312} 1313 1314static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1315 int err) 1316{ 1317 struct msdc_host *host = mmc_priv(mmc); 1318 struct mmc_data *data; 1319 1320 data = mrq->data; 1321 if (!data) 1322 return; 1323 if (data->host_cookie) { 1324 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1325 msdc_unprepare_data(host, mrq); 1326 } 1327} 1328 1329static void msdc_data_xfer_next(struct msdc_host *host, 1330 struct mmc_request *mrq, struct mmc_data *data) 1331{ 1332 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1333 !mrq->sbc) 1334 msdc_start_command(host, mrq, mrq->stop); 1335 else 1336 msdc_request_done(host, mrq); 1337} 1338 1339static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1340 struct mmc_request *mrq, struct mmc_data *data) 1341{ 1342 struct mmc_command *stop; 1343 unsigned long flags; 1344 bool done; 1345 unsigned int check_data = events & 1346 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1347 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1348 | MSDC_INT_DMA_PROTECT); 1349 1350 spin_lock_irqsave(&host->lock, flags); 1351 done = !host->data; 1352 if (check_data) 1353 host->data = NULL; 1354 spin_unlock_irqrestore(&host->lock, flags); 1355 1356 if (done) 1357 return true; 1358 stop = data->stop; 1359 1360 if (check_data || (stop && stop->error)) { 1361 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1362 readl(host->base + MSDC_DMA_CFG)); 1363 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1364 1); 1365 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1366 cpu_relax(); 1367 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1368 dev_dbg(host->dev, "DMA stop\n"); 1369 1370 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1371 data->bytes_xfered = data->blocks * data->blksz; 1372 } else { 1373 dev_dbg(host->dev, "interrupt events: %x\n", events); 1374 msdc_reset_hw(host); 1375 host->error |= REQ_DAT_ERR; 1376 data->bytes_xfered = 0; 1377 1378 if (events & MSDC_INT_DATTMO) 1379 data->error = -ETIMEDOUT; 1380 else if (events & MSDC_INT_DATCRCERR) 1381 data->error = -EILSEQ; 1382 1383 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1384 __func__, mrq->cmd->opcode, data->blocks); 1385 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1386 (int)data->error, data->bytes_xfered); 1387 } 1388 1389 msdc_data_xfer_next(host, mrq, data); 1390 done = true; 1391 } 1392 return done; 1393} 1394 1395static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1396{ 1397 u32 val = readl(host->base + SDC_CFG); 1398 1399 val &= ~SDC_CFG_BUSWIDTH; 1400 1401 switch (width) { 1402 default: 1403 case MMC_BUS_WIDTH_1: 1404 val |= (MSDC_BUS_1BITS << 16); 1405 break; 1406 case MMC_BUS_WIDTH_4: 1407 val |= (MSDC_BUS_4BITS << 16); 1408 break; 1409 case MMC_BUS_WIDTH_8: 1410 val |= (MSDC_BUS_8BITS << 16); 1411 break; 1412 } 1413 1414 writel(val, host->base + SDC_CFG); 1415 dev_dbg(host->dev, "Bus Width = %d", width); 1416} 1417 1418static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1419{ 1420 struct msdc_host *host = mmc_priv(mmc); 1421 int ret; 1422 1423 if (!IS_ERR(mmc->supply.vqmmc)) { 1424 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1425 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1426 dev_err(host->dev, "Unsupported signal voltage!\n"); 1427 return -EINVAL; 1428 } 1429 1430 ret = mmc_regulator_set_vqmmc(mmc, ios); 1431 if (ret < 0) { 1432 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1433 ret, ios->signal_voltage); 1434 return ret; 1435 } 1436 1437 /* Apply different pinctrl settings for different signal voltage */ 1438 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1439 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1440 else 1441 pinctrl_select_state(host->pinctrl, host->pins_default); 1442 } 1443 return 0; 1444} 1445 1446static int msdc_card_busy(struct mmc_host *mmc) 1447{ 1448 struct msdc_host *host = mmc_priv(mmc); 1449 u32 status = readl(host->base + MSDC_PS); 1450 1451 /* only check if data0 is low */ 1452 return !(status & BIT(16)); 1453} 1454 1455static void msdc_request_timeout(struct work_struct *work) 1456{ 1457 struct msdc_host *host = container_of(work, struct msdc_host, 1458 req_timeout.work); 1459 1460 /* simulate HW timeout status */ 1461 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1462 if (host->mrq) { 1463 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1464 host->mrq, host->mrq->cmd->opcode); 1465 if (host->cmd) { 1466 dev_err(host->dev, "%s: aborting cmd=%d\n", 1467 __func__, host->cmd->opcode); 1468 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1469 host->cmd); 1470 } else if (host->data) { 1471 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1472 __func__, host->mrq->cmd->opcode, 1473 host->data->blocks); 1474 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1475 host->data); 1476 } 1477 } 1478} 1479 1480static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1481{ 1482 if (enb) { 1483 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1484 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1485 if (host->dev_comp->recheck_sdio_irq) 1486 msdc_recheck_sdio_irq(host); 1487 } else { 1488 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1489 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1490 } 1491} 1492 1493static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1494{ 1495 unsigned long flags; 1496 struct msdc_host *host = mmc_priv(mmc); 1497 1498 spin_lock_irqsave(&host->lock, flags); 1499 __msdc_enable_sdio_irq(host, enb); 1500 spin_unlock_irqrestore(&host->lock, flags); 1501 1502 if (enb) 1503 pm_runtime_get_noresume(host->dev); 1504 else 1505 pm_runtime_put_noidle(host->dev); 1506} 1507 1508static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1509{ 1510 struct mmc_host *mmc = mmc_from_priv(host); 1511 int cmd_err = 0, dat_err = 0; 1512 1513 if (intsts & MSDC_INT_RSPCRCERR) { 1514 cmd_err = -EILSEQ; 1515 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1516 } else if (intsts & MSDC_INT_CMDTMO) { 1517 cmd_err = -ETIMEDOUT; 1518 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1519 } 1520 1521 if (intsts & MSDC_INT_DATCRCERR) { 1522 dat_err = -EILSEQ; 1523 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1524 } else if (intsts & MSDC_INT_DATTMO) { 1525 dat_err = -ETIMEDOUT; 1526 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1527 } 1528 1529 if (cmd_err || dat_err) { 1530 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1531 cmd_err, dat_err, intsts); 1532 } 1533 1534 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1535} 1536 1537static irqreturn_t msdc_irq(int irq, void *dev_id) 1538{ 1539 struct msdc_host *host = (struct msdc_host *) dev_id; 1540 struct mmc_host *mmc = mmc_from_priv(host); 1541 1542 while (true) { 1543 unsigned long flags; 1544 struct mmc_request *mrq; 1545 struct mmc_command *cmd; 1546 struct mmc_data *data; 1547 u32 events, event_mask; 1548 1549 spin_lock_irqsave(&host->lock, flags); 1550 events = readl(host->base + MSDC_INT); 1551 event_mask = readl(host->base + MSDC_INTEN); 1552 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1553 __msdc_enable_sdio_irq(host, 0); 1554 /* clear interrupts */ 1555 writel(events & event_mask, host->base + MSDC_INT); 1556 1557 mrq = host->mrq; 1558 cmd = host->cmd; 1559 data = host->data; 1560 spin_unlock_irqrestore(&host->lock, flags); 1561 1562 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1563 sdio_signal_irq(mmc); 1564 1565 if ((events & event_mask) & MSDC_INT_CDSC) { 1566 if (host->internal_cd) 1567 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1568 events &= ~MSDC_INT_CDSC; 1569 } 1570 1571 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1572 break; 1573 1574 if ((mmc->caps2 & MMC_CAP2_CQE) && 1575 (events & MSDC_INT_CMDQ)) { 1576 msdc_cmdq_irq(host, events); 1577 /* clear interrupts */ 1578 writel(events, host->base + MSDC_INT); 1579 return IRQ_HANDLED; 1580 } 1581 1582 if (!mrq) { 1583 dev_err(host->dev, 1584 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1585 __func__, events, event_mask); 1586 WARN_ON(1); 1587 break; 1588 } 1589 1590 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1591 1592 if (cmd) 1593 msdc_cmd_done(host, events, mrq, cmd); 1594 else if (data) 1595 msdc_data_xfer_done(host, events, mrq, data); 1596 } 1597 1598 return IRQ_HANDLED; 1599} 1600 1601static void msdc_init_hw(struct msdc_host *host) 1602{ 1603 u32 val; 1604 u32 tune_reg = host->dev_comp->pad_tune_reg; 1605 1606 if (host->reset) { 1607 reset_control_assert(host->reset); 1608 usleep_range(10, 50); 1609 reset_control_deassert(host->reset); 1610 } 1611 1612 /* Configure to MMC/SD mode, clock free running */ 1613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1614 1615 /* Reset */ 1616 msdc_reset_hw(host); 1617 1618 /* Disable and clear all interrupts */ 1619 writel(0, host->base + MSDC_INTEN); 1620 val = readl(host->base + MSDC_INT); 1621 writel(val, host->base + MSDC_INT); 1622 1623 /* Configure card detection */ 1624 if (host->internal_cd) { 1625 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1626 DEFAULT_DEBOUNCE); 1627 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1628 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1629 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1630 } else { 1631 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1632 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1633 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1634 } 1635 1636 if (host->top_base) { 1637 writel(0, host->top_base + EMMC_TOP_CONTROL); 1638 writel(0, host->top_base + EMMC_TOP_CMD); 1639 } else { 1640 writel(0, host->base + tune_reg); 1641 } 1642 writel(0, host->base + MSDC_IOCON); 1643 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1644 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1645 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1646 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1647 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1648 1649 if (host->dev_comp->stop_clk_fix) { 1650 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1651 MSDC_PATCH_BIT1_STOP_DLY, 3); 1652 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1653 SDC_FIFO_CFG_WRVALIDSEL); 1654 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1655 SDC_FIFO_CFG_RDVALIDSEL); 1656 } 1657 1658 if (host->dev_comp->busy_check) 1659 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1660 1661 if (host->dev_comp->async_fifo) { 1662 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1663 MSDC_PB2_RESPWAIT, 3); 1664 if (host->dev_comp->enhance_rx) { 1665 if (host->top_base) 1666 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1667 SDC_RX_ENH_EN); 1668 else 1669 sdr_set_bits(host->base + SDC_ADV_CFG0, 1670 SDC_RX_ENHANCE_EN); 1671 } else { 1672 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1673 MSDC_PB2_RESPSTSENSEL, 2); 1674 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1675 MSDC_PB2_CRCSTSENSEL, 2); 1676 } 1677 /* use async fifo, then no need tune internal delay */ 1678 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1679 MSDC_PATCH_BIT2_CFGRESP); 1680 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1681 MSDC_PATCH_BIT2_CFGCRCSTS); 1682 } 1683 1684 if (host->dev_comp->support_64g) 1685 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1686 MSDC_PB2_SUPPORT_64G); 1687 if (host->dev_comp->data_tune) { 1688 if (host->top_base) { 1689 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1690 PAD_DAT_RD_RXDLY_SEL); 1691 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1692 DATA_K_VALUE_SEL); 1693 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1694 PAD_CMD_RD_RXDLY_SEL); 1695 } else { 1696 sdr_set_bits(host->base + tune_reg, 1697 MSDC_PAD_TUNE_RD_SEL | 1698 MSDC_PAD_TUNE_CMD_SEL); 1699 } 1700 } else { 1701 /* choose clock tune */ 1702 if (host->top_base) 1703 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1704 PAD_RXDLY_SEL); 1705 else 1706 sdr_set_bits(host->base + tune_reg, 1707 MSDC_PAD_TUNE_RXDLYSEL); 1708 } 1709 1710 /* Configure to enable SDIO mode. 1711 * it's must otherwise sdio cmd5 failed 1712 */ 1713 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1714 1715 /* Config SDIO device detect interrupt function */ 1716 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1717 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1718 1719 /* Configure to default data timeout */ 1720 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1721 1722 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1723 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1724 if (host->top_base) { 1725 host->def_tune_para.emmc_top_control = 1726 readl(host->top_base + EMMC_TOP_CONTROL); 1727 host->def_tune_para.emmc_top_cmd = 1728 readl(host->top_base + EMMC_TOP_CMD); 1729 host->saved_tune_para.emmc_top_control = 1730 readl(host->top_base + EMMC_TOP_CONTROL); 1731 host->saved_tune_para.emmc_top_cmd = 1732 readl(host->top_base + EMMC_TOP_CMD); 1733 } else { 1734 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1735 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1736 } 1737 dev_dbg(host->dev, "init hardware done!"); 1738} 1739 1740static void msdc_deinit_hw(struct msdc_host *host) 1741{ 1742 u32 val; 1743 1744 if (host->internal_cd) { 1745 /* Disabled card-detect */ 1746 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1747 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1748 } 1749 1750 /* Disable and clear all interrupts */ 1751 writel(0, host->base + MSDC_INTEN); 1752 1753 val = readl(host->base + MSDC_INT); 1754 writel(val, host->base + MSDC_INT); 1755} 1756 1757/* init gpd and bd list in msdc_drv_probe */ 1758static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1759{ 1760 struct mt_gpdma_desc *gpd = dma->gpd; 1761 struct mt_bdma_desc *bd = dma->bd; 1762 dma_addr_t dma_addr; 1763 int i; 1764 1765 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1766 1767 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1768 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1769 /* gpd->next is must set for desc DMA 1770 * That's why must alloc 2 gpd structure. 1771 */ 1772 gpd->next = lower_32_bits(dma_addr); 1773 if (host->dev_comp->support_64g) 1774 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1775 1776 dma_addr = dma->bd_addr; 1777 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1778 if (host->dev_comp->support_64g) 1779 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1780 1781 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1782 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1783 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1784 bd[i].next = lower_32_bits(dma_addr); 1785 if (host->dev_comp->support_64g) 1786 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1787 } 1788} 1789 1790static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1791{ 1792 struct msdc_host *host = mmc_priv(mmc); 1793 int ret; 1794 1795 msdc_set_buswidth(host, ios->bus_width); 1796 1797 /* Suspend/Resume will do power off/on */ 1798 switch (ios->power_mode) { 1799 case MMC_POWER_UP: 1800 if (!IS_ERR(mmc->supply.vmmc)) { 1801 msdc_init_hw(host); 1802 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1803 ios->vdd); 1804 if (ret) { 1805 dev_err(host->dev, "Failed to set vmmc power!\n"); 1806 return; 1807 } 1808 } 1809 break; 1810 case MMC_POWER_ON: 1811 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1812 ret = regulator_enable(mmc->supply.vqmmc); 1813 if (ret) 1814 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1815 else 1816 host->vqmmc_enabled = true; 1817 } 1818 break; 1819 case MMC_POWER_OFF: 1820 if (!IS_ERR(mmc->supply.vmmc)) 1821 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1822 1823 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1824 regulator_disable(mmc->supply.vqmmc); 1825 host->vqmmc_enabled = false; 1826 } 1827 break; 1828 default: 1829 break; 1830 } 1831 1832 if (host->mclk != ios->clock || host->timing != ios->timing) 1833 msdc_set_mclk(host, ios->timing, ios->clock); 1834} 1835 1836static u32 test_delay_bit(u32 delay, u32 bit) 1837{ 1838 bit %= PAD_DELAY_MAX; 1839 return delay & (1 << bit); 1840} 1841 1842static int get_delay_len(u32 delay, u32 start_bit) 1843{ 1844 int i; 1845 1846 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1847 if (test_delay_bit(delay, start_bit + i) == 0) 1848 return i; 1849 } 1850 return PAD_DELAY_MAX - start_bit; 1851} 1852 1853static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1854{ 1855 int start = 0, len = 0; 1856 int start_final = 0, len_final = 0; 1857 u8 final_phase = 0xff; 1858 struct msdc_delay_phase delay_phase = { 0, }; 1859 1860 if (delay == 0) { 1861 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1862 delay_phase.final_phase = final_phase; 1863 return delay_phase; 1864 } 1865 1866 while (start < PAD_DELAY_MAX) { 1867 len = get_delay_len(delay, start); 1868 if (len_final < len) { 1869 start_final = start; 1870 len_final = len; 1871 } 1872 start += len ? len : 1; 1873 if (len >= 12 && start_final < 4) 1874 break; 1875 } 1876 1877 /* The rule is that to find the smallest delay cell */ 1878 if (start_final == 0) 1879 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1880 else 1881 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1882 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1883 delay, len_final, final_phase); 1884 1885 delay_phase.maxlen = len_final; 1886 delay_phase.start = start_final; 1887 delay_phase.final_phase = final_phase; 1888 return delay_phase; 1889} 1890 1891static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1892{ 1893 u32 tune_reg = host->dev_comp->pad_tune_reg; 1894 1895 if (host->top_base) 1896 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1897 value); 1898 else 1899 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1900 value); 1901} 1902 1903static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1904{ 1905 u32 tune_reg = host->dev_comp->pad_tune_reg; 1906 1907 if (host->top_base) 1908 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1909 PAD_DAT_RD_RXDLY, value); 1910 else 1911 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1912 value); 1913} 1914 1915static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1916{ 1917 struct msdc_host *host = mmc_priv(mmc); 1918 u32 rise_delay = 0, fall_delay = 0; 1919 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1920 struct msdc_delay_phase internal_delay_phase; 1921 u8 final_delay, final_maxlen; 1922 u32 internal_delay = 0; 1923 u32 tune_reg = host->dev_comp->pad_tune_reg; 1924 int cmd_err; 1925 int i, j; 1926 1927 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1928 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1929 sdr_set_field(host->base + tune_reg, 1930 MSDC_PAD_TUNE_CMDRRDLY, 1931 host->hs200_cmd_int_delay); 1932 1933 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1934 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1935 msdc_set_cmd_delay(host, i); 1936 /* 1937 * Using the same parameters, it may sometimes pass the test, 1938 * but sometimes it may fail. To make sure the parameters are 1939 * more stable, we test each set of parameters 3 times. 1940 */ 1941 for (j = 0; j < 3; j++) { 1942 mmc_send_tuning(mmc, opcode, &cmd_err); 1943 if (!cmd_err) { 1944 rise_delay |= (1 << i); 1945 } else { 1946 rise_delay &= ~(1 << i); 1947 break; 1948 } 1949 } 1950 } 1951 final_rise_delay = get_best_delay(host, rise_delay); 1952 /* if rising edge has enough margin, then do not scan falling edge */ 1953 if (final_rise_delay.maxlen >= 12 || 1954 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1955 goto skip_fall; 1956 1957 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1958 for (i = 0; i < PAD_DELAY_MAX; i++) { 1959 msdc_set_cmd_delay(host, i); 1960 /* 1961 * Using the same parameters, it may sometimes pass the test, 1962 * but sometimes it may fail. To make sure the parameters are 1963 * more stable, we test each set of parameters 3 times. 1964 */ 1965 for (j = 0; j < 3; j++) { 1966 mmc_send_tuning(mmc, opcode, &cmd_err); 1967 if (!cmd_err) { 1968 fall_delay |= (1 << i); 1969 } else { 1970 fall_delay &= ~(1 << i); 1971 break; 1972 } 1973 } 1974 } 1975 final_fall_delay = get_best_delay(host, fall_delay); 1976 1977skip_fall: 1978 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1979 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1980 final_maxlen = final_fall_delay.maxlen; 1981 if (final_maxlen == final_rise_delay.maxlen) { 1982 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1983 final_delay = final_rise_delay.final_phase; 1984 } else { 1985 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1986 final_delay = final_fall_delay.final_phase; 1987 } 1988 msdc_set_cmd_delay(host, final_delay); 1989 1990 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1991 goto skip_internal; 1992 1993 for (i = 0; i < PAD_DELAY_MAX; i++) { 1994 sdr_set_field(host->base + tune_reg, 1995 MSDC_PAD_TUNE_CMDRRDLY, i); 1996 mmc_send_tuning(mmc, opcode, &cmd_err); 1997 if (!cmd_err) 1998 internal_delay |= (1 << i); 1999 } 2000 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2001 internal_delay_phase = get_best_delay(host, internal_delay); 2002 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2003 internal_delay_phase.final_phase); 2004skip_internal: 2005 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2006 return final_delay == 0xff ? -EIO : 0; 2007} 2008 2009static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2010{ 2011 struct msdc_host *host = mmc_priv(mmc); 2012 u32 cmd_delay = 0; 2013 struct msdc_delay_phase final_cmd_delay = { 0,}; 2014 u8 final_delay; 2015 int cmd_err; 2016 int i, j; 2017 2018 /* select EMMC50 PAD CMD tune */ 2019 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2020 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2021 2022 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2023 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2024 sdr_set_field(host->base + MSDC_PAD_TUNE, 2025 MSDC_PAD_TUNE_CMDRRDLY, 2026 host->hs200_cmd_int_delay); 2027 2028 if (host->hs400_cmd_resp_sel_rising) 2029 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2030 else 2031 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2032 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2033 sdr_set_field(host->base + PAD_CMD_TUNE, 2034 PAD_CMD_TUNE_RX_DLY3, i); 2035 /* 2036 * Using the same parameters, it may sometimes pass the test, 2037 * but sometimes it may fail. To make sure the parameters are 2038 * more stable, we test each set of parameters 3 times. 2039 */ 2040 for (j = 0; j < 3; j++) { 2041 mmc_send_tuning(mmc, opcode, &cmd_err); 2042 if (!cmd_err) { 2043 cmd_delay |= (1 << i); 2044 } else { 2045 cmd_delay &= ~(1 << i); 2046 break; 2047 } 2048 } 2049 } 2050 final_cmd_delay = get_best_delay(host, cmd_delay); 2051 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2052 final_cmd_delay.final_phase); 2053 final_delay = final_cmd_delay.final_phase; 2054 2055 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2056 return final_delay == 0xff ? -EIO : 0; 2057} 2058 2059static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2060{ 2061 struct msdc_host *host = mmc_priv(mmc); 2062 u32 rise_delay = 0, fall_delay = 0; 2063 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2064 u8 final_delay, final_maxlen; 2065 int i, ret; 2066 2067 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2068 host->latch_ck); 2069 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2070 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2071 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2072 msdc_set_data_delay(host, i); 2073 ret = mmc_send_tuning(mmc, opcode, NULL); 2074 if (!ret) 2075 rise_delay |= (1 << i); 2076 } 2077 final_rise_delay = get_best_delay(host, rise_delay); 2078 /* if rising edge has enough margin, then do not scan falling edge */ 2079 if (final_rise_delay.maxlen >= 12 || 2080 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2081 goto skip_fall; 2082 2083 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2084 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2085 for (i = 0; i < PAD_DELAY_MAX; i++) { 2086 msdc_set_data_delay(host, i); 2087 ret = mmc_send_tuning(mmc, opcode, NULL); 2088 if (!ret) 2089 fall_delay |= (1 << i); 2090 } 2091 final_fall_delay = get_best_delay(host, fall_delay); 2092 2093skip_fall: 2094 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2095 if (final_maxlen == final_rise_delay.maxlen) { 2096 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2097 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2098 final_delay = final_rise_delay.final_phase; 2099 } else { 2100 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2101 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2102 final_delay = final_fall_delay.final_phase; 2103 } 2104 msdc_set_data_delay(host, final_delay); 2105 2106 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2107 return final_delay == 0xff ? -EIO : 0; 2108} 2109 2110/* 2111 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2112 * together, which can save the tuning time. 2113 */ 2114static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2115{ 2116 struct msdc_host *host = mmc_priv(mmc); 2117 u32 rise_delay = 0, fall_delay = 0; 2118 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2119 u8 final_delay, final_maxlen; 2120 int i, ret; 2121 2122 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2123 host->latch_ck); 2124 2125 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2126 sdr_clr_bits(host->base + MSDC_IOCON, 2127 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2128 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2129 msdc_set_cmd_delay(host, i); 2130 msdc_set_data_delay(host, i); 2131 ret = mmc_send_tuning(mmc, opcode, NULL); 2132 if (!ret) 2133 rise_delay |= (1 << i); 2134 } 2135 final_rise_delay = get_best_delay(host, rise_delay); 2136 /* if rising edge has enough margin, then do not scan falling edge */ 2137 if (final_rise_delay.maxlen >= 12 || 2138 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2139 goto skip_fall; 2140 2141 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2142 sdr_set_bits(host->base + MSDC_IOCON, 2143 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2144 for (i = 0; i < PAD_DELAY_MAX; i++) { 2145 msdc_set_cmd_delay(host, i); 2146 msdc_set_data_delay(host, i); 2147 ret = mmc_send_tuning(mmc, opcode, NULL); 2148 if (!ret) 2149 fall_delay |= (1 << i); 2150 } 2151 final_fall_delay = get_best_delay(host, fall_delay); 2152 2153skip_fall: 2154 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2155 if (final_maxlen == final_rise_delay.maxlen) { 2156 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2157 sdr_clr_bits(host->base + MSDC_IOCON, 2158 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2159 final_delay = final_rise_delay.final_phase; 2160 } else { 2161 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2162 sdr_set_bits(host->base + MSDC_IOCON, 2163 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2164 final_delay = final_fall_delay.final_phase; 2165 } 2166 2167 msdc_set_cmd_delay(host, final_delay); 2168 msdc_set_data_delay(host, final_delay); 2169 2170 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2171 return final_delay == 0xff ? -EIO : 0; 2172} 2173 2174static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2175{ 2176 struct msdc_host *host = mmc_priv(mmc); 2177 int ret; 2178 u32 tune_reg = host->dev_comp->pad_tune_reg; 2179 2180 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2181 ret = msdc_tune_together(mmc, opcode); 2182 if (host->hs400_mode) { 2183 sdr_clr_bits(host->base + MSDC_IOCON, 2184 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2185 msdc_set_data_delay(host, 0); 2186 } 2187 goto tune_done; 2188 } 2189 if (host->hs400_mode && 2190 host->dev_comp->hs400_tune) 2191 ret = hs400_tune_response(mmc, opcode); 2192 else 2193 ret = msdc_tune_response(mmc, opcode); 2194 if (ret == -EIO) { 2195 dev_err(host->dev, "Tune response fail!\n"); 2196 return ret; 2197 } 2198 if (host->hs400_mode == false) { 2199 ret = msdc_tune_data(mmc, opcode); 2200 if (ret == -EIO) 2201 dev_err(host->dev, "Tune data fail!\n"); 2202 } 2203 2204tune_done: 2205 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2206 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2207 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2208 if (host->top_base) { 2209 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2210 EMMC_TOP_CONTROL); 2211 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2212 EMMC_TOP_CMD); 2213 } 2214 return ret; 2215} 2216 2217static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2218{ 2219 struct msdc_host *host = mmc_priv(mmc); 2220 host->hs400_mode = true; 2221 2222 if (host->top_base) 2223 writel(host->hs400_ds_delay, 2224 host->top_base + EMMC50_PAD_DS_TUNE); 2225 else 2226 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2227 /* hs400 mode must set it to 0 */ 2228 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2229 /* to improve read performance, set outstanding to 2 */ 2230 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2231 2232 return 0; 2233} 2234 2235static void msdc_hw_reset(struct mmc_host *mmc) 2236{ 2237 struct msdc_host *host = mmc_priv(mmc); 2238 2239 sdr_set_bits(host->base + EMMC_IOCON, 1); 2240 udelay(10); /* 10us is enough */ 2241 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2242} 2243 2244static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2245{ 2246 unsigned long flags; 2247 struct msdc_host *host = mmc_priv(mmc); 2248 2249 spin_lock_irqsave(&host->lock, flags); 2250 __msdc_enable_sdio_irq(host, 1); 2251 spin_unlock_irqrestore(&host->lock, flags); 2252} 2253 2254static int msdc_get_cd(struct mmc_host *mmc) 2255{ 2256 struct msdc_host *host = mmc_priv(mmc); 2257 int val; 2258 2259 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2260 return 1; 2261 2262 if (!host->internal_cd) 2263 return mmc_gpio_get_cd(mmc); 2264 2265 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2266 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2267 return !!val; 2268 else 2269 return !val; 2270} 2271 2272static void msdc_cqe_enable(struct mmc_host *mmc) 2273{ 2274 struct msdc_host *host = mmc_priv(mmc); 2275 2276 /* enable cmdq irq */ 2277 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2278 /* enable busy check */ 2279 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2280 /* default write data / busy timeout 20s */ 2281 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2282 /* default read data timeout 1s */ 2283 msdc_set_timeout(host, 1000000000ULL, 0); 2284} 2285 2286static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2287{ 2288 struct msdc_host *host = mmc_priv(mmc); 2289 unsigned int val = 0; 2290 2291 /* disable cmdq irq */ 2292 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2293 /* disable busy check */ 2294 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2295 2296 val = readl(host->base + MSDC_INT); 2297 writel(val, host->base + MSDC_INT); 2298 2299 if (recovery) { 2300 sdr_set_field(host->base + MSDC_DMA_CTRL, 2301 MSDC_DMA_CTRL_STOP, 1); 2302 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2303 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2304 return; 2305 msdc_reset_hw(host); 2306 } 2307} 2308 2309static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2310{ 2311 struct cqhci_host *cq_host = mmc->cqe_private; 2312 u32 reg; 2313 2314 reg = cqhci_readl(cq_host, CQHCI_CFG); 2315 reg |= CQHCI_ENABLE; 2316 cqhci_writel(cq_host, reg, CQHCI_CFG); 2317} 2318 2319static void msdc_cqe_post_disable(struct mmc_host *mmc) 2320{ 2321 struct cqhci_host *cq_host = mmc->cqe_private; 2322 u32 reg; 2323 2324 reg = cqhci_readl(cq_host, CQHCI_CFG); 2325 reg &= ~CQHCI_ENABLE; 2326 cqhci_writel(cq_host, reg, CQHCI_CFG); 2327} 2328 2329static const struct mmc_host_ops mt_msdc_ops = { 2330 .post_req = msdc_post_req, 2331 .pre_req = msdc_pre_req, 2332 .request = msdc_ops_request, 2333 .set_ios = msdc_ops_set_ios, 2334 .get_ro = mmc_gpio_get_ro, 2335 .get_cd = msdc_get_cd, 2336 .enable_sdio_irq = msdc_enable_sdio_irq, 2337 .ack_sdio_irq = msdc_ack_sdio_irq, 2338 .start_signal_voltage_switch = msdc_ops_switch_volt, 2339 .card_busy = msdc_card_busy, 2340 .execute_tuning = msdc_execute_tuning, 2341 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2342 .hw_reset = msdc_hw_reset, 2343}; 2344 2345static const struct cqhci_host_ops msdc_cmdq_ops = { 2346 .enable = msdc_cqe_enable, 2347 .disable = msdc_cqe_disable, 2348 .pre_enable = msdc_cqe_pre_enable, 2349 .post_disable = msdc_cqe_post_disable, 2350}; 2351 2352static void msdc_of_property_parse(struct platform_device *pdev, 2353 struct msdc_host *host) 2354{ 2355 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2356 &host->latch_ck); 2357 2358 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2359 &host->hs400_ds_delay); 2360 2361 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2362 &host->hs200_cmd_int_delay); 2363 2364 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2365 &host->hs400_cmd_int_delay); 2366 2367 if (of_property_read_bool(pdev->dev.of_node, 2368 "mediatek,hs400-cmd-resp-sel-rising")) 2369 host->hs400_cmd_resp_sel_rising = true; 2370 else 2371 host->hs400_cmd_resp_sel_rising = false; 2372 2373 if (of_property_read_bool(pdev->dev.of_node, 2374 "supports-cqe")) 2375 host->cqhci = true; 2376 else 2377 host->cqhci = false; 2378} 2379 2380static int msdc_drv_probe(struct platform_device *pdev) 2381{ 2382 struct mmc_host *mmc; 2383 struct msdc_host *host; 2384 struct resource *res; 2385 int ret; 2386 2387 if (!pdev->dev.of_node) { 2388 dev_err(&pdev->dev, "No DT found\n"); 2389 return -EINVAL; 2390 } 2391 2392 /* Allocate MMC host for this device */ 2393 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2394 if (!mmc) 2395 return -ENOMEM; 2396 2397 host = mmc_priv(mmc); 2398 ret = mmc_of_parse(mmc); 2399 if (ret) 2400 goto host_free; 2401 2402 host->base = devm_platform_ioremap_resource(pdev, 0); 2403 if (IS_ERR(host->base)) { 2404 ret = PTR_ERR(host->base); 2405 goto host_free; 2406 } 2407 2408 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2409 if (res) { 2410 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2411 if (IS_ERR(host->top_base)) 2412 host->top_base = NULL; 2413 } 2414 2415 ret = mmc_regulator_get_supply(mmc); 2416 if (ret) 2417 goto host_free; 2418 2419 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2420 if (IS_ERR(host->src_clk)) { 2421 ret = PTR_ERR(host->src_clk); 2422 goto host_free; 2423 } 2424 2425 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2426 if (IS_ERR(host->h_clk)) { 2427 ret = PTR_ERR(host->h_clk); 2428 goto host_free; 2429 } 2430 2431 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2432 if (IS_ERR(host->bus_clk)) 2433 host->bus_clk = NULL; 2434 /*source clock control gate is optional clock*/ 2435 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2436 if (IS_ERR(host->src_clk_cg)) 2437 host->src_clk_cg = NULL; 2438 2439 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2440 "hrst"); 2441 if (IS_ERR(host->reset)) 2442 return PTR_ERR(host->reset); 2443 2444 host->irq = platform_get_irq(pdev, 0); 2445 if (host->irq < 0) { 2446 ret = host->irq; 2447 goto host_free; 2448 } 2449 2450 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2451 if (IS_ERR(host->pinctrl)) { 2452 ret = PTR_ERR(host->pinctrl); 2453 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2454 goto host_free; 2455 } 2456 2457 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2458 if (IS_ERR(host->pins_default)) { 2459 ret = PTR_ERR(host->pins_default); 2460 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2461 goto host_free; 2462 } 2463 2464 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2465 if (IS_ERR(host->pins_uhs)) { 2466 ret = PTR_ERR(host->pins_uhs); 2467 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2468 goto host_free; 2469 } 2470 2471 msdc_of_property_parse(pdev, host); 2472 2473 host->dev = &pdev->dev; 2474 host->dev_comp = of_device_get_match_data(&pdev->dev); 2475 host->src_clk_freq = clk_get_rate(host->src_clk); 2476 /* Set host parameters to mmc */ 2477 mmc->ops = &mt_msdc_ops; 2478 if (host->dev_comp->clk_div_bits == 8) 2479 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2480 else 2481 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2482 2483 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2484 !mmc_can_gpio_cd(mmc) && 2485 host->dev_comp->use_internal_cd) { 2486 /* 2487 * Is removable but no GPIO declared, so 2488 * use internal functionality. 2489 */ 2490 host->internal_cd = true; 2491 } 2492 2493 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2494 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2495 2496 mmc->caps |= MMC_CAP_CMD23; 2497 if (host->cqhci) 2498 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2499 /* MMC core transfer sizes tunable parameters */ 2500 mmc->max_segs = MAX_BD_NUM; 2501 if (host->dev_comp->support_64g) 2502 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2503 else 2504 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2505 mmc->max_blk_size = 2048; 2506 mmc->max_req_size = 512 * 1024; 2507 mmc->max_blk_count = mmc->max_req_size / 512; 2508 if (host->dev_comp->support_64g) 2509 host->dma_mask = DMA_BIT_MASK(36); 2510 else 2511 host->dma_mask = DMA_BIT_MASK(32); 2512 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2513 2514 host->timeout_clks = 3 * 1048576; 2515 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2516 2 * sizeof(struct mt_gpdma_desc), 2517 &host->dma.gpd_addr, GFP_KERNEL); 2518 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2519 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2520 &host->dma.bd_addr, GFP_KERNEL); 2521 if (!host->dma.gpd || !host->dma.bd) { 2522 ret = -ENOMEM; 2523 goto release_mem; 2524 } 2525 msdc_init_gpd_bd(host, &host->dma); 2526 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2527 spin_lock_init(&host->lock); 2528 2529 platform_set_drvdata(pdev, mmc); 2530 msdc_ungate_clock(host); 2531 msdc_init_hw(host); 2532 2533 if (mmc->caps2 & MMC_CAP2_CQE) { 2534 host->cq_host = devm_kzalloc(mmc->parent, 2535 sizeof(*host->cq_host), 2536 GFP_KERNEL); 2537 if (!host->cq_host) { 2538 ret = -ENOMEM; 2539 goto host_free; 2540 } 2541 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2542 host->cq_host->mmio = host->base + 0x800; 2543 host->cq_host->ops = &msdc_cmdq_ops; 2544 ret = cqhci_init(host->cq_host, mmc, true); 2545 if (ret) 2546 goto host_free; 2547 mmc->max_segs = 128; 2548 /* cqhci 16bit length */ 2549 /* 0 size, means 65536 so we don't have to -1 here */ 2550 mmc->max_seg_size = 64 * 1024; 2551 } 2552 2553 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2554 IRQF_TRIGGER_NONE, pdev->name, host); 2555 if (ret) 2556 goto release; 2557 2558 pm_runtime_set_active(host->dev); 2559 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2560 pm_runtime_use_autosuspend(host->dev); 2561 pm_runtime_enable(host->dev); 2562 ret = mmc_add_host(mmc); 2563 2564 if (ret) 2565 goto end; 2566 2567 return 0; 2568end: 2569 pm_runtime_disable(host->dev); 2570release: 2571 platform_set_drvdata(pdev, NULL); 2572 msdc_deinit_hw(host); 2573 msdc_gate_clock(host); 2574release_mem: 2575 if (host->dma.gpd) 2576 dma_free_coherent(&pdev->dev, 2577 2 * sizeof(struct mt_gpdma_desc), 2578 host->dma.gpd, host->dma.gpd_addr); 2579 if (host->dma.bd) 2580 dma_free_coherent(&pdev->dev, 2581 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2582 host->dma.bd, host->dma.bd_addr); 2583host_free: 2584 mmc_free_host(mmc); 2585 2586 return ret; 2587} 2588 2589static int msdc_drv_remove(struct platform_device *pdev) 2590{ 2591 struct mmc_host *mmc; 2592 struct msdc_host *host; 2593 2594 mmc = platform_get_drvdata(pdev); 2595 host = mmc_priv(mmc); 2596 2597 pm_runtime_get_sync(host->dev); 2598 2599 platform_set_drvdata(pdev, NULL); 2600 mmc_remove_host(mmc); 2601 msdc_deinit_hw(host); 2602 msdc_gate_clock(host); 2603 2604 pm_runtime_disable(host->dev); 2605 pm_runtime_put_noidle(host->dev); 2606 dma_free_coherent(&pdev->dev, 2607 2 * sizeof(struct mt_gpdma_desc), 2608 host->dma.gpd, host->dma.gpd_addr); 2609 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2610 host->dma.bd, host->dma.bd_addr); 2611 2612 mmc_free_host(mmc); 2613 2614 return 0; 2615} 2616 2617static void msdc_save_reg(struct msdc_host *host) 2618{ 2619 u32 tune_reg = host->dev_comp->pad_tune_reg; 2620 2621 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2622 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2623 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2624 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2625 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2626 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2627 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2628 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2629 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2630 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2631 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2632 if (host->top_base) { 2633 host->save_para.emmc_top_control = 2634 readl(host->top_base + EMMC_TOP_CONTROL); 2635 host->save_para.emmc_top_cmd = 2636 readl(host->top_base + EMMC_TOP_CMD); 2637 host->save_para.emmc50_pad_ds_tune = 2638 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2639 } else { 2640 host->save_para.pad_tune = readl(host->base + tune_reg); 2641 } 2642} 2643 2644static void msdc_restore_reg(struct msdc_host *host) 2645{ 2646 struct mmc_host *mmc = mmc_from_priv(host); 2647 u32 tune_reg = host->dev_comp->pad_tune_reg; 2648 2649 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2650 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2651 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2652 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2653 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2654 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2655 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2656 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2657 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2658 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2659 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2660 if (host->top_base) { 2661 writel(host->save_para.emmc_top_control, 2662 host->top_base + EMMC_TOP_CONTROL); 2663 writel(host->save_para.emmc_top_cmd, 2664 host->top_base + EMMC_TOP_CMD); 2665 writel(host->save_para.emmc50_pad_ds_tune, 2666 host->top_base + EMMC50_PAD_DS_TUNE); 2667 } else { 2668 writel(host->save_para.pad_tune, host->base + tune_reg); 2669 } 2670 2671 if (sdio_irq_claimed(mmc)) 2672 __msdc_enable_sdio_irq(host, 1); 2673} 2674 2675static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2676{ 2677 struct mmc_host *mmc = dev_get_drvdata(dev); 2678 struct msdc_host *host = mmc_priv(mmc); 2679 2680 msdc_save_reg(host); 2681 msdc_gate_clock(host); 2682 return 0; 2683} 2684 2685static int __maybe_unused msdc_runtime_resume(struct device *dev) 2686{ 2687 struct mmc_host *mmc = dev_get_drvdata(dev); 2688 struct msdc_host *host = mmc_priv(mmc); 2689 2690 msdc_ungate_clock(host); 2691 msdc_restore_reg(host); 2692 return 0; 2693} 2694 2695static int __maybe_unused msdc_suspend(struct device *dev) 2696{ 2697 struct mmc_host *mmc = dev_get_drvdata(dev); 2698 int ret; 2699 u32 val; 2700 2701 if (mmc->caps2 & MMC_CAP2_CQE) { 2702 ret = cqhci_suspend(mmc); 2703 if (ret) 2704 return ret; 2705 val = readl(((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT); 2706 writel(val, ((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT); 2707 } 2708 2709 return pm_runtime_force_suspend(dev); 2710} 2711 2712static int __maybe_unused msdc_resume(struct device *dev) 2713{ 2714 return pm_runtime_force_resume(dev); 2715} 2716 2717static const struct dev_pm_ops msdc_dev_pm_ops = { 2718 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2719 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2720}; 2721 2722static struct platform_driver mt_msdc_driver = { 2723 .probe = msdc_drv_probe, 2724 .remove = msdc_drv_remove, 2725 .driver = { 2726 .name = "mtk-msdc", 2727 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2728 .of_match_table = msdc_of_ids, 2729 .pm = &msdc_dev_pm_ops, 2730 }, 2731}; 2732 2733module_platform_driver(mt_msdc_driver); 2734MODULE_LICENSE("GPL v2"); 2735MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2736