1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8#include <linux/kernel.h> 9#include <linux/module.h> 10#include <linux/init.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/iopoll.h> 14#include <linux/of_device.h> 15#include <linux/platform_device.h> 16#include <linux/ioport.h> 17#include <linux/dma-mapping.h> 18#include <linux/mmc/host.h> 19#include <linux/mmc/mmc.h> 20#include <linux/mmc/sdio.h> 21#include <linux/mmc/slot-gpio.h> 22#include <linux/io.h> 23#include <linux/clk.h> 24#include <linux/clk-provider.h> 25#include <linux/regulator/consumer.h> 26#include <linux/reset.h> 27#include <linux/interrupt.h> 28#include <linux/bitfield.h> 29#include <linux/pinctrl/consumer.h> 30 31#define DRIVER_NAME "meson-gx-mmc" 32 33#define SD_EMMC_CLOCK 0x0 34#define CLK_DIV_MASK GENMASK(5, 0) 35#define CLK_SRC_MASK GENMASK(7, 6) 36#define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37#define CLK_TX_PHASE_MASK GENMASK(11, 10) 38#define CLK_RX_PHASE_MASK GENMASK(13, 12) 39#define CLK_PHASE_0 0 40#define CLK_PHASE_180 2 41#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43#define CLK_V2_ALWAYS_ON BIT(24) 44 45#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47#define CLK_V3_ALWAYS_ON BIT(28) 48 49#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51#define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53#define SD_EMMC_DELAY 0x4 54#define SD_EMMC_ADJUST 0x8 55#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56#define ADJUST_DS_EN BIT(15) 57#define ADJUST_ADJ_EN BIT(13) 58 59#define SD_EMMC_DELAY1 0x4 60#define SD_EMMC_DELAY2 0x8 61#define SD_EMMC_V3_ADJUST 0xc 62 63#define SD_EMMC_CALOUT 0x10 64#define SD_EMMC_START 0x40 65#define START_DESC_INIT BIT(0) 66#define START_DESC_BUSY BIT(1) 67#define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69#define SD_EMMC_CFG 0x44 70#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71#define CFG_BUS_WIDTH_1 0x0 72#define CFG_BUS_WIDTH_4 0x1 73#define CFG_BUS_WIDTH_8 0x2 74#define CFG_DDR BIT(2) 75#define CFG_BLK_LEN_MASK GENMASK(7, 4) 76#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77#define CFG_RC_CC_MASK GENMASK(15, 12) 78#define CFG_STOP_CLOCK BIT(22) 79#define CFG_CLK_ALWAYS_ON BIT(18) 80#define CFG_CHK_DS BIT(20) 81#define CFG_AUTO_CLK BIT(23) 82#define CFG_ERR_ABORT BIT(27) 83 84#define SD_EMMC_STATUS 0x48 85#define STATUS_BUSY BIT(31) 86#define STATUS_DESC_BUSY BIT(30) 87#define STATUS_DATI GENMASK(23, 16) 88 89#define SD_EMMC_IRQ_EN 0x4c 90#define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91#define IRQ_TXD_ERR BIT(8) 92#define IRQ_DESC_ERR BIT(9) 93#define IRQ_RESP_ERR BIT(10) 94#define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96#define IRQ_RESP_TIMEOUT BIT(11) 97#define IRQ_DESC_TIMEOUT BIT(12) 98#define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100#define IRQ_END_OF_CHAIN BIT(13) 101#define IRQ_RESP_STATUS BIT(14) 102#define IRQ_SDIO BIT(15) 103#define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107#define SD_EMMC_CMD_CFG 0x50 108#define SD_EMMC_CMD_ARG 0x54 109#define SD_EMMC_CMD_DAT 0x58 110#define SD_EMMC_CMD_RSP 0x5c 111#define SD_EMMC_CMD_RSP1 0x60 112#define SD_EMMC_CMD_RSP2 0x64 113#define SD_EMMC_CMD_RSP3 0x68 114 115#define SD_EMMC_RXD 0x94 116#define SD_EMMC_TXD 0x94 117#define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119#define SD_EMMC_SRAM_DATA_BUF_LEN 1536 120#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200 121 122#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 123#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 124#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 125#define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 126#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 127#define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 128 129#define SD_EMMC_PRE_REQ_DONE BIT(0) 130#define SD_EMMC_DESC_CHAIN_MODE BIT(1) 131 132#define MUX_CLK_NUM_PARENTS 2 133 134struct meson_mmc_data { 135 unsigned int tx_delay_mask; 136 unsigned int rx_delay_mask; 137 unsigned int always_on; 138 unsigned int adjust; 139}; 140 141struct sd_emmc_desc { 142 u32 cmd_cfg; 143 u32 cmd_arg; 144 u32 cmd_data; 145 u32 cmd_resp; 146}; 147 148struct meson_host { 149 struct device *dev; 150 struct meson_mmc_data *data; 151 struct mmc_host *mmc; 152 struct mmc_command *cmd; 153 154 void __iomem *regs; 155 struct clk *core_clk; 156 struct clk *mux_clk; 157 struct clk *mmc_clk; 158 unsigned long req_rate; 159 bool ddr; 160 161 bool dram_access_quirk; 162 163 struct pinctrl *pinctrl; 164 struct pinctrl_state *pins_clk_gate; 165 166 unsigned int bounce_buf_size; 167 void *bounce_buf; 168 void __iomem *bounce_iomem_buf; 169 dma_addr_t bounce_dma_addr; 170 struct sd_emmc_desc *descs; 171 dma_addr_t descs_dma_addr; 172 173 int irq; 174 175 bool vqmmc_enabled; 176 bool needs_pre_post_req; 177 178}; 179 180#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 181#define CMD_CFG_BLOCK_MODE BIT(9) 182#define CMD_CFG_R1B BIT(10) 183#define CMD_CFG_END_OF_CHAIN BIT(11) 184#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 185#define CMD_CFG_NO_RESP BIT(16) 186#define CMD_CFG_NO_CMD BIT(17) 187#define CMD_CFG_DATA_IO BIT(18) 188#define CMD_CFG_DATA_WR BIT(19) 189#define CMD_CFG_RESP_NOCRC BIT(20) 190#define CMD_CFG_RESP_128 BIT(21) 191#define CMD_CFG_RESP_NUM BIT(22) 192#define CMD_CFG_DATA_NUM BIT(23) 193#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 194#define CMD_CFG_ERROR BIT(30) 195#define CMD_CFG_OWNER BIT(31) 196 197#define CMD_DATA_MASK GENMASK(31, 2) 198#define CMD_DATA_BIG_ENDIAN BIT(1) 199#define CMD_DATA_SRAM BIT(0) 200#define CMD_RESP_MASK GENMASK(31, 1) 201#define CMD_RESP_SRAM BIT(0) 202 203static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 204{ 205 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 206 207 if (!timeout) 208 return SD_EMMC_CMD_TIMEOUT_DATA; 209 210 timeout = roundup_pow_of_two(timeout); 211 212 return min(timeout, 32768U); /* max. 2^15 ms */ 213} 214 215static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 216{ 217 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 218 return cmd->mrq->cmd; 219 else if (mmc_op_multi(cmd->opcode) && 220 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 221 return cmd->mrq->stop; 222 else 223 return NULL; 224} 225 226static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 227 struct mmc_request *mrq) 228{ 229 struct meson_host *host = mmc_priv(mmc); 230 struct mmc_data *data = mrq->data; 231 struct scatterlist *sg; 232 int i; 233 bool use_desc_chain_mode = true; 234 235 /* 236 * When Controller DMA cannot directly access DDR memory, disable 237 * support for Chain Mode to directly use the internal SRAM using 238 * the bounce buffer mode. 239 */ 240 if (host->dram_access_quirk) 241 return; 242 243 /* 244 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 245 * reported. For some strange reason this occurs in descriptor 246 * chain mode only. So let's fall back to bounce buffer mode 247 * for command SD_IO_RW_EXTENDED. 248 */ 249 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 250 return; 251 252 for_each_sg(data->sg, sg, data->sg_len, i) 253 /* check for 8 byte alignment */ 254 if (sg->offset & 7) { 255 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 256 use_desc_chain_mode = false; 257 break; 258 } 259 260 if (use_desc_chain_mode) 261 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 262} 263 264static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 265{ 266 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 267} 268 269static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 270{ 271 return data && data->flags & MMC_DATA_READ && 272 !meson_mmc_desc_chain_mode(data); 273} 274 275static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 276{ 277 struct mmc_data *data = mrq->data; 278 279 if (!data) 280 return; 281 282 meson_mmc_get_transfer_mode(mmc, mrq); 283 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 284 285 if (!meson_mmc_desc_chain_mode(data)) 286 return; 287 288 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 289 mmc_get_dma_dir(data)); 290 if (!data->sg_count) 291 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 292} 293 294static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 295 int err) 296{ 297 struct mmc_data *data = mrq->data; 298 299 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 300 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 301 mmc_get_dma_dir(data)); 302} 303 304/* 305 * Gating the clock on this controller is tricky. It seems the mmc clock 306 * is also used by the controller. It may crash during some operation if the 307 * clock is stopped. The safest thing to do, whenever possible, is to keep 308 * clock running at stop it at the pad using the pinmux. 309 */ 310static void meson_mmc_clk_gate(struct meson_host *host) 311{ 312 u32 cfg; 313 314 if (host->pins_clk_gate) { 315 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 316 } else { 317 /* 318 * If the pinmux is not provided - default to the classic and 319 * unsafe method 320 */ 321 cfg = readl(host->regs + SD_EMMC_CFG); 322 cfg |= CFG_STOP_CLOCK; 323 writel(cfg, host->regs + SD_EMMC_CFG); 324 } 325} 326 327static void meson_mmc_clk_ungate(struct meson_host *host) 328{ 329 u32 cfg; 330 331 if (host->pins_clk_gate) 332 pinctrl_select_default_state(host->dev); 333 334 /* Make sure the clock is not stopped in the controller */ 335 cfg = readl(host->regs + SD_EMMC_CFG); 336 cfg &= ~CFG_STOP_CLOCK; 337 writel(cfg, host->regs + SD_EMMC_CFG); 338} 339 340static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 341 bool ddr) 342{ 343 struct mmc_host *mmc = host->mmc; 344 int ret; 345 u32 cfg; 346 347 /* Same request - bail-out */ 348 if (host->ddr == ddr && host->req_rate == rate) 349 return 0; 350 351 /* stop clock */ 352 meson_mmc_clk_gate(host); 353 host->req_rate = 0; 354 mmc->actual_clock = 0; 355 356 /* return with clock being stopped */ 357 if (!rate) 358 return 0; 359 360 /* Stop the clock during rate change to avoid glitches */ 361 cfg = readl(host->regs + SD_EMMC_CFG); 362 cfg |= CFG_STOP_CLOCK; 363 writel(cfg, host->regs + SD_EMMC_CFG); 364 365 if (ddr) { 366 /* DDR modes require higher module clock */ 367 rate <<= 1; 368 cfg |= CFG_DDR; 369 } else { 370 cfg &= ~CFG_DDR; 371 } 372 writel(cfg, host->regs + SD_EMMC_CFG); 373 host->ddr = ddr; 374 375 ret = clk_set_rate(host->mmc_clk, rate); 376 if (ret) { 377 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 378 rate, ret); 379 return ret; 380 } 381 382 host->req_rate = rate; 383 mmc->actual_clock = clk_get_rate(host->mmc_clk); 384 385 /* We should report the real output frequency of the controller */ 386 if (ddr) { 387 host->req_rate >>= 1; 388 mmc->actual_clock >>= 1; 389 } 390 391 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 392 if (rate != mmc->actual_clock) 393 dev_dbg(host->dev, "requested rate was %lu\n", rate); 394 395 /* (re)start clock */ 396 meson_mmc_clk_ungate(host); 397 398 return 0; 399} 400 401/* 402 * The SD/eMMC IP block has an internal mux and divider used for 403 * generating the MMC clock. Use the clock framework to create and 404 * manage these clocks. 405 */ 406static int meson_mmc_clk_init(struct meson_host *host) 407{ 408 struct clk_init_data init; 409 struct clk_mux *mux; 410 struct clk_divider *div; 411 char clk_name[32]; 412 int i, ret = 0; 413 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 414 const char *clk_parent[1]; 415 u32 clk_reg; 416 417 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 418 clk_reg = CLK_ALWAYS_ON(host); 419 clk_reg |= CLK_DIV_MASK; 420 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 421 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 422 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 423 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 424 425 /* get the mux parents */ 426 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 427 struct clk *clk; 428 char name[16]; 429 430 snprintf(name, sizeof(name), "clkin%d", i); 431 clk = devm_clk_get(host->dev, name); 432 if (IS_ERR(clk)) 433 return dev_err_probe(host->dev, PTR_ERR(clk), 434 "Missing clock %s\n", name); 435 436 mux_parent_names[i] = __clk_get_name(clk); 437 } 438 439 /* create the mux */ 440 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 441 if (!mux) 442 return -ENOMEM; 443 444 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 445 init.name = clk_name; 446 init.ops = &clk_mux_ops; 447 init.flags = 0; 448 init.parent_names = mux_parent_names; 449 init.num_parents = MUX_CLK_NUM_PARENTS; 450 451 mux->reg = host->regs + SD_EMMC_CLOCK; 452 mux->shift = __ffs(CLK_SRC_MASK); 453 mux->mask = CLK_SRC_MASK >> mux->shift; 454 mux->hw.init = &init; 455 456 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 457 if (WARN_ON(IS_ERR(host->mux_clk))) 458 return PTR_ERR(host->mux_clk); 459 460 /* create the divider */ 461 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 462 if (!div) 463 return -ENOMEM; 464 465 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 466 init.name = clk_name; 467 init.ops = &clk_divider_ops; 468 init.flags = CLK_SET_RATE_PARENT; 469 clk_parent[0] = __clk_get_name(host->mux_clk); 470 init.parent_names = clk_parent; 471 init.num_parents = 1; 472 473 div->reg = host->regs + SD_EMMC_CLOCK; 474 div->shift = __ffs(CLK_DIV_MASK); 475 div->width = __builtin_popcountl(CLK_DIV_MASK); 476 div->hw.init = &init; 477 div->flags = CLK_DIVIDER_ONE_BASED; 478 479 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 480 if (WARN_ON(IS_ERR(host->mmc_clk))) 481 return PTR_ERR(host->mmc_clk); 482 483 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 484 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 485 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 486 if (ret) 487 return ret; 488 489 return clk_prepare_enable(host->mmc_clk); 490} 491 492static void meson_mmc_disable_resampling(struct meson_host *host) 493{ 494 unsigned int val = readl(host->regs + host->data->adjust); 495 496 val &= ~ADJUST_ADJ_EN; 497 writel(val, host->regs + host->data->adjust); 498} 499 500static void meson_mmc_reset_resampling(struct meson_host *host) 501{ 502 unsigned int val; 503 504 meson_mmc_disable_resampling(host); 505 506 val = readl(host->regs + host->data->adjust); 507 val &= ~ADJUST_ADJ_DELAY_MASK; 508 writel(val, host->regs + host->data->adjust); 509} 510 511static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 512{ 513 struct meson_host *host = mmc_priv(mmc); 514 unsigned int val, dly, max_dly, i; 515 int ret; 516 517 /* Resampling is done using the source clock */ 518 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 519 clk_get_rate(host->mmc_clk)); 520 521 val = readl(host->regs + host->data->adjust); 522 val |= ADJUST_ADJ_EN; 523 writel(val, host->regs + host->data->adjust); 524 525 if (mmc_doing_retune(mmc)) 526 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 527 else 528 dly = 0; 529 530 for (i = 0; i < max_dly; i++) { 531 val &= ~ADJUST_ADJ_DELAY_MASK; 532 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 533 writel(val, host->regs + host->data->adjust); 534 535 ret = mmc_send_tuning(mmc, opcode, NULL); 536 if (!ret) { 537 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 538 (dly + i) % max_dly); 539 return 0; 540 } 541 } 542 543 meson_mmc_reset_resampling(host); 544 return -EIO; 545} 546 547static int meson_mmc_prepare_ios_clock(struct meson_host *host, 548 struct mmc_ios *ios) 549{ 550 bool ddr; 551 552 switch (ios->timing) { 553 case MMC_TIMING_MMC_DDR52: 554 case MMC_TIMING_UHS_DDR50: 555 ddr = true; 556 break; 557 558 default: 559 ddr = false; 560 break; 561 } 562 563 return meson_mmc_clk_set(host, ios->clock, ddr); 564} 565 566static void meson_mmc_check_resampling(struct meson_host *host, 567 struct mmc_ios *ios) 568{ 569 switch (ios->timing) { 570 case MMC_TIMING_LEGACY: 571 case MMC_TIMING_MMC_HS: 572 case MMC_TIMING_SD_HS: 573 case MMC_TIMING_MMC_DDR52: 574 meson_mmc_disable_resampling(host); 575 break; 576 } 577} 578 579static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 580{ 581 struct meson_host *host = mmc_priv(mmc); 582 u32 bus_width, val; 583 int err; 584 585 /* 586 * GPIO regulator, only controls switching between 1v8 and 587 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 588 */ 589 switch (ios->power_mode) { 590 case MMC_POWER_OFF: 591 if (!IS_ERR(mmc->supply.vmmc)) 592 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 593 594 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 595 regulator_disable(mmc->supply.vqmmc); 596 host->vqmmc_enabled = false; 597 } 598 599 break; 600 601 case MMC_POWER_UP: 602 if (!IS_ERR(mmc->supply.vmmc)) 603 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 604 605 break; 606 607 case MMC_POWER_ON: 608 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 609 int ret = regulator_enable(mmc->supply.vqmmc); 610 611 if (ret < 0) 612 dev_err(host->dev, 613 "failed to enable vqmmc regulator\n"); 614 else 615 host->vqmmc_enabled = true; 616 } 617 618 break; 619 } 620 621 /* Bus width */ 622 switch (ios->bus_width) { 623 case MMC_BUS_WIDTH_1: 624 bus_width = CFG_BUS_WIDTH_1; 625 break; 626 case MMC_BUS_WIDTH_4: 627 bus_width = CFG_BUS_WIDTH_4; 628 break; 629 case MMC_BUS_WIDTH_8: 630 bus_width = CFG_BUS_WIDTH_8; 631 break; 632 default: 633 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 634 ios->bus_width); 635 bus_width = CFG_BUS_WIDTH_4; 636 } 637 638 val = readl(host->regs + SD_EMMC_CFG); 639 val &= ~CFG_BUS_WIDTH_MASK; 640 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 641 writel(val, host->regs + SD_EMMC_CFG); 642 643 meson_mmc_check_resampling(host, ios); 644 err = meson_mmc_prepare_ios_clock(host, ios); 645 if (err) 646 dev_err(host->dev, "Failed to set clock: %d\n,", err); 647 648 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 649} 650 651static void meson_mmc_request_done(struct mmc_host *mmc, 652 struct mmc_request *mrq) 653{ 654 struct meson_host *host = mmc_priv(mmc); 655 656 host->cmd = NULL; 657 if (host->needs_pre_post_req) 658 meson_mmc_post_req(mmc, mrq, 0); 659 mmc_request_done(host->mmc, mrq); 660} 661 662static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 663{ 664 struct meson_host *host = mmc_priv(mmc); 665 u32 cfg, blksz_old; 666 667 cfg = readl(host->regs + SD_EMMC_CFG); 668 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 669 670 if (!is_power_of_2(blksz)) 671 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 672 673 blksz = ilog2(blksz); 674 675 /* check if block-size matches, if not update */ 676 if (blksz == blksz_old) 677 return; 678 679 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 680 blksz_old, blksz); 681 682 cfg &= ~CFG_BLK_LEN_MASK; 683 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 684 writel(cfg, host->regs + SD_EMMC_CFG); 685} 686 687static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 688{ 689 if (cmd->flags & MMC_RSP_PRESENT) { 690 if (cmd->flags & MMC_RSP_136) 691 *cmd_cfg |= CMD_CFG_RESP_128; 692 *cmd_cfg |= CMD_CFG_RESP_NUM; 693 694 if (!(cmd->flags & MMC_RSP_CRC)) 695 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 696 697 if (cmd->flags & MMC_RSP_BUSY) 698 *cmd_cfg |= CMD_CFG_R1B; 699 } else { 700 *cmd_cfg |= CMD_CFG_NO_RESP; 701 } 702} 703 704static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 705{ 706 struct meson_host *host = mmc_priv(mmc); 707 struct sd_emmc_desc *desc = host->descs; 708 struct mmc_data *data = host->cmd->data; 709 struct scatterlist *sg; 710 u32 start; 711 int i; 712 713 if (data->flags & MMC_DATA_WRITE) 714 cmd_cfg |= CMD_CFG_DATA_WR; 715 716 if (data->blocks > 1) { 717 cmd_cfg |= CMD_CFG_BLOCK_MODE; 718 meson_mmc_set_blksz(mmc, data->blksz); 719 } 720 721 for_each_sg(data->sg, sg, data->sg_count, i) { 722 unsigned int len = sg_dma_len(sg); 723 724 if (data->blocks > 1) 725 len /= data->blksz; 726 727 desc[i].cmd_cfg = cmd_cfg; 728 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 729 if (i > 0) 730 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 731 desc[i].cmd_arg = host->cmd->arg; 732 desc[i].cmd_resp = 0; 733 desc[i].cmd_data = sg_dma_address(sg); 734 } 735 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 736 737 dma_wmb(); /* ensure descriptor is written before kicked */ 738 start = host->descs_dma_addr | START_DESC_BUSY; 739 writel(start, host->regs + SD_EMMC_START); 740} 741 742/* local sg copy for dram_access_quirk */ 743static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data, 744 size_t buflen, bool to_buffer) 745{ 746 unsigned int sg_flags = SG_MITER_ATOMIC; 747 struct scatterlist *sgl = data->sg; 748 unsigned int nents = data->sg_len; 749 struct sg_mapping_iter miter; 750 unsigned int offset = 0; 751 752 if (to_buffer) 753 sg_flags |= SG_MITER_FROM_SG; 754 else 755 sg_flags |= SG_MITER_TO_SG; 756 757 sg_miter_start(&miter, sgl, nents, sg_flags); 758 759 while ((offset < buflen) && sg_miter_next(&miter)) { 760 unsigned int buf_offset = 0; 761 unsigned int len, left; 762 u32 *buf = miter.addr; 763 764 len = min(miter.length, buflen - offset); 765 left = len; 766 767 if (to_buffer) { 768 do { 769 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset); 770 771 buf_offset += 4; 772 left -= 4; 773 } while (left); 774 } else { 775 do { 776 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset); 777 778 buf_offset += 4; 779 left -= 4; 780 } while (left); 781 } 782 783 offset += len; 784 } 785 786 sg_miter_stop(&miter); 787} 788 789static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 790{ 791 struct meson_host *host = mmc_priv(mmc); 792 struct mmc_data *data = cmd->data; 793 u32 cmd_cfg = 0, cmd_data = 0; 794 unsigned int xfer_bytes = 0; 795 796 /* Setup descriptors */ 797 dma_rmb(); 798 799 host->cmd = cmd; 800 801 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 802 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 803 804 meson_mmc_set_response_bits(cmd, &cmd_cfg); 805 806 /* data? */ 807 if (data) { 808 data->bytes_xfered = 0; 809 cmd_cfg |= CMD_CFG_DATA_IO; 810 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 811 ilog2(meson_mmc_get_timeout_msecs(data))); 812 813 if (meson_mmc_desc_chain_mode(data)) { 814 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 815 return; 816 } 817 818 if (data->blocks > 1) { 819 cmd_cfg |= CMD_CFG_BLOCK_MODE; 820 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 821 data->blocks); 822 meson_mmc_set_blksz(mmc, data->blksz); 823 } else { 824 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 825 } 826 827 xfer_bytes = data->blksz * data->blocks; 828 if (data->flags & MMC_DATA_WRITE) { 829 cmd_cfg |= CMD_CFG_DATA_WR; 830 WARN_ON(xfer_bytes > host->bounce_buf_size); 831 if (host->dram_access_quirk) 832 meson_mmc_copy_buffer(host, data, xfer_bytes, true); 833 else 834 sg_copy_to_buffer(data->sg, data->sg_len, 835 host->bounce_buf, xfer_bytes); 836 dma_wmb(); 837 } 838 839 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 840 } else { 841 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 842 ilog2(SD_EMMC_CMD_TIMEOUT)); 843 } 844 845 /* Last descriptor */ 846 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 847 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 848 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 849 writel(0, host->regs + SD_EMMC_CMD_RSP); 850 wmb(); /* ensure descriptor is written before kicked */ 851 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 852} 853 854static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data) 855{ 856 struct scatterlist *sg; 857 int i; 858 859 /* Reject request if any element offset or size is not 32bit aligned */ 860 for_each_sg(data->sg, sg, data->sg_len, i) { 861 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || 862 !IS_ALIGNED(sg->length, sizeof(u32))) { 863 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n", 864 data->sg->offset, data->sg->length); 865 return -EINVAL; 866 } 867 } 868 869 return 0; 870} 871 872static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 873{ 874 struct meson_host *host = mmc_priv(mmc); 875 host->needs_pre_post_req = mrq->data && 876 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 877 878 /* 879 * The memory at the end of the controller used as bounce buffer for 880 * the dram_access_quirk only accepts 32bit read/write access, 881 * check the aligment and length of the data before starting the request. 882 */ 883 if (host->dram_access_quirk && mrq->data) { 884 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data); 885 if (mrq->cmd->error) { 886 mmc_request_done(mmc, mrq); 887 return; 888 } 889 } 890 891 if (host->needs_pre_post_req) { 892 meson_mmc_get_transfer_mode(mmc, mrq); 893 if (!meson_mmc_desc_chain_mode(mrq->data)) 894 host->needs_pre_post_req = false; 895 } 896 897 if (host->needs_pre_post_req) 898 meson_mmc_pre_req(mmc, mrq); 899 900 /* Stop execution */ 901 writel(0, host->regs + SD_EMMC_START); 902 903 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 904} 905 906static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 907{ 908 struct meson_host *host = mmc_priv(mmc); 909 910 if (cmd->flags & MMC_RSP_136) { 911 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 912 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 913 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 914 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 915 } else if (cmd->flags & MMC_RSP_PRESENT) { 916 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 917 } 918} 919 920static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 921{ 922 struct meson_host *host = dev_id; 923 struct mmc_command *cmd; 924 struct mmc_data *data; 925 u32 irq_en, status, raw_status; 926 irqreturn_t ret = IRQ_NONE; 927 928 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 929 raw_status = readl(host->regs + SD_EMMC_STATUS); 930 status = raw_status & irq_en; 931 932 if (!status) { 933 dev_dbg(host->dev, 934 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 935 irq_en, raw_status); 936 return IRQ_NONE; 937 } 938 939 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 940 return IRQ_NONE; 941 942 /* ack all raised interrupts */ 943 writel(status, host->regs + SD_EMMC_STATUS); 944 945 cmd = host->cmd; 946 data = cmd->data; 947 cmd->error = 0; 948 if (status & IRQ_CRC_ERR) { 949 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 950 cmd->error = -EILSEQ; 951 ret = IRQ_WAKE_THREAD; 952 goto out; 953 } 954 955 if (status & IRQ_TIMEOUTS) { 956 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 957 cmd->error = -ETIMEDOUT; 958 ret = IRQ_WAKE_THREAD; 959 goto out; 960 } 961 962 meson_mmc_read_resp(host->mmc, cmd); 963 964 if (status & IRQ_SDIO) { 965 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 966 ret = IRQ_HANDLED; 967 } 968 969 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 970 if (data && !cmd->error) 971 data->bytes_xfered = data->blksz * data->blocks; 972 973 return IRQ_WAKE_THREAD; 974 } 975 976out: 977 if (cmd->error) { 978 /* Stop desc in case of errors */ 979 u32 start = readl(host->regs + SD_EMMC_START); 980 981 start &= ~START_DESC_BUSY; 982 writel(start, host->regs + SD_EMMC_START); 983 } 984 985 return ret; 986} 987 988static int meson_mmc_wait_desc_stop(struct meson_host *host) 989{ 990 u32 status; 991 992 /* 993 * It may sometimes take a while for it to actually halt. Here, we 994 * are giving it 5ms to comply 995 * 996 * If we don't confirm the descriptor is stopped, it might raise new 997 * IRQs after we have called mmc_request_done() which is bad. 998 */ 999 1000 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 1001 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 1002 100, 5000); 1003} 1004 1005static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 1006{ 1007 struct meson_host *host = dev_id; 1008 struct mmc_command *next_cmd, *cmd = host->cmd; 1009 struct mmc_data *data; 1010 unsigned int xfer_bytes; 1011 1012 if (WARN_ON(!cmd)) 1013 return IRQ_NONE; 1014 1015 if (cmd->error) { 1016 meson_mmc_wait_desc_stop(host); 1017 meson_mmc_request_done(host->mmc, cmd->mrq); 1018 1019 return IRQ_HANDLED; 1020 } 1021 1022 data = cmd->data; 1023 if (meson_mmc_bounce_buf_read(data)) { 1024 xfer_bytes = data->blksz * data->blocks; 1025 WARN_ON(xfer_bytes > host->bounce_buf_size); 1026 if (host->dram_access_quirk) 1027 meson_mmc_copy_buffer(host, data, xfer_bytes, false); 1028 else 1029 sg_copy_from_buffer(data->sg, data->sg_len, 1030 host->bounce_buf, xfer_bytes); 1031 } 1032 1033 next_cmd = meson_mmc_get_next_command(cmd); 1034 if (next_cmd) 1035 meson_mmc_start_cmd(host->mmc, next_cmd); 1036 else 1037 meson_mmc_request_done(host->mmc, cmd->mrq); 1038 1039 return IRQ_HANDLED; 1040} 1041 1042/* 1043 * NOTE: we only need this until the GPIO/pinctrl driver can handle 1044 * interrupts. For now, the MMC core will use this for polling. 1045 */ 1046static int meson_mmc_get_cd(struct mmc_host *mmc) 1047{ 1048 int status = mmc_gpio_get_cd(mmc); 1049 1050 if (status == -ENOSYS) 1051 return 1; /* assume present */ 1052 1053 return status; 1054} 1055 1056static void meson_mmc_cfg_init(struct meson_host *host) 1057{ 1058 u32 cfg = 0; 1059 1060 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 1061 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 1062 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 1063 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 1064 1065 /* abort chain on R/W errors */ 1066 cfg |= CFG_ERR_ABORT; 1067 1068 writel(cfg, host->regs + SD_EMMC_CFG); 1069} 1070 1071static int meson_mmc_card_busy(struct mmc_host *mmc) 1072{ 1073 struct meson_host *host = mmc_priv(mmc); 1074 u32 regval; 1075 1076 regval = readl(host->regs + SD_EMMC_STATUS); 1077 1078 /* We are only interrested in lines 0 to 3, so mask the other ones */ 1079 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 1080} 1081 1082static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1083{ 1084 int ret; 1085 1086 /* vqmmc regulator is available */ 1087 if (!IS_ERR(mmc->supply.vqmmc)) { 1088 /* 1089 * The usual amlogic setup uses a GPIO to switch from one 1090 * regulator to the other. While the voltage ramp up is 1091 * pretty fast, care must be taken when switching from 3.3v 1092 * to 1.8v. Please make sure the regulator framework is aware 1093 * of your own regulator constraints 1094 */ 1095 ret = mmc_regulator_set_vqmmc(mmc, ios); 1096 return ret < 0 ? ret : 0; 1097 } 1098 1099 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1100 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1101 return 0; 1102 1103 return -EINVAL; 1104} 1105 1106static const struct mmc_host_ops meson_mmc_ops = { 1107 .request = meson_mmc_request, 1108 .set_ios = meson_mmc_set_ios, 1109 .get_cd = meson_mmc_get_cd, 1110 .pre_req = meson_mmc_pre_req, 1111 .post_req = meson_mmc_post_req, 1112 .execute_tuning = meson_mmc_resampling_tuning, 1113 .card_busy = meson_mmc_card_busy, 1114 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1115}; 1116 1117static int meson_mmc_probe(struct platform_device *pdev) 1118{ 1119 struct resource *res; 1120 struct meson_host *host; 1121 struct mmc_host *mmc; 1122 int ret; 1123 1124 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host)); 1125 if (!mmc) 1126 return -ENOMEM; 1127 host = mmc_priv(mmc); 1128 host->mmc = mmc; 1129 host->dev = &pdev->dev; 1130 dev_set_drvdata(&pdev->dev, host); 1131 1132 /* The G12A SDIO Controller needs an SRAM bounce buffer */ 1133 host->dram_access_quirk = device_property_read_bool(&pdev->dev, 1134 "amlogic,dram-access-quirk"); 1135 1136 /* Get regulators and the supported OCR mask */ 1137 host->vqmmc_enabled = false; 1138 ret = mmc_regulator_get_supply(mmc); 1139 if (ret) 1140 return ret; 1141 1142 ret = mmc_of_parse(mmc); 1143 if (ret) 1144 return dev_err_probe(&pdev->dev, ret, "error parsing DT\n"); 1145 1146 host->data = (struct meson_mmc_data *) 1147 of_device_get_match_data(&pdev->dev); 1148 if (!host->data) 1149 return -EINVAL; 1150 1151 ret = device_reset_optional(&pdev->dev); 1152 if (ret) 1153 return dev_err_probe(&pdev->dev, ret, "device reset failed\n"); 1154 1155 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1156 host->regs = devm_ioremap_resource(&pdev->dev, res); 1157 if (IS_ERR(host->regs)) 1158 return PTR_ERR(host->regs); 1159 1160 host->irq = platform_get_irq(pdev, 0); 1161 if (host->irq < 0) 1162 return host->irq; 1163 1164 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1165 if (IS_ERR(host->pinctrl)) 1166 return PTR_ERR(host->pinctrl); 1167 1168 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1169 "clk-gate"); 1170 if (IS_ERR(host->pins_clk_gate)) { 1171 dev_warn(&pdev->dev, 1172 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1173 host->pins_clk_gate = NULL; 1174 } 1175 1176 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1177 if (IS_ERR(host->core_clk)) 1178 return PTR_ERR(host->core_clk); 1179 1180 ret = clk_prepare_enable(host->core_clk); 1181 if (ret) 1182 return ret; 1183 1184 ret = meson_mmc_clk_init(host); 1185 if (ret) 1186 goto err_core_clk; 1187 1188 /* set config to sane default */ 1189 meson_mmc_cfg_init(host); 1190 1191 /* Stop execution */ 1192 writel(0, host->regs + SD_EMMC_START); 1193 1194 /* clear, ack and enable interrupts */ 1195 writel(0, host->regs + SD_EMMC_IRQ_EN); 1196 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1197 host->regs + SD_EMMC_STATUS); 1198 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1199 host->regs + SD_EMMC_IRQ_EN); 1200 1201 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1202 meson_mmc_irq_thread, IRQF_ONESHOT, 1203 dev_name(&pdev->dev), host); 1204 if (ret) 1205 goto err_init_clk; 1206 1207 mmc->caps |= MMC_CAP_CMD23; 1208 if (host->dram_access_quirk) { 1209 /* Limit segments to 1 due to low available sram memory */ 1210 mmc->max_segs = 1; 1211 /* Limit to the available sram memory */ 1212 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN / 1213 mmc->max_blk_size; 1214 } else { 1215 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1216 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / 1217 sizeof(struct sd_emmc_desc); 1218 } 1219 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1220 mmc->max_seg_size = mmc->max_req_size; 1221 1222 /* 1223 * At the moment, we don't know how to reliably enable HS400. 1224 * From the different datasheets, it is not even clear if this mode 1225 * is officially supported by any of the SoCs 1226 */ 1227 mmc->caps2 &= ~MMC_CAP2_HS400; 1228 1229 if (host->dram_access_quirk) { 1230 /* 1231 * The MMC Controller embeds 1,5KiB of internal SRAM 1232 * that can be used to be used as bounce buffer. 1233 * In the case of the G12A SDIO controller, use these 1234 * instead of the DDR memory 1235 */ 1236 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN; 1237 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF; 1238 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF; 1239 } else { 1240 /* data bounce buffer */ 1241 host->bounce_buf_size = mmc->max_req_size; 1242 host->bounce_buf = 1243 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1244 &host->bounce_dma_addr, GFP_KERNEL); 1245 if (host->bounce_buf == NULL) { 1246 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1247 ret = -ENOMEM; 1248 goto err_free_irq; 1249 } 1250 } 1251 1252 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1253 &host->descs_dma_addr, GFP_KERNEL); 1254 if (!host->descs) { 1255 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1256 ret = -ENOMEM; 1257 goto err_bounce_buf; 1258 } 1259 1260 mmc->ops = &meson_mmc_ops; 1261 ret = mmc_add_host(mmc); 1262 if (ret) 1263 goto err_free_irq; 1264 1265 return 0; 1266 1267err_bounce_buf: 1268 if (!host->dram_access_quirk) 1269 dma_free_coherent(host->dev, host->bounce_buf_size, 1270 host->bounce_buf, host->bounce_dma_addr); 1271err_free_irq: 1272 free_irq(host->irq, host); 1273err_init_clk: 1274 clk_disable_unprepare(host->mmc_clk); 1275err_core_clk: 1276 clk_disable_unprepare(host->core_clk); 1277 return ret; 1278} 1279 1280static int meson_mmc_remove(struct platform_device *pdev) 1281{ 1282 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1283 1284 mmc_remove_host(host->mmc); 1285 1286 /* disable interrupts */ 1287 writel(0, host->regs + SD_EMMC_IRQ_EN); 1288 free_irq(host->irq, host); 1289 1290 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1291 host->descs, host->descs_dma_addr); 1292 1293 if (!host->dram_access_quirk) 1294 dma_free_coherent(host->dev, host->bounce_buf_size, 1295 host->bounce_buf, host->bounce_dma_addr); 1296 1297 clk_disable_unprepare(host->mmc_clk); 1298 clk_disable_unprepare(host->core_clk); 1299 1300 return 0; 1301} 1302 1303static const struct meson_mmc_data meson_gx_data = { 1304 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1305 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1306 .always_on = CLK_V2_ALWAYS_ON, 1307 .adjust = SD_EMMC_ADJUST, 1308}; 1309 1310static const struct meson_mmc_data meson_axg_data = { 1311 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1312 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1313 .always_on = CLK_V3_ALWAYS_ON, 1314 .adjust = SD_EMMC_V3_ADJUST, 1315}; 1316 1317static const struct of_device_id meson_mmc_of_match[] = { 1318 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1319 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1320 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1321 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1322 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1323 {} 1324}; 1325MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1326 1327static struct platform_driver meson_mmc_driver = { 1328 .probe = meson_mmc_probe, 1329 .remove = meson_mmc_remove, 1330 .driver = { 1331 .name = DRIVER_NAME, 1332 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1333 .of_match_table = of_match_ptr(meson_mmc_of_match), 1334 }, 1335}; 1336 1337module_platform_driver(meson_mmc_driver); 1338 1339MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1340MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1341MODULE_LICENSE("GPL v2"); 1342