1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10#include <linux/blkdev.h> 11#include <linux/clk.h> 12#include <linux/debugfs.h> 13#include <linux/device.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/init.h> 17#include <linux/interrupt.h> 18#include <linux/iopoll.h> 19#include <linux/ioport.h> 20#include <linux/module.h> 21#include <linux/platform_device.h> 22#include <linux/pm_runtime.h> 23#include <linux/seq_file.h> 24#include <linux/slab.h> 25#include <linux/stat.h> 26#include <linux/delay.h> 27#include <linux/irq.h> 28#include <linux/mmc/card.h> 29#include <linux/mmc/host.h> 30#include <linux/mmc/mmc.h> 31#include <linux/mmc/sd.h> 32#include <linux/mmc/sdio.h> 33#include <linux/bitops.h> 34#include <linux/regulator/consumer.h> 35#include <linux/of.h> 36#include <linux/of_gpio.h> 37#include <linux/mmc/slot-gpio.h> 38 39#include "dw_mmc.h" 40 41/* Common flag combinations */ 42#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ 43 SDMMC_INT_HTO | SDMMC_INT_SBE | \ 44 SDMMC_INT_EBE | SDMMC_INT_HLE) 45#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ 46 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE) 47#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ 48 DW_MCI_CMD_ERROR_FLAGS) 49#define DW_MCI_SEND_STATUS 1 50#define DW_MCI_RECV_STATUS 2 51#define DW_MCI_DMA_THRESHOLD 16 52 53#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ 54#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */ 55 56#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 57 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 58 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ 59 SDMMC_IDMAC_INT_TI) 60 61#define DESC_RING_BUF_SZ PAGE_SIZE 62 63struct idmac_desc_64addr { 64 u32 des0; /* Control Descriptor */ 65#define IDMAC_OWN_CLR64(x) \ 66 !((x) & cpu_to_le32(IDMAC_DES0_OWN)) 67 68 u32 des1; /* Reserved */ 69 70 u32 des2; /*Buffer sizes */ 71#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ 72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ 73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) 74 75 u32 des3; /* Reserved */ 76 77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ 78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ 79 80 u32 des6; /* Lower 32-bits of Next Descriptor Address */ 81 u32 des7; /* Upper 32-bits of Next Descriptor Address */ 82}; 83 84struct idmac_desc { 85 __le32 des0; /* Control Descriptor */ 86#define IDMAC_DES0_DIC BIT(1) 87#define IDMAC_DES0_LD BIT(2) 88#define IDMAC_DES0_FD BIT(3) 89#define IDMAC_DES0_CH BIT(4) 90#define IDMAC_DES0_ER BIT(5) 91#define IDMAC_DES0_CES BIT(30) 92#define IDMAC_DES0_OWN BIT(31) 93 94 __le32 des1; /* Buffer sizes */ 95#define IDMAC_SET_BUFFER1_SIZE(d, s) \ 96 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff))) 97 98 __le32 des2; /* buffer 1 physical address */ 99 100 __le32 des3; /* buffer 2 physical address */ 101}; 102 103/* Each descriptor can transfer up to 4KB of data in chained mode */ 104#define DW_MCI_DESC_DATA_LENGTH 0x1000 105 106#if defined(CONFIG_DEBUG_FS) 107static int dw_mci_req_show(struct seq_file *s, void *v) 108{ 109 struct dw_mci_slot *slot = s->private; 110 struct mmc_request *mrq; 111 struct mmc_command *cmd; 112 struct mmc_command *stop; 113 struct mmc_data *data; 114 115 /* Make sure we get a consistent snapshot */ 116 spin_lock_bh(&slot->host->lock); 117 mrq = slot->mrq; 118 119 if (mrq) { 120 cmd = mrq->cmd; 121 data = mrq->data; 122 stop = mrq->stop; 123 124 if (cmd) 125 seq_printf(s, 126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 127 cmd->opcode, cmd->arg, cmd->flags, 128 cmd->resp[0], cmd->resp[1], cmd->resp[2], 129 cmd->resp[2], cmd->error); 130 if (data) 131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", 132 data->bytes_xfered, data->blocks, 133 data->blksz, data->flags, data->error); 134 if (stop) 135 seq_printf(s, 136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", 137 stop->opcode, stop->arg, stop->flags, 138 stop->resp[0], stop->resp[1], stop->resp[2], 139 stop->resp[2], stop->error); 140 } 141 142 spin_unlock_bh(&slot->host->lock); 143 144 return 0; 145} 146DEFINE_SHOW_ATTRIBUTE(dw_mci_req); 147 148static int dw_mci_regs_show(struct seq_file *s, void *v) 149{ 150 struct dw_mci *host = s->private; 151 152 pm_runtime_get_sync(host->dev); 153 154 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS)); 155 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS)); 156 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD)); 157 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); 158 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK)); 159 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA)); 160 161 pm_runtime_put_autosuspend(host->dev); 162 163 return 0; 164} 165DEFINE_SHOW_ATTRIBUTE(dw_mci_regs); 166 167static void dw_mci_init_debugfs(struct dw_mci_slot *slot) 168{ 169 struct mmc_host *mmc = slot->mmc; 170 struct dw_mci *host = slot->host; 171 struct dentry *root; 172 173 root = mmc->debugfs_root; 174 if (!root) 175 return; 176 177 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops); 178 debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops); 179 debugfs_create_u32("state", S_IRUSR, root, &host->state); 180 debugfs_create_xul("pending_events", S_IRUSR, root, 181 &host->pending_events); 182 debugfs_create_xul("completed_events", S_IRUSR, root, 183 &host->completed_events); 184} 185#endif /* defined(CONFIG_DEBUG_FS) */ 186 187static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) 188{ 189 u32 ctrl; 190 191 ctrl = mci_readl(host, CTRL); 192 ctrl |= reset; 193 mci_writel(host, CTRL, ctrl); 194 195 /* wait till resets clear */ 196 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, 197 !(ctrl & reset), 198 1, 500 * USEC_PER_MSEC)) { 199 dev_err(host->dev, 200 "Timeout resetting block (ctrl reset %#x)\n", 201 ctrl & reset); 202 return false; 203 } 204 205 return true; 206} 207 208static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) 209{ 210 u32 status; 211 212 /* 213 * Databook says that before issuing a new data transfer command 214 * we need to check to see if the card is busy. Data transfer commands 215 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. 216 * 217 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is 218 * expected. 219 */ 220 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && 221 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { 222 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 223 status, 224 !(status & SDMMC_STATUS_BUSY), 225 10, 500 * USEC_PER_MSEC)) 226 dev_err(host->dev, "Busy; trying anyway\n"); 227 } 228} 229 230static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) 231{ 232 struct dw_mci *host = slot->host; 233 unsigned int cmd_status = 0; 234 235 mci_writel(host, CMDARG, arg); 236 wmb(); /* drain writebuffer */ 237 dw_mci_wait_while_busy(host, cmd); 238 mci_writel(host, CMD, SDMMC_CMD_START | cmd); 239 240 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, 241 !(cmd_status & SDMMC_CMD_START), 242 1, 500 * USEC_PER_MSEC)) 243 dev_err(&slot->mmc->class_dev, 244 "Timeout sending command (cmd %#x arg %#x status %#x)\n", 245 cmd, arg, cmd_status); 246} 247 248static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) 249{ 250 struct dw_mci_slot *slot = mmc_priv(mmc); 251 struct dw_mci *host = slot->host; 252 u32 cmdr; 253 254 cmd->error = -EINPROGRESS; 255 cmdr = cmd->opcode; 256 257 if (cmd->opcode == MMC_STOP_TRANSMISSION || 258 cmd->opcode == MMC_GO_IDLE_STATE || 259 cmd->opcode == MMC_GO_INACTIVE_STATE || 260 (cmd->opcode == SD_IO_RW_DIRECT && 261 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) 262 cmdr |= SDMMC_CMD_STOP; 263 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) 264 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; 265 266 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 267 u32 clk_en_a; 268 269 /* Special bit makes CMD11 not die */ 270 cmdr |= SDMMC_CMD_VOLT_SWITCH; 271 272 /* Change state to continue to handle CMD11 weirdness */ 273 WARN_ON(slot->host->state != STATE_SENDING_CMD); 274 slot->host->state = STATE_SENDING_CMD11; 275 276 /* 277 * We need to disable low power mode (automatic clock stop) 278 * while doing voltage switch so we don't confuse the card, 279 * since stopping the clock is a specific part of the UHS 280 * voltage change dance. 281 * 282 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be 283 * unconditionally turned back on in dw_mci_setup_bus() if it's 284 * ever called with a non-zero clock. That shouldn't happen 285 * until the voltage change is all done. 286 */ 287 clk_en_a = mci_readl(host, CLKENA); 288 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); 289 mci_writel(host, CLKENA, clk_en_a); 290 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 291 SDMMC_CMD_PRV_DAT_WAIT, 0); 292 } 293 294 if (cmd->flags & MMC_RSP_PRESENT) { 295 /* We expect a response, so set this bit */ 296 cmdr |= SDMMC_CMD_RESP_EXP; 297 if (cmd->flags & MMC_RSP_136) 298 cmdr |= SDMMC_CMD_RESP_LONG; 299 } 300 301 if (cmd->flags & MMC_RSP_CRC) 302 cmdr |= SDMMC_CMD_RESP_CRC; 303 304 if (cmd->data) { 305 cmdr |= SDMMC_CMD_DAT_EXP; 306 if (cmd->data->flags & MMC_DATA_WRITE) 307 cmdr |= SDMMC_CMD_DAT_WR; 308 } 309 310 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) 311 cmdr |= SDMMC_CMD_USE_HOLD_REG; 312 313 return cmdr; 314} 315 316static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) 317{ 318 struct mmc_command *stop; 319 u32 cmdr; 320 321 if (!cmd->data) 322 return 0; 323 324 stop = &host->stop_abort; 325 cmdr = cmd->opcode; 326 memset(stop, 0, sizeof(struct mmc_command)); 327 328 if (cmdr == MMC_READ_SINGLE_BLOCK || 329 cmdr == MMC_READ_MULTIPLE_BLOCK || 330 cmdr == MMC_WRITE_BLOCK || 331 cmdr == MMC_WRITE_MULTIPLE_BLOCK || 332 cmdr == MMC_SEND_TUNING_BLOCK || 333 cmdr == MMC_SEND_TUNING_BLOCK_HS200) { 334 stop->opcode = MMC_STOP_TRANSMISSION; 335 stop->arg = 0; 336 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; 337 } else if (cmdr == SD_IO_RW_EXTENDED) { 338 stop->opcode = SD_IO_RW_DIRECT; 339 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 340 ((cmd->arg >> 28) & 0x7); 341 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; 342 } else { 343 return 0; 344 } 345 346 cmdr = stop->opcode | SDMMC_CMD_STOP | 347 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; 348 349 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) 350 cmdr |= SDMMC_CMD_USE_HOLD_REG; 351 352 return cmdr; 353} 354 355static inline void dw_mci_set_cto(struct dw_mci *host) 356{ 357 unsigned int cto_clks; 358 unsigned int cto_div; 359 unsigned int cto_ms; 360 unsigned long irqflags; 361 362 cto_clks = mci_readl(host, TMOUT) & 0xff; 363 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 364 if (cto_div == 0) 365 cto_div = 1; 366 367 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 368 host->bus_hz); 369 370 /* add a bit spare time */ 371 cto_ms += 10; 372 373 /* 374 * The durations we're working with are fairly short so we have to be 375 * extra careful about synchronization here. Specifically in hardware a 376 * command timeout is _at most_ 5.1 ms, so that means we expect an 377 * interrupt (either command done or timeout) to come rather quickly 378 * after the mci_writel. ...but just in case we have a long interrupt 379 * latency let's add a bit of paranoia. 380 * 381 * In general we'll assume that at least an interrupt will be asserted 382 * in hardware by the time the cto_timer runs. ...and if it hasn't 383 * been asserted in hardware by that time then we'll assume it'll never 384 * come. 385 */ 386 spin_lock_irqsave(&host->irq_lock, irqflags); 387 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 388 mod_timer(&host->cto_timer, 389 jiffies + msecs_to_jiffies(cto_ms) + 1); 390 spin_unlock_irqrestore(&host->irq_lock, irqflags); 391} 392 393static void dw_mci_start_command(struct dw_mci *host, 394 struct mmc_command *cmd, u32 cmd_flags) 395{ 396 host->cmd = cmd; 397 dev_vdbg(host->dev, 398 "start command: ARGR=0x%08x CMDR=0x%08x\n", 399 cmd->arg, cmd_flags); 400 401 mci_writel(host, CMDARG, cmd->arg); 402 wmb(); /* drain writebuffer */ 403 dw_mci_wait_while_busy(host, cmd_flags); 404 405 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); 406 407 /* response expected command only */ 408 if (cmd_flags & SDMMC_CMD_RESP_EXP) 409 dw_mci_set_cto(host); 410} 411 412static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) 413{ 414 struct mmc_command *stop = &host->stop_abort; 415 416 dw_mci_start_command(host, stop, host->stop_cmdr); 417} 418 419/* DMA interface functions */ 420static void dw_mci_stop_dma(struct dw_mci *host) 421{ 422 if (host->using_dma) { 423 host->dma_ops->stop(host); 424 host->dma_ops->cleanup(host); 425 } 426 427 /* Data transfer was stopped by the interrupt handler */ 428 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 429} 430 431static void dw_mci_dma_cleanup(struct dw_mci *host) 432{ 433 struct mmc_data *data = host->data; 434 435 if (data && data->host_cookie == COOKIE_MAPPED) { 436 dma_unmap_sg(host->dev, 437 data->sg, 438 data->sg_len, 439 mmc_get_dma_dir(data)); 440 data->host_cookie = COOKIE_UNMAPPED; 441 } 442} 443 444static void dw_mci_idmac_reset(struct dw_mci *host) 445{ 446 u32 bmod = mci_readl(host, BMOD); 447 /* Software reset of DMA */ 448 bmod |= SDMMC_IDMAC_SWRESET; 449 mci_writel(host, BMOD, bmod); 450} 451 452static void dw_mci_idmac_stop_dma(struct dw_mci *host) 453{ 454 u32 temp; 455 456 /* Disable and reset the IDMAC interface */ 457 temp = mci_readl(host, CTRL); 458 temp &= ~SDMMC_CTRL_USE_IDMAC; 459 temp |= SDMMC_CTRL_DMA_RESET; 460 mci_writel(host, CTRL, temp); 461 462 /* Stop the IDMAC running */ 463 temp = mci_readl(host, BMOD); 464 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); 465 temp |= SDMMC_IDMAC_SWRESET; 466 mci_writel(host, BMOD, temp); 467} 468 469static void dw_mci_dmac_complete_dma(void *arg) 470{ 471 struct dw_mci *host = arg; 472 struct mmc_data *data = host->data; 473 474 dev_vdbg(host->dev, "DMA complete\n"); 475 476 if ((host->use_dma == TRANS_MODE_EDMAC) && 477 data && (data->flags & MMC_DATA_READ)) 478 /* Invalidate cache after read */ 479 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), 480 data->sg, 481 data->sg_len, 482 DMA_FROM_DEVICE); 483 484 host->dma_ops->cleanup(host); 485 486 /* 487 * If the card was removed, data will be NULL. No point in trying to 488 * send the stop command or waiting for NBUSY in this case. 489 */ 490 if (data) { 491 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 492 tasklet_schedule(&host->tasklet); 493 } 494} 495 496static int dw_mci_idmac_init(struct dw_mci *host) 497{ 498 int i; 499 500 if (host->dma_64bit_address == 1) { 501 struct idmac_desc_64addr *p; 502 /* Number of descriptors in the ring buffer */ 503 host->ring_size = 504 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr); 505 506 /* Forward link the descriptor list */ 507 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; 508 i++, p++) { 509 p->des6 = (host->sg_dma + 510 (sizeof(struct idmac_desc_64addr) * 511 (i + 1))) & 0xffffffff; 512 513 p->des7 = (u64)(host->sg_dma + 514 (sizeof(struct idmac_desc_64addr) * 515 (i + 1))) >> 32; 516 /* Initialize reserved and buffer size fields to "0" */ 517 p->des0 = 0; 518 p->des1 = 0; 519 p->des2 = 0; 520 p->des3 = 0; 521 } 522 523 /* Set the last descriptor as the end-of-ring descriptor */ 524 p->des6 = host->sg_dma & 0xffffffff; 525 p->des7 = (u64)host->sg_dma >> 32; 526 p->des0 = IDMAC_DES0_ER; 527 528 } else { 529 struct idmac_desc *p; 530 /* Number of descriptors in the ring buffer */ 531 host->ring_size = 532 DESC_RING_BUF_SZ / sizeof(struct idmac_desc); 533 534 /* Forward link the descriptor list */ 535 for (i = 0, p = host->sg_cpu; 536 i < host->ring_size - 1; 537 i++, p++) { 538 p->des3 = cpu_to_le32(host->sg_dma + 539 (sizeof(struct idmac_desc) * (i + 1))); 540 p->des0 = 0; 541 p->des1 = 0; 542 } 543 544 /* Set the last descriptor as the end-of-ring descriptor */ 545 p->des3 = cpu_to_le32(host->sg_dma); 546 p->des0 = cpu_to_le32(IDMAC_DES0_ER); 547 } 548 549 dw_mci_idmac_reset(host); 550 551 if (host->dma_64bit_address == 1) { 552 /* Mask out interrupts - get Tx & Rx complete only */ 553 mci_writel(host, IDSTS64, IDMAC_INT_CLR); 554 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | 555 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 556 557 /* Set the descriptor base address */ 558 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); 559 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); 560 561 } else { 562 /* Mask out interrupts - get Tx & Rx complete only */ 563 mci_writel(host, IDSTS, IDMAC_INT_CLR); 564 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | 565 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); 566 567 /* Set the descriptor base address */ 568 mci_writel(host, DBADDR, host->sg_dma); 569 } 570 571 return 0; 572} 573 574static inline int dw_mci_prepare_desc64(struct dw_mci *host, 575 struct mmc_data *data, 576 unsigned int sg_len) 577{ 578 unsigned int desc_len; 579 struct idmac_desc_64addr *desc_first, *desc_last, *desc; 580 u32 val; 581 int i; 582 583 desc_first = desc_last = desc = host->sg_cpu; 584 585 for (i = 0; i < sg_len; i++) { 586 unsigned int length = sg_dma_len(&data->sg[i]); 587 588 u64 mem_addr = sg_dma_address(&data->sg[i]); 589 590 for ( ; length ; desc++) { 591 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 592 length : DW_MCI_DESC_DATA_LENGTH; 593 594 length -= desc_len; 595 596 /* 597 * Wait for the former clear OWN bit operation 598 * of IDMAC to make sure that this descriptor 599 * isn't still owned by IDMAC as IDMAC's write 600 * ops and CPU's read ops are asynchronous. 601 */ 602 if (readl_poll_timeout_atomic(&desc->des0, val, 603 !(val & IDMAC_DES0_OWN), 604 10, 100 * USEC_PER_MSEC)) 605 goto err_own_bit; 606 607 /* 608 * Set the OWN bit and disable interrupts 609 * for this descriptor 610 */ 611 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | 612 IDMAC_DES0_CH; 613 614 /* Buffer length */ 615 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len); 616 617 /* Physical address to DMA to/from */ 618 desc->des4 = mem_addr & 0xffffffff; 619 desc->des5 = mem_addr >> 32; 620 621 /* Update physical address for the next desc */ 622 mem_addr += desc_len; 623 624 /* Save pointer to the last descriptor */ 625 desc_last = desc; 626 } 627 } 628 629 /* Set first descriptor */ 630 desc_first->des0 |= IDMAC_DES0_FD; 631 632 /* Set last descriptor */ 633 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); 634 desc_last->des0 |= IDMAC_DES0_LD; 635 636 return 0; 637err_own_bit: 638 /* restore the descriptor chain as it's polluted */ 639 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 640 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 641 dw_mci_idmac_init(host); 642 return -EINVAL; 643} 644 645 646static inline int dw_mci_prepare_desc32(struct dw_mci *host, 647 struct mmc_data *data, 648 unsigned int sg_len) 649{ 650 unsigned int desc_len; 651 struct idmac_desc *desc_first, *desc_last, *desc; 652 u32 val; 653 int i; 654 655 desc_first = desc_last = desc = host->sg_cpu; 656 657 for (i = 0; i < sg_len; i++) { 658 unsigned int length = sg_dma_len(&data->sg[i]); 659 660 u32 mem_addr = sg_dma_address(&data->sg[i]); 661 662 for ( ; length ; desc++) { 663 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ? 664 length : DW_MCI_DESC_DATA_LENGTH; 665 666 length -= desc_len; 667 668 /* 669 * Wait for the former clear OWN bit operation 670 * of IDMAC to make sure that this descriptor 671 * isn't still owned by IDMAC as IDMAC's write 672 * ops and CPU's read ops are asynchronous. 673 */ 674 if (readl_poll_timeout_atomic(&desc->des0, val, 675 IDMAC_OWN_CLR64(val), 676 10, 677 100 * USEC_PER_MSEC)) 678 goto err_own_bit; 679 680 /* 681 * Set the OWN bit and disable interrupts 682 * for this descriptor 683 */ 684 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | 685 IDMAC_DES0_DIC | 686 IDMAC_DES0_CH); 687 688 /* Buffer length */ 689 IDMAC_SET_BUFFER1_SIZE(desc, desc_len); 690 691 /* Physical address to DMA to/from */ 692 desc->des2 = cpu_to_le32(mem_addr); 693 694 /* Update physical address for the next desc */ 695 mem_addr += desc_len; 696 697 /* Save pointer to the last descriptor */ 698 desc_last = desc; 699 } 700 } 701 702 /* Set first descriptor */ 703 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); 704 705 /* Set last descriptor */ 706 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | 707 IDMAC_DES0_DIC)); 708 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); 709 710 return 0; 711err_own_bit: 712 /* restore the descriptor chain as it's polluted */ 713 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); 714 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); 715 dw_mci_idmac_init(host); 716 return -EINVAL; 717} 718 719static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) 720{ 721 u32 temp; 722 int ret; 723 724 if (host->dma_64bit_address == 1) 725 ret = dw_mci_prepare_desc64(host, host->data, sg_len); 726 else 727 ret = dw_mci_prepare_desc32(host, host->data, sg_len); 728 729 if (ret) 730 goto out; 731 732 /* drain writebuffer */ 733 wmb(); 734 735 /* Make sure to reset DMA in case we did PIO before this */ 736 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); 737 dw_mci_idmac_reset(host); 738 739 /* Select IDMAC interface */ 740 temp = mci_readl(host, CTRL); 741 temp |= SDMMC_CTRL_USE_IDMAC; 742 mci_writel(host, CTRL, temp); 743 744 /* drain writebuffer */ 745 wmb(); 746 747 /* Enable the IDMAC */ 748 temp = mci_readl(host, BMOD); 749 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; 750 mci_writel(host, BMOD, temp); 751 752 /* Start it running */ 753 mci_writel(host, PLDMND, 1); 754 755out: 756 return ret; 757} 758 759static const struct dw_mci_dma_ops dw_mci_idmac_ops = { 760 .init = dw_mci_idmac_init, 761 .start = dw_mci_idmac_start_dma, 762 .stop = dw_mci_idmac_stop_dma, 763 .complete = dw_mci_dmac_complete_dma, 764 .cleanup = dw_mci_dma_cleanup, 765}; 766 767static void dw_mci_edmac_stop_dma(struct dw_mci *host) 768{ 769 dmaengine_terminate_async(host->dms->ch); 770} 771 772static int dw_mci_edmac_start_dma(struct dw_mci *host, 773 unsigned int sg_len) 774{ 775 struct dma_slave_config cfg; 776 struct dma_async_tx_descriptor *desc = NULL; 777 struct scatterlist *sgl = host->data->sg; 778 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 779 u32 sg_elems = host->data->sg_len; 780 u32 fifoth_val; 781 u32 fifo_offset = host->fifo_reg - host->regs; 782 int ret = 0; 783 784 /* Set external dma config: burst size, burst width */ 785 memset(&cfg, 0, sizeof(cfg)); 786 cfg.dst_addr = host->phy_regs + fifo_offset; 787 cfg.src_addr = cfg.dst_addr; 788 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 789 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 790 791 /* Match burst msize with external dma config */ 792 fifoth_val = mci_readl(host, FIFOTH); 793 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7]; 794 cfg.src_maxburst = cfg.dst_maxburst; 795 796 if (host->data->flags & MMC_DATA_WRITE) 797 cfg.direction = DMA_MEM_TO_DEV; 798 else 799 cfg.direction = DMA_DEV_TO_MEM; 800 801 ret = dmaengine_slave_config(host->dms->ch, &cfg); 802 if (ret) { 803 dev_err(host->dev, "Failed to config edmac.\n"); 804 return -EBUSY; 805 } 806 807 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, 808 sg_len, cfg.direction, 809 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 810 if (!desc) { 811 dev_err(host->dev, "Can't prepare slave sg.\n"); 812 return -EBUSY; 813 } 814 815 /* Set dw_mci_dmac_complete_dma as callback */ 816 desc->callback = dw_mci_dmac_complete_dma; 817 desc->callback_param = (void *)host; 818 dmaengine_submit(desc); 819 820 /* Flush cache before write */ 821 if (host->data->flags & MMC_DATA_WRITE) 822 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, 823 sg_elems, DMA_TO_DEVICE); 824 825 dma_async_issue_pending(host->dms->ch); 826 827 return 0; 828} 829 830static int dw_mci_edmac_init(struct dw_mci *host) 831{ 832 /* Request external dma channel */ 833 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); 834 if (!host->dms) 835 return -ENOMEM; 836 837 host->dms->ch = dma_request_chan(host->dev, "rx-tx"); 838 if (IS_ERR(host->dms->ch)) { 839 int ret = PTR_ERR(host->dms->ch); 840 841 dev_err(host->dev, "Failed to get external DMA channel.\n"); 842 kfree(host->dms); 843 host->dms = NULL; 844 return ret; 845 } 846 847 return 0; 848} 849 850static void dw_mci_edmac_exit(struct dw_mci *host) 851{ 852 if (host->dms) { 853 if (host->dms->ch) { 854 dma_release_channel(host->dms->ch); 855 host->dms->ch = NULL; 856 } 857 kfree(host->dms); 858 host->dms = NULL; 859 } 860} 861 862static const struct dw_mci_dma_ops dw_mci_edmac_ops = { 863 .init = dw_mci_edmac_init, 864 .exit = dw_mci_edmac_exit, 865 .start = dw_mci_edmac_start_dma, 866 .stop = dw_mci_edmac_stop_dma, 867 .complete = dw_mci_dmac_complete_dma, 868 .cleanup = dw_mci_dma_cleanup, 869}; 870 871static int dw_mci_pre_dma_transfer(struct dw_mci *host, 872 struct mmc_data *data, 873 int cookie) 874{ 875 struct scatterlist *sg; 876 unsigned int i, sg_len; 877 878 if (data->host_cookie == COOKIE_PRE_MAPPED) 879 return data->sg_len; 880 881 /* 882 * We don't do DMA on "complex" transfers, i.e. with 883 * non-word-aligned buffers or lengths. Also, we don't bother 884 * with all the DMA setup overhead for short transfers. 885 */ 886 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) 887 return -EINVAL; 888 889 if (data->blksz & 3) 890 return -EINVAL; 891 892 for_each_sg(data->sg, sg, data->sg_len, i) { 893 if (sg->offset & 3 || sg->length & 3) 894 return -EINVAL; 895 } 896 897 sg_len = dma_map_sg(host->dev, 898 data->sg, 899 data->sg_len, 900 mmc_get_dma_dir(data)); 901 if (sg_len == 0) 902 return -EINVAL; 903 904 data->host_cookie = cookie; 905 906 return sg_len; 907} 908 909static void dw_mci_pre_req(struct mmc_host *mmc, 910 struct mmc_request *mrq) 911{ 912 struct dw_mci_slot *slot = mmc_priv(mmc); 913 struct mmc_data *data = mrq->data; 914 915 if (!slot->host->use_dma || !data) 916 return; 917 918 /* This data might be unmapped at this time */ 919 data->host_cookie = COOKIE_UNMAPPED; 920 921 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 922 COOKIE_PRE_MAPPED) < 0) 923 data->host_cookie = COOKIE_UNMAPPED; 924} 925 926static void dw_mci_post_req(struct mmc_host *mmc, 927 struct mmc_request *mrq, 928 int err) 929{ 930 struct dw_mci_slot *slot = mmc_priv(mmc); 931 struct mmc_data *data = mrq->data; 932 933 if (!slot->host->use_dma || !data) 934 return; 935 936 if (data->host_cookie != COOKIE_UNMAPPED) 937 dma_unmap_sg(slot->host->dev, 938 data->sg, 939 data->sg_len, 940 mmc_get_dma_dir(data)); 941 data->host_cookie = COOKIE_UNMAPPED; 942} 943 944static int dw_mci_get_cd(struct mmc_host *mmc) 945{ 946 int present; 947 struct dw_mci_slot *slot = mmc_priv(mmc); 948 struct dw_mci *host = slot->host; 949 int gpio_cd = mmc_gpio_get_cd(mmc); 950 951 /* Use platform get_cd function, else try onboard card detect */ 952 if (((mmc->caps & MMC_CAP_NEEDS_POLL) 953 || !mmc_card_is_removable(mmc))) { 954 present = 1; 955 956 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { 957 if (mmc->caps & MMC_CAP_NEEDS_POLL) { 958 dev_info(&mmc->class_dev, 959 "card is polling.\n"); 960 } else { 961 dev_info(&mmc->class_dev, 962 "card is non-removable.\n"); 963 } 964 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); 965 } 966 967 return present; 968 } else if (gpio_cd >= 0) 969 present = gpio_cd; 970 else 971 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) 972 == 0 ? 1 : 0; 973 974 spin_lock_bh(&host->lock); 975 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 976 dev_dbg(&mmc->class_dev, "card is present\n"); 977 else if (!present && 978 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) 979 dev_dbg(&mmc->class_dev, "card is not present\n"); 980 spin_unlock_bh(&host->lock); 981 982 return present; 983} 984 985static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) 986{ 987 unsigned int blksz = data->blksz; 988 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; 989 u32 fifo_width = 1 << host->data_shift; 990 u32 blksz_depth = blksz / fifo_width, fifoth_val; 991 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; 992 int idx = ARRAY_SIZE(mszs) - 1; 993 994 /* pio should ship this scenario */ 995 if (!host->use_dma) 996 return; 997 998 tx_wmark = (host->fifo_depth) / 2; 999 tx_wmark_invers = host->fifo_depth - tx_wmark; 1000 1001 /* 1002 * MSIZE is '1', 1003 * if blksz is not a multiple of the FIFO width 1004 */ 1005 if (blksz % fifo_width) 1006 goto done; 1007 1008 do { 1009 if (!((blksz_depth % mszs[idx]) || 1010 (tx_wmark_invers % mszs[idx]))) { 1011 msize = idx; 1012 rx_wmark = mszs[idx] - 1; 1013 break; 1014 } 1015 } while (--idx > 0); 1016 /* 1017 * If idx is '0', it won't be tried 1018 * Thus, initial values are uesed 1019 */ 1020done: 1021 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); 1022 mci_writel(host, FIFOTH, fifoth_val); 1023} 1024 1025static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data) 1026{ 1027 unsigned int blksz = data->blksz; 1028 u32 blksz_depth, fifo_depth; 1029 u16 thld_size; 1030 u8 enable; 1031 1032 /* 1033 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is 1034 * in the FIFO region, so we really shouldn't access it). 1035 */ 1036 if (host->verid < DW_MMC_240A || 1037 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) 1038 return; 1039 1040 /* 1041 * Card write Threshold is introduced since 2.80a 1042 * It's used when HS400 mode is enabled. 1043 */ 1044 if (data->flags & MMC_DATA_WRITE && 1045 host->timing != MMC_TIMING_MMC_HS400) 1046 goto disable; 1047 1048 if (data->flags & MMC_DATA_WRITE) 1049 enable = SDMMC_CARD_WR_THR_EN; 1050 else 1051 enable = SDMMC_CARD_RD_THR_EN; 1052 1053 if (host->timing != MMC_TIMING_MMC_HS200 && 1054 host->timing != MMC_TIMING_UHS_SDR104 && 1055 host->timing != MMC_TIMING_MMC_HS400) 1056 goto disable; 1057 1058 blksz_depth = blksz / (1 << host->data_shift); 1059 fifo_depth = host->fifo_depth; 1060 1061 if (blksz_depth > fifo_depth) 1062 goto disable; 1063 1064 /* 1065 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' 1066 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz 1067 * Currently just choose blksz. 1068 */ 1069 thld_size = blksz; 1070 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable)); 1071 return; 1072 1073disable: 1074 mci_writel(host, CDTHRCTL, 0); 1075} 1076 1077static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) 1078{ 1079 unsigned long irqflags; 1080 int sg_len; 1081 u32 temp; 1082 1083 host->using_dma = 0; 1084 1085 /* If we don't have a channel, we can't do DMA */ 1086 if (!host->use_dma) 1087 return -ENODEV; 1088 1089 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1090 if (sg_len < 0) { 1091 host->dma_ops->stop(host); 1092 return sg_len; 1093 } 1094 1095 host->using_dma = 1; 1096 1097 if (host->use_dma == TRANS_MODE_IDMAC) 1098 dev_vdbg(host->dev, 1099 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", 1100 (unsigned long)host->sg_cpu, 1101 (unsigned long)host->sg_dma, 1102 sg_len); 1103 1104 /* 1105 * Decide the MSIZE and RX/TX Watermark. 1106 * If current block size is same with previous size, 1107 * no need to update fifoth. 1108 */ 1109 if (host->prev_blksz != data->blksz) 1110 dw_mci_adjust_fifoth(host, data); 1111 1112 /* Enable the DMA interface */ 1113 temp = mci_readl(host, CTRL); 1114 temp |= SDMMC_CTRL_DMA_ENABLE; 1115 mci_writel(host, CTRL, temp); 1116 1117 /* Disable RX/TX IRQs, let DMA handle it */ 1118 spin_lock_irqsave(&host->irq_lock, irqflags); 1119 temp = mci_readl(host, INTMASK); 1120 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); 1121 mci_writel(host, INTMASK, temp); 1122 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1123 1124 if (host->dma_ops->start(host, sg_len)) { 1125 host->dma_ops->stop(host); 1126 /* We can't do DMA, try PIO for this one */ 1127 dev_dbg(host->dev, 1128 "%s: fall back to PIO mode for current transfer\n", 1129 __func__); 1130 return -ENODEV; 1131 } 1132 1133 return 0; 1134} 1135 1136static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) 1137{ 1138 unsigned long irqflags; 1139 int flags = SG_MITER_ATOMIC; 1140 u32 temp; 1141 1142 data->error = -EINPROGRESS; 1143 1144 WARN_ON(host->data); 1145 host->sg = NULL; 1146 host->data = data; 1147 1148 if (data->flags & MMC_DATA_READ) 1149 host->dir_status = DW_MCI_RECV_STATUS; 1150 else 1151 host->dir_status = DW_MCI_SEND_STATUS; 1152 1153 dw_mci_ctrl_thld(host, data); 1154 1155 if (dw_mci_submit_data_dma(host, data)) { 1156 if (host->data->flags & MMC_DATA_READ) 1157 flags |= SG_MITER_TO_SG; 1158 else 1159 flags |= SG_MITER_FROM_SG; 1160 1161 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1162 host->sg = data->sg; 1163 host->part_buf_start = 0; 1164 host->part_buf_count = 0; 1165 1166 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); 1167 1168 spin_lock_irqsave(&host->irq_lock, irqflags); 1169 temp = mci_readl(host, INTMASK); 1170 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; 1171 mci_writel(host, INTMASK, temp); 1172 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1173 1174 temp = mci_readl(host, CTRL); 1175 temp &= ~SDMMC_CTRL_DMA_ENABLE; 1176 mci_writel(host, CTRL, temp); 1177 1178 /* 1179 * Use the initial fifoth_val for PIO mode. If wm_algined 1180 * is set, we set watermark same as data size. 1181 * If next issued data may be transfered by DMA mode, 1182 * prev_blksz should be invalidated. 1183 */ 1184 if (host->wm_aligned) 1185 dw_mci_adjust_fifoth(host, data); 1186 else 1187 mci_writel(host, FIFOTH, host->fifoth_val); 1188 host->prev_blksz = 0; 1189 } else { 1190 /* 1191 * Keep the current block size. 1192 * It will be used to decide whether to update 1193 * fifoth register next time. 1194 */ 1195 host->prev_blksz = data->blksz; 1196 } 1197} 1198 1199static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) 1200{ 1201 struct dw_mci *host = slot->host; 1202 unsigned int clock = slot->clock; 1203 u32 div; 1204 u32 clk_en_a; 1205 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; 1206 1207 /* We must continue to set bit 28 in CMD until the change is complete */ 1208 if (host->state == STATE_WAITING_CMD11_DONE) 1209 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; 1210 1211 slot->mmc->actual_clock = 0; 1212 1213 if (!clock) { 1214 mci_writel(host, CLKENA, 0); 1215 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1216 } else if (clock != host->current_speed || force_clkinit) { 1217 div = host->bus_hz / clock; 1218 if (host->bus_hz % clock && host->bus_hz > clock) 1219 /* 1220 * move the + 1 after the divide to prevent 1221 * over-clocking the card. 1222 */ 1223 div += 1; 1224 1225 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; 1226 1227 if ((clock != slot->__clk_old && 1228 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || 1229 force_clkinit) { 1230 /* Silent the verbose log if calling from PM context */ 1231 if (!force_clkinit) 1232 dev_info(&slot->mmc->class_dev, 1233 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", 1234 slot->id, host->bus_hz, clock, 1235 div ? ((host->bus_hz / div) >> 1) : 1236 host->bus_hz, div); 1237 1238 /* 1239 * If card is polling, display the message only 1240 * one time at boot time. 1241 */ 1242 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && 1243 slot->mmc->f_min == clock) 1244 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); 1245 } 1246 1247 /* disable clock */ 1248 mci_writel(host, CLKENA, 0); 1249 mci_writel(host, CLKSRC, 0); 1250 1251 /* inform CIU */ 1252 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1253 1254 /* set clock to desired speed */ 1255 mci_writel(host, CLKDIV, div); 1256 1257 /* inform CIU */ 1258 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1259 1260 /* enable clock; only low power if no SDIO */ 1261 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; 1262 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) 1263 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; 1264 mci_writel(host, CLKENA, clk_en_a); 1265 1266 /* inform CIU */ 1267 mci_send_cmd(slot, sdmmc_cmd_bits, 0); 1268 1269 /* keep the last clock value that was requested from core */ 1270 slot->__clk_old = clock; 1271 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : 1272 host->bus_hz; 1273 } 1274 1275 host->current_speed = clock; 1276 1277 /* Set the current slot bus width */ 1278 mci_writel(host, CTYPE, (slot->ctype << slot->id)); 1279} 1280 1281static void __dw_mci_start_request(struct dw_mci *host, 1282 struct dw_mci_slot *slot, 1283 struct mmc_command *cmd) 1284{ 1285 struct mmc_request *mrq; 1286 struct mmc_data *data; 1287 u32 cmdflags; 1288 1289 mrq = slot->mrq; 1290 1291 host->mrq = mrq; 1292 1293 host->pending_events = 0; 1294 host->completed_events = 0; 1295 host->cmd_status = 0; 1296 host->data_status = 0; 1297 host->dir_status = 0; 1298 1299 data = cmd->data; 1300 if (data) { 1301 mci_writel(host, TMOUT, 0xFFFFFFFF); 1302 mci_writel(host, BYTCNT, data->blksz*data->blocks); 1303 mci_writel(host, BLKSIZ, data->blksz); 1304 } 1305 1306 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); 1307 1308 /* this is the first command, send the initialization clock */ 1309 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) 1310 cmdflags |= SDMMC_CMD_INIT; 1311 1312 if (data) { 1313 dw_mci_submit_data(host, data); 1314 wmb(); /* drain writebuffer */ 1315 } 1316 1317 dw_mci_start_command(host, cmd, cmdflags); 1318 1319 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 1320 unsigned long irqflags; 1321 1322 /* 1323 * Databook says to fail after 2ms w/ no response, but evidence 1324 * shows that sometimes the cmd11 interrupt takes over 130ms. 1325 * We'll set to 500ms, plus an extra jiffy just in case jiffies 1326 * is just about to roll over. 1327 * 1328 * We do this whole thing under spinlock and only if the 1329 * command hasn't already completed (indicating the the irq 1330 * already ran so we don't want the timeout). 1331 */ 1332 spin_lock_irqsave(&host->irq_lock, irqflags); 1333 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1334 mod_timer(&host->cmd11_timer, 1335 jiffies + msecs_to_jiffies(500) + 1); 1336 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1337 } 1338 1339 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); 1340} 1341 1342static void dw_mci_start_request(struct dw_mci *host, 1343 struct dw_mci_slot *slot) 1344{ 1345 struct mmc_request *mrq = slot->mrq; 1346 struct mmc_command *cmd; 1347 1348 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; 1349 __dw_mci_start_request(host, slot, cmd); 1350} 1351 1352/* must be called with host->lock held */ 1353static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, 1354 struct mmc_request *mrq) 1355{ 1356 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1357 host->state); 1358 1359 slot->mrq = mrq; 1360 1361 if (host->state == STATE_WAITING_CMD11_DONE) { 1362 dev_warn(&slot->mmc->class_dev, 1363 "Voltage change didn't complete\n"); 1364 /* 1365 * this case isn't expected to happen, so we can 1366 * either crash here or just try to continue on 1367 * in the closest possible state 1368 */ 1369 host->state = STATE_IDLE; 1370 } 1371 1372 if (host->state == STATE_IDLE) { 1373 host->state = STATE_SENDING_CMD; 1374 dw_mci_start_request(host, slot); 1375 } else { 1376 list_add_tail(&slot->queue_node, &host->queue); 1377 } 1378} 1379 1380static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1381{ 1382 struct dw_mci_slot *slot = mmc_priv(mmc); 1383 struct dw_mci *host = slot->host; 1384 1385 WARN_ON(slot->mrq); 1386 1387 /* 1388 * The check for card presence and queueing of the request must be 1389 * atomic, otherwise the card could be removed in between and the 1390 * request wouldn't fail until another card was inserted. 1391 */ 1392 1393 if (!dw_mci_get_cd(mmc)) { 1394 mrq->cmd->error = -ENOMEDIUM; 1395 mmc_request_done(mmc, mrq); 1396 return; 1397 } 1398 1399 spin_lock_bh(&host->lock); 1400 1401 dw_mci_queue_request(host, slot, mrq); 1402 1403 spin_unlock_bh(&host->lock); 1404} 1405 1406static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1407{ 1408 struct dw_mci_slot *slot = mmc_priv(mmc); 1409 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; 1410 u32 regs; 1411 int ret; 1412 1413 switch (ios->bus_width) { 1414 case MMC_BUS_WIDTH_4: 1415 slot->ctype = SDMMC_CTYPE_4BIT; 1416 break; 1417 case MMC_BUS_WIDTH_8: 1418 slot->ctype = SDMMC_CTYPE_8BIT; 1419 break; 1420 default: 1421 /* set default 1 bit mode */ 1422 slot->ctype = SDMMC_CTYPE_1BIT; 1423 } 1424 1425 regs = mci_readl(slot->host, UHS_REG); 1426 1427 /* DDR mode set */ 1428 if (ios->timing == MMC_TIMING_MMC_DDR52 || 1429 ios->timing == MMC_TIMING_UHS_DDR50 || 1430 ios->timing == MMC_TIMING_MMC_HS400) 1431 regs |= ((0x1 << slot->id) << 16); 1432 else 1433 regs &= ~((0x1 << slot->id) << 16); 1434 1435 mci_writel(slot->host, UHS_REG, regs); 1436 slot->host->timing = ios->timing; 1437 1438 /* 1439 * Use mirror of ios->clock to prevent race with mmc 1440 * core ios update when finding the minimum. 1441 */ 1442 slot->clock = ios->clock; 1443 1444 if (drv_data && drv_data->set_ios) 1445 drv_data->set_ios(slot->host, ios); 1446 1447 switch (ios->power_mode) { 1448 case MMC_POWER_UP: 1449 if (!IS_ERR(mmc->supply.vmmc)) { 1450 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1451 ios->vdd); 1452 if (ret) { 1453 dev_err(slot->host->dev, 1454 "failed to enable vmmc regulator\n"); 1455 /*return, if failed turn on vmmc*/ 1456 return; 1457 } 1458 } 1459 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); 1460 regs = mci_readl(slot->host, PWREN); 1461 regs |= (1 << slot->id); 1462 mci_writel(slot->host, PWREN, regs); 1463 break; 1464 case MMC_POWER_ON: 1465 if (!slot->host->vqmmc_enabled) { 1466 if (!IS_ERR(mmc->supply.vqmmc)) { 1467 ret = regulator_enable(mmc->supply.vqmmc); 1468 if (ret < 0) 1469 dev_err(slot->host->dev, 1470 "failed to enable vqmmc\n"); 1471 else 1472 slot->host->vqmmc_enabled = true; 1473 1474 } else { 1475 /* Keep track so we don't reset again */ 1476 slot->host->vqmmc_enabled = true; 1477 } 1478 1479 /* Reset our state machine after powering on */ 1480 dw_mci_ctrl_reset(slot->host, 1481 SDMMC_CTRL_ALL_RESET_FLAGS); 1482 } 1483 1484 /* Adjust clock / bus width after power is up */ 1485 dw_mci_setup_bus(slot, false); 1486 1487 break; 1488 case MMC_POWER_OFF: 1489 /* Turn clock off before power goes down */ 1490 dw_mci_setup_bus(slot, false); 1491 1492 if (!IS_ERR(mmc->supply.vmmc)) 1493 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1494 1495 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) 1496 regulator_disable(mmc->supply.vqmmc); 1497 slot->host->vqmmc_enabled = false; 1498 1499 regs = mci_readl(slot->host, PWREN); 1500 regs &= ~(1 << slot->id); 1501 mci_writel(slot->host, PWREN, regs); 1502 break; 1503 default: 1504 break; 1505 } 1506 1507 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) 1508 slot->host->state = STATE_IDLE; 1509} 1510 1511static int dw_mci_card_busy(struct mmc_host *mmc) 1512{ 1513 struct dw_mci_slot *slot = mmc_priv(mmc); 1514 u32 status; 1515 1516 /* 1517 * Check the busy bit which is low when DAT[3:0] 1518 * (the data lines) are 0000 1519 */ 1520 status = mci_readl(slot->host, STATUS); 1521 1522 return !!(status & SDMMC_STATUS_BUSY); 1523} 1524 1525static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1526{ 1527 struct dw_mci_slot *slot = mmc_priv(mmc); 1528 struct dw_mci *host = slot->host; 1529 const struct dw_mci_drv_data *drv_data = host->drv_data; 1530 u32 uhs; 1531 u32 v18 = SDMMC_UHS_18V << slot->id; 1532 int ret; 1533 1534 if (drv_data && drv_data->switch_voltage) 1535 return drv_data->switch_voltage(mmc, ios); 1536 1537 /* 1538 * Program the voltage. Note that some instances of dw_mmc may use 1539 * the UHS_REG for this. For other instances (like exynos) the UHS_REG 1540 * does no harm but you need to set the regulator directly. Try both. 1541 */ 1542 uhs = mci_readl(host, UHS_REG); 1543 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1544 uhs &= ~v18; 1545 else 1546 uhs |= v18; 1547 1548 if (!IS_ERR(mmc->supply.vqmmc)) { 1549 ret = mmc_regulator_set_vqmmc(mmc, ios); 1550 if (ret < 0) { 1551 dev_dbg(&mmc->class_dev, 1552 "Regulator set error %d - %s V\n", 1553 ret, uhs & v18 ? "1.8" : "3.3"); 1554 return ret; 1555 } 1556 } 1557 mci_writel(host, UHS_REG, uhs); 1558 1559 return 0; 1560} 1561 1562static int dw_mci_get_ro(struct mmc_host *mmc) 1563{ 1564 int read_only; 1565 struct dw_mci_slot *slot = mmc_priv(mmc); 1566 int gpio_ro = mmc_gpio_get_ro(mmc); 1567 1568 /* Use platform get_ro function, else try on board write protect */ 1569 if (gpio_ro >= 0) 1570 read_only = gpio_ro; 1571 else 1572 read_only = 1573 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; 1574 1575 dev_dbg(&mmc->class_dev, "card is %s\n", 1576 read_only ? "read-only" : "read-write"); 1577 1578 return read_only; 1579} 1580 1581static void dw_mci_hw_reset(struct mmc_host *mmc) 1582{ 1583 struct dw_mci_slot *slot = mmc_priv(mmc); 1584 struct dw_mci *host = slot->host; 1585 int reset; 1586 1587 if (host->use_dma == TRANS_MODE_IDMAC) 1588 dw_mci_idmac_reset(host); 1589 1590 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | 1591 SDMMC_CTRL_FIFO_RESET)) 1592 return; 1593 1594 /* 1595 * According to eMMC spec, card reset procedure: 1596 * tRstW >= 1us: RST_n pulse width 1597 * tRSCA >= 200us: RST_n to Command time 1598 * tRSTH >= 1us: RST_n high period 1599 */ 1600 reset = mci_readl(host, RST_N); 1601 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); 1602 mci_writel(host, RST_N, reset); 1603 usleep_range(1, 2); 1604 reset |= SDMMC_RST_HWACTIVE << slot->id; 1605 mci_writel(host, RST_N, reset); 1606 usleep_range(200, 300); 1607} 1608 1609static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) 1610{ 1611 struct dw_mci_slot *slot = mmc_priv(mmc); 1612 struct dw_mci *host = slot->host; 1613 1614 /* 1615 * Low power mode will stop the card clock when idle. According to the 1616 * description of the CLKENA register we should disable low power mode 1617 * for SDIO cards if we need SDIO interrupts to work. 1618 */ 1619 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1620 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; 1621 u32 clk_en_a_old; 1622 u32 clk_en_a; 1623 1624 clk_en_a_old = mci_readl(host, CLKENA); 1625 1626 if (card->type == MMC_TYPE_SDIO || 1627 card->type == MMC_TYPE_SD_COMBO) { 1628 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1629 clk_en_a = clk_en_a_old & ~clken_low_pwr; 1630 } else { 1631 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); 1632 clk_en_a = clk_en_a_old | clken_low_pwr; 1633 } 1634 1635 if (clk_en_a != clk_en_a_old) { 1636 mci_writel(host, CLKENA, clk_en_a); 1637 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | 1638 SDMMC_CMD_PRV_DAT_WAIT, 0); 1639 } 1640 } 1641} 1642 1643static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb) 1644{ 1645 struct dw_mci *host = slot->host; 1646 unsigned long irqflags; 1647 u32 int_mask; 1648 1649 spin_lock_irqsave(&host->irq_lock, irqflags); 1650 1651 /* Enable/disable Slot Specific SDIO interrupt */ 1652 int_mask = mci_readl(host, INTMASK); 1653 if (enb) 1654 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); 1655 else 1656 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); 1657 mci_writel(host, INTMASK, int_mask); 1658 1659 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1660} 1661 1662static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) 1663{ 1664 struct dw_mci_slot *slot = mmc_priv(mmc); 1665 struct dw_mci *host = slot->host; 1666 1667 __dw_mci_enable_sdio_irq(slot, enb); 1668 1669 /* Avoid runtime suspending the device when SDIO IRQ is enabled */ 1670 if (enb) 1671 pm_runtime_get_noresume(host->dev); 1672 else 1673 pm_runtime_put_noidle(host->dev); 1674} 1675 1676static void dw_mci_ack_sdio_irq(struct mmc_host *mmc) 1677{ 1678 struct dw_mci_slot *slot = mmc_priv(mmc); 1679 1680 __dw_mci_enable_sdio_irq(slot, 1); 1681} 1682 1683static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1684{ 1685 struct dw_mci_slot *slot = mmc_priv(mmc); 1686 struct dw_mci *host = slot->host; 1687 const struct dw_mci_drv_data *drv_data = host->drv_data; 1688 int err = -EINVAL; 1689 1690 if (drv_data && drv_data->execute_tuning) 1691 err = drv_data->execute_tuning(slot, opcode); 1692 return err; 1693} 1694 1695static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, 1696 struct mmc_ios *ios) 1697{ 1698 struct dw_mci_slot *slot = mmc_priv(mmc); 1699 struct dw_mci *host = slot->host; 1700 const struct dw_mci_drv_data *drv_data = host->drv_data; 1701 1702 if (drv_data && drv_data->prepare_hs400_tuning) 1703 return drv_data->prepare_hs400_tuning(host, ios); 1704 1705 return 0; 1706} 1707 1708static bool dw_mci_reset(struct dw_mci *host) 1709{ 1710 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; 1711 bool ret = false; 1712 u32 status = 0; 1713 1714 /* 1715 * Resetting generates a block interrupt, hence setting 1716 * the scatter-gather pointer to NULL. 1717 */ 1718 if (host->sg) { 1719 sg_miter_stop(&host->sg_miter); 1720 host->sg = NULL; 1721 } 1722 1723 if (host->use_dma) 1724 flags |= SDMMC_CTRL_DMA_RESET; 1725 1726 if (dw_mci_ctrl_reset(host, flags)) { 1727 /* 1728 * In all cases we clear the RAWINTS 1729 * register to clear any interrupts. 1730 */ 1731 mci_writel(host, RINTSTS, 0xFFFFFFFF); 1732 1733 if (!host->use_dma) { 1734 ret = true; 1735 goto ciu_out; 1736 } 1737 1738 /* Wait for dma_req to be cleared */ 1739 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, 1740 status, 1741 !(status & SDMMC_STATUS_DMA_REQ), 1742 1, 500 * USEC_PER_MSEC)) { 1743 dev_err(host->dev, 1744 "%s: Timeout waiting for dma_req to be cleared\n", 1745 __func__); 1746 goto ciu_out; 1747 } 1748 1749 /* when using DMA next we reset the fifo again */ 1750 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) 1751 goto ciu_out; 1752 } else { 1753 /* if the controller reset bit did clear, then set clock regs */ 1754 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { 1755 dev_err(host->dev, 1756 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", 1757 __func__); 1758 goto ciu_out; 1759 } 1760 } 1761 1762 if (host->use_dma == TRANS_MODE_IDMAC) 1763 /* It is also required that we reinit idmac */ 1764 dw_mci_idmac_init(host); 1765 1766 ret = true; 1767 1768ciu_out: 1769 /* After a CTRL reset we need to have CIU set clock registers */ 1770 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); 1771 1772 return ret; 1773} 1774 1775static const struct mmc_host_ops dw_mci_ops = { 1776 .request = dw_mci_request, 1777 .pre_req = dw_mci_pre_req, 1778 .post_req = dw_mci_post_req, 1779 .set_ios = dw_mci_set_ios, 1780 .get_ro = dw_mci_get_ro, 1781 .get_cd = dw_mci_get_cd, 1782 .hw_reset = dw_mci_hw_reset, 1783 .enable_sdio_irq = dw_mci_enable_sdio_irq, 1784 .ack_sdio_irq = dw_mci_ack_sdio_irq, 1785 .execute_tuning = dw_mci_execute_tuning, 1786 .card_busy = dw_mci_card_busy, 1787 .start_signal_voltage_switch = dw_mci_switch_voltage, 1788 .init_card = dw_mci_init_card, 1789 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, 1790}; 1791 1792static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) 1793 __releases(&host->lock) 1794 __acquires(&host->lock) 1795{ 1796 struct dw_mci_slot *slot; 1797 struct mmc_host *prev_mmc = host->slot->mmc; 1798 1799 WARN_ON(host->cmd || host->data); 1800 1801 host->slot->mrq = NULL; 1802 host->mrq = NULL; 1803 if (!list_empty(&host->queue)) { 1804 slot = list_entry(host->queue.next, 1805 struct dw_mci_slot, queue_node); 1806 list_del(&slot->queue_node); 1807 dev_vdbg(host->dev, "list not empty: %s is next\n", 1808 mmc_hostname(slot->mmc)); 1809 host->state = STATE_SENDING_CMD; 1810 dw_mci_start_request(host, slot); 1811 } else { 1812 dev_vdbg(host->dev, "list empty\n"); 1813 1814 if (host->state == STATE_SENDING_CMD11) 1815 host->state = STATE_WAITING_CMD11_DONE; 1816 else 1817 host->state = STATE_IDLE; 1818 } 1819 1820 spin_unlock(&host->lock); 1821 mmc_request_done(prev_mmc, mrq); 1822 spin_lock(&host->lock); 1823} 1824 1825static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) 1826{ 1827 u32 status = host->cmd_status; 1828 1829 host->cmd_status = 0; 1830 1831 /* Read the response from the card (up to 16 bytes) */ 1832 if (cmd->flags & MMC_RSP_PRESENT) { 1833 if (cmd->flags & MMC_RSP_136) { 1834 cmd->resp[3] = mci_readl(host, RESP0); 1835 cmd->resp[2] = mci_readl(host, RESP1); 1836 cmd->resp[1] = mci_readl(host, RESP2); 1837 cmd->resp[0] = mci_readl(host, RESP3); 1838 } else { 1839 cmd->resp[0] = mci_readl(host, RESP0); 1840 cmd->resp[1] = 0; 1841 cmd->resp[2] = 0; 1842 cmd->resp[3] = 0; 1843 } 1844 } 1845 1846 if (status & SDMMC_INT_RTO) 1847 cmd->error = -ETIMEDOUT; 1848 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) 1849 cmd->error = -EILSEQ; 1850 else if (status & SDMMC_INT_RESP_ERR) 1851 cmd->error = -EIO; 1852 else 1853 cmd->error = 0; 1854 1855 return cmd->error; 1856} 1857 1858static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) 1859{ 1860 u32 status = host->data_status; 1861 1862 if (status & DW_MCI_DATA_ERROR_FLAGS) { 1863 if (status & SDMMC_INT_DRTO) { 1864 data->error = -ETIMEDOUT; 1865 } else if (status & SDMMC_INT_DCRC) { 1866 data->error = -EILSEQ; 1867 } else if (status & SDMMC_INT_EBE) { 1868 if (host->dir_status == 1869 DW_MCI_SEND_STATUS) { 1870 /* 1871 * No data CRC status was returned. 1872 * The number of bytes transferred 1873 * will be exaggerated in PIO mode. 1874 */ 1875 data->bytes_xfered = 0; 1876 data->error = -ETIMEDOUT; 1877 } else if (host->dir_status == 1878 DW_MCI_RECV_STATUS) { 1879 data->error = -EILSEQ; 1880 } 1881 } else { 1882 /* SDMMC_INT_SBE is included */ 1883 data->error = -EILSEQ; 1884 } 1885 1886 dev_dbg(host->dev, "data error, status 0x%08x\n", status); 1887 1888 /* 1889 * After an error, there may be data lingering 1890 * in the FIFO 1891 */ 1892 dw_mci_reset(host); 1893 } else { 1894 data->bytes_xfered = data->blocks * data->blksz; 1895 data->error = 0; 1896 } 1897 1898 return data->error; 1899} 1900 1901static void dw_mci_set_drto(struct dw_mci *host) 1902{ 1903 unsigned int drto_clks; 1904 unsigned int drto_div; 1905 unsigned int drto_ms; 1906 unsigned long irqflags; 1907 1908 drto_clks = mci_readl(host, TMOUT) >> 8; 1909 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; 1910 if (drto_div == 0) 1911 drto_div = 1; 1912 1913 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 1914 host->bus_hz); 1915 1916 /* add a bit spare time */ 1917 drto_ms += 10; 1918 1919 spin_lock_irqsave(&host->irq_lock, irqflags); 1920 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1921 mod_timer(&host->dto_timer, 1922 jiffies + msecs_to_jiffies(drto_ms)); 1923 spin_unlock_irqrestore(&host->irq_lock, irqflags); 1924} 1925 1926static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host) 1927{ 1928 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) 1929 return false; 1930 1931 /* 1932 * Really be certain that the timer has stopped. This is a bit of 1933 * paranoia and could only really happen if we had really bad 1934 * interrupt latency and the interrupt routine and timeout were 1935 * running concurrently so that the del_timer() in the interrupt 1936 * handler couldn't run. 1937 */ 1938 WARN_ON(del_timer_sync(&host->cto_timer)); 1939 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); 1940 1941 return true; 1942} 1943 1944static bool dw_mci_clear_pending_data_complete(struct dw_mci *host) 1945{ 1946 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) 1947 return false; 1948 1949 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */ 1950 WARN_ON(del_timer_sync(&host->dto_timer)); 1951 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); 1952 1953 return true; 1954} 1955 1956static void dw_mci_tasklet_func(unsigned long priv) 1957{ 1958 struct dw_mci *host = (struct dw_mci *)priv; 1959 struct mmc_data *data; 1960 struct mmc_command *cmd; 1961 struct mmc_request *mrq; 1962 enum dw_mci_state state; 1963 enum dw_mci_state prev_state; 1964 unsigned int err; 1965 1966 spin_lock(&host->lock); 1967 1968 state = host->state; 1969 data = host->data; 1970 mrq = host->mrq; 1971 1972 do { 1973 prev_state = state; 1974 1975 switch (state) { 1976 case STATE_IDLE: 1977 case STATE_WAITING_CMD11_DONE: 1978 break; 1979 1980 case STATE_SENDING_CMD11: 1981 case STATE_SENDING_CMD: 1982 if (!dw_mci_clear_pending_cmd_complete(host)) 1983 break; 1984 1985 cmd = host->cmd; 1986 host->cmd = NULL; 1987 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); 1988 err = dw_mci_command_complete(host, cmd); 1989 if (cmd == mrq->sbc && !err) { 1990 __dw_mci_start_request(host, host->slot, 1991 mrq->cmd); 1992 goto unlock; 1993 } 1994 1995 if (cmd->data && err) { 1996 /* 1997 * During UHS tuning sequence, sending the stop 1998 * command after the response CRC error would 1999 * throw the system into a confused state 2000 * causing all future tuning phases to report 2001 * failure. 2002 * 2003 * In such case controller will move into a data 2004 * transfer state after a response error or 2005 * response CRC error. Let's let that finish 2006 * before trying to send a stop, so we'll go to 2007 * STATE_SENDING_DATA. 2008 * 2009 * Although letting the data transfer take place 2010 * will waste a bit of time (we already know 2011 * the command was bad), it can't cause any 2012 * errors since it's possible it would have 2013 * taken place anyway if this tasklet got 2014 * delayed. Allowing the transfer to take place 2015 * avoids races and keeps things simple. 2016 */ 2017 if (err != -ETIMEDOUT && 2018 host->dir_status == DW_MCI_RECV_STATUS) { 2019 state = STATE_SENDING_DATA; 2020 continue; 2021 } 2022 2023 send_stop_abort(host, data); 2024 dw_mci_stop_dma(host); 2025 state = STATE_SENDING_STOP; 2026 break; 2027 } 2028 2029 if (!cmd->data || err) { 2030 dw_mci_request_end(host, mrq); 2031 goto unlock; 2032 } 2033 2034 prev_state = state = STATE_SENDING_DATA; 2035 fallthrough; 2036 2037 case STATE_SENDING_DATA: 2038 /* 2039 * We could get a data error and never a transfer 2040 * complete so we'd better check for it here. 2041 * 2042 * Note that we don't really care if we also got a 2043 * transfer complete; stopping the DMA and sending an 2044 * abort won't hurt. 2045 */ 2046 if (test_and_clear_bit(EVENT_DATA_ERROR, 2047 &host->pending_events)) { 2048 if (!(host->data_status & (SDMMC_INT_DRTO | 2049 SDMMC_INT_EBE))) 2050 send_stop_abort(host, data); 2051 dw_mci_stop_dma(host); 2052 state = STATE_DATA_ERROR; 2053 break; 2054 } 2055 2056 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2057 &host->pending_events)) { 2058 /* 2059 * If all data-related interrupts don't come 2060 * within the given time in reading data state. 2061 */ 2062 if (host->dir_status == DW_MCI_RECV_STATUS) 2063 dw_mci_set_drto(host); 2064 break; 2065 } 2066 2067 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); 2068 2069 /* 2070 * Handle an EVENT_DATA_ERROR that might have shown up 2071 * before the transfer completed. This might not have 2072 * been caught by the check above because the interrupt 2073 * could have gone off between the previous check and 2074 * the check for transfer complete. 2075 * 2076 * Technically this ought not be needed assuming we 2077 * get a DATA_COMPLETE eventually (we'll notice the 2078 * error and end the request), but it shouldn't hurt. 2079 * 2080 * This has the advantage of sending the stop command. 2081 */ 2082 if (test_and_clear_bit(EVENT_DATA_ERROR, 2083 &host->pending_events)) { 2084 if (!(host->data_status & (SDMMC_INT_DRTO | 2085 SDMMC_INT_EBE))) 2086 send_stop_abort(host, data); 2087 dw_mci_stop_dma(host); 2088 state = STATE_DATA_ERROR; 2089 break; 2090 } 2091 prev_state = state = STATE_DATA_BUSY; 2092 2093 fallthrough; 2094 2095 case STATE_DATA_BUSY: 2096 if (!dw_mci_clear_pending_data_complete(host)) { 2097 /* 2098 * If data error interrupt comes but data over 2099 * interrupt doesn't come within the given time. 2100 * in reading data state. 2101 */ 2102 if (host->dir_status == DW_MCI_RECV_STATUS) 2103 dw_mci_set_drto(host); 2104 break; 2105 } 2106 2107 host->data = NULL; 2108 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); 2109 err = dw_mci_data_complete(host, data); 2110 2111 if (!err) { 2112 if (!data->stop || mrq->sbc) { 2113 if (mrq->sbc && data->stop) 2114 data->stop->error = 0; 2115 dw_mci_request_end(host, mrq); 2116 goto unlock; 2117 } 2118 2119 /* stop command for open-ended transfer*/ 2120 if (data->stop) 2121 send_stop_abort(host, data); 2122 } else { 2123 /* 2124 * If we don't have a command complete now we'll 2125 * never get one since we just reset everything; 2126 * better end the request. 2127 * 2128 * If we do have a command complete we'll fall 2129 * through to the SENDING_STOP command and 2130 * everything will be peachy keen. 2131 */ 2132 if (!test_bit(EVENT_CMD_COMPLETE, 2133 &host->pending_events)) { 2134 host->cmd = NULL; 2135 dw_mci_request_end(host, mrq); 2136 goto unlock; 2137 } 2138 } 2139 2140 /* 2141 * If err has non-zero, 2142 * stop-abort command has been already issued. 2143 */ 2144 prev_state = state = STATE_SENDING_STOP; 2145 2146 fallthrough; 2147 2148 case STATE_SENDING_STOP: 2149 if (!dw_mci_clear_pending_cmd_complete(host)) 2150 break; 2151 2152 /* CMD error in data command */ 2153 if (mrq->cmd->error && mrq->data) 2154 dw_mci_reset(host); 2155 2156 host->cmd = NULL; 2157 host->data = NULL; 2158 2159 if (!mrq->sbc && mrq->stop) 2160 dw_mci_command_complete(host, mrq->stop); 2161 else 2162 host->cmd_status = 0; 2163 2164 dw_mci_request_end(host, mrq); 2165 goto unlock; 2166 2167 case STATE_DATA_ERROR: 2168 if (!test_and_clear_bit(EVENT_XFER_COMPLETE, 2169 &host->pending_events)) 2170 break; 2171 2172 state = STATE_DATA_BUSY; 2173 break; 2174 } 2175 } while (state != prev_state); 2176 2177 host->state = state; 2178unlock: 2179 spin_unlock(&host->lock); 2180 2181} 2182 2183/* push final bytes to part_buf, only use during push */ 2184static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) 2185{ 2186 memcpy((void *)&host->part_buf, buf, cnt); 2187 host->part_buf_count = cnt; 2188} 2189 2190/* append bytes to part_buf, only use during push */ 2191static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) 2192{ 2193 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); 2194 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); 2195 host->part_buf_count += cnt; 2196 return cnt; 2197} 2198 2199/* pull first bytes from part_buf, only use during pull */ 2200static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) 2201{ 2202 cnt = min_t(int, cnt, host->part_buf_count); 2203 if (cnt) { 2204 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, 2205 cnt); 2206 host->part_buf_count -= cnt; 2207 host->part_buf_start += cnt; 2208 } 2209 return cnt; 2210} 2211 2212/* pull final bytes from the part_buf, assuming it's just been filled */ 2213static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) 2214{ 2215 memcpy(buf, &host->part_buf, cnt); 2216 host->part_buf_start = cnt; 2217 host->part_buf_count = (1 << host->data_shift) - cnt; 2218} 2219 2220static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) 2221{ 2222 struct mmc_data *data = host->data; 2223 int init_cnt = cnt; 2224 2225 /* try and push anything in the part_buf */ 2226 if (unlikely(host->part_buf_count)) { 2227 int len = dw_mci_push_part_bytes(host, buf, cnt); 2228 2229 buf += len; 2230 cnt -= len; 2231 if (host->part_buf_count == 2) { 2232 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2233 host->part_buf_count = 0; 2234 } 2235 } 2236#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2237 if (unlikely((unsigned long)buf & 0x1)) { 2238 while (cnt >= 2) { 2239 u16 aligned_buf[64]; 2240 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2241 int items = len >> 1; 2242 int i; 2243 /* memcpy from input buffer into aligned buffer */ 2244 memcpy(aligned_buf, buf, len); 2245 buf += len; 2246 cnt -= len; 2247 /* push data from aligned buffer into fifo */ 2248 for (i = 0; i < items; ++i) 2249 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); 2250 } 2251 } else 2252#endif 2253 { 2254 u16 *pdata = buf; 2255 2256 for (; cnt >= 2; cnt -= 2) 2257 mci_fifo_writew(host->fifo_reg, *pdata++); 2258 buf = pdata; 2259 } 2260 /* put anything remaining in the part_buf */ 2261 if (cnt) { 2262 dw_mci_set_part_bytes(host, buf, cnt); 2263 /* Push data if we have reached the expected data length */ 2264 if ((data->bytes_xfered + init_cnt) == 2265 (data->blksz * data->blocks)) 2266 mci_fifo_writew(host->fifo_reg, host->part_buf16); 2267 } 2268} 2269 2270static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) 2271{ 2272#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2273 if (unlikely((unsigned long)buf & 0x1)) { 2274 while (cnt >= 2) { 2275 /* pull data from fifo into aligned buffer */ 2276 u16 aligned_buf[64]; 2277 int len = min(cnt & -2, (int)sizeof(aligned_buf)); 2278 int items = len >> 1; 2279 int i; 2280 2281 for (i = 0; i < items; ++i) 2282 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); 2283 /* memcpy from aligned buffer into output buffer */ 2284 memcpy(buf, aligned_buf, len); 2285 buf += len; 2286 cnt -= len; 2287 } 2288 } else 2289#endif 2290 { 2291 u16 *pdata = buf; 2292 2293 for (; cnt >= 2; cnt -= 2) 2294 *pdata++ = mci_fifo_readw(host->fifo_reg); 2295 buf = pdata; 2296 } 2297 if (cnt) { 2298 host->part_buf16 = mci_fifo_readw(host->fifo_reg); 2299 dw_mci_pull_final_bytes(host, buf, cnt); 2300 } 2301} 2302 2303static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) 2304{ 2305 struct mmc_data *data = host->data; 2306 int init_cnt = cnt; 2307 2308 /* try and push anything in the part_buf */ 2309 if (unlikely(host->part_buf_count)) { 2310 int len = dw_mci_push_part_bytes(host, buf, cnt); 2311 2312 buf += len; 2313 cnt -= len; 2314 if (host->part_buf_count == 4) { 2315 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2316 host->part_buf_count = 0; 2317 } 2318 } 2319#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2320 if (unlikely((unsigned long)buf & 0x3)) { 2321 while (cnt >= 4) { 2322 u32 aligned_buf[32]; 2323 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2324 int items = len >> 2; 2325 int i; 2326 /* memcpy from input buffer into aligned buffer */ 2327 memcpy(aligned_buf, buf, len); 2328 buf += len; 2329 cnt -= len; 2330 /* push data from aligned buffer into fifo */ 2331 for (i = 0; i < items; ++i) 2332 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); 2333 } 2334 } else 2335#endif 2336 { 2337 u32 *pdata = buf; 2338 2339 for (; cnt >= 4; cnt -= 4) 2340 mci_fifo_writel(host->fifo_reg, *pdata++); 2341 buf = pdata; 2342 } 2343 /* put anything remaining in the part_buf */ 2344 if (cnt) { 2345 dw_mci_set_part_bytes(host, buf, cnt); 2346 /* Push data if we have reached the expected data length */ 2347 if ((data->bytes_xfered + init_cnt) == 2348 (data->blksz * data->blocks)) 2349 mci_fifo_writel(host->fifo_reg, host->part_buf32); 2350 } 2351} 2352 2353static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) 2354{ 2355#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2356 if (unlikely((unsigned long)buf & 0x3)) { 2357 while (cnt >= 4) { 2358 /* pull data from fifo into aligned buffer */ 2359 u32 aligned_buf[32]; 2360 int len = min(cnt & -4, (int)sizeof(aligned_buf)); 2361 int items = len >> 2; 2362 int i; 2363 2364 for (i = 0; i < items; ++i) 2365 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); 2366 /* memcpy from aligned buffer into output buffer */ 2367 memcpy(buf, aligned_buf, len); 2368 buf += len; 2369 cnt -= len; 2370 } 2371 } else 2372#endif 2373 { 2374 u32 *pdata = buf; 2375 2376 for (; cnt >= 4; cnt -= 4) 2377 *pdata++ = mci_fifo_readl(host->fifo_reg); 2378 buf = pdata; 2379 } 2380 if (cnt) { 2381 host->part_buf32 = mci_fifo_readl(host->fifo_reg); 2382 dw_mci_pull_final_bytes(host, buf, cnt); 2383 } 2384} 2385 2386static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) 2387{ 2388 struct mmc_data *data = host->data; 2389 int init_cnt = cnt; 2390 2391 /* try and push anything in the part_buf */ 2392 if (unlikely(host->part_buf_count)) { 2393 int len = dw_mci_push_part_bytes(host, buf, cnt); 2394 2395 buf += len; 2396 cnt -= len; 2397 2398 if (host->part_buf_count == 8) { 2399 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2400 host->part_buf_count = 0; 2401 } 2402 } 2403#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2404 if (unlikely((unsigned long)buf & 0x7)) { 2405 while (cnt >= 8) { 2406 u64 aligned_buf[16]; 2407 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2408 int items = len >> 3; 2409 int i; 2410 /* memcpy from input buffer into aligned buffer */ 2411 memcpy(aligned_buf, buf, len); 2412 buf += len; 2413 cnt -= len; 2414 /* push data from aligned buffer into fifo */ 2415 for (i = 0; i < items; ++i) 2416 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); 2417 } 2418 } else 2419#endif 2420 { 2421 u64 *pdata = buf; 2422 2423 for (; cnt >= 8; cnt -= 8) 2424 mci_fifo_writeq(host->fifo_reg, *pdata++); 2425 buf = pdata; 2426 } 2427 /* put anything remaining in the part_buf */ 2428 if (cnt) { 2429 dw_mci_set_part_bytes(host, buf, cnt); 2430 /* Push data if we have reached the expected data length */ 2431 if ((data->bytes_xfered + init_cnt) == 2432 (data->blksz * data->blocks)) 2433 mci_fifo_writeq(host->fifo_reg, host->part_buf); 2434 } 2435} 2436 2437static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) 2438{ 2439#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2440 if (unlikely((unsigned long)buf & 0x7)) { 2441 while (cnt >= 8) { 2442 /* pull data from fifo into aligned buffer */ 2443 u64 aligned_buf[16]; 2444 int len = min(cnt & -8, (int)sizeof(aligned_buf)); 2445 int items = len >> 3; 2446 int i; 2447 2448 for (i = 0; i < items; ++i) 2449 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); 2450 2451 /* memcpy from aligned buffer into output buffer */ 2452 memcpy(buf, aligned_buf, len); 2453 buf += len; 2454 cnt -= len; 2455 } 2456 } else 2457#endif 2458 { 2459 u64 *pdata = buf; 2460 2461 for (; cnt >= 8; cnt -= 8) 2462 *pdata++ = mci_fifo_readq(host->fifo_reg); 2463 buf = pdata; 2464 } 2465 if (cnt) { 2466 host->part_buf = mci_fifo_readq(host->fifo_reg); 2467 dw_mci_pull_final_bytes(host, buf, cnt); 2468 } 2469} 2470 2471static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) 2472{ 2473 int len; 2474 2475 /* get remaining partial bytes */ 2476 len = dw_mci_pull_part_bytes(host, buf, cnt); 2477 if (unlikely(len == cnt)) 2478 return; 2479 buf += len; 2480 cnt -= len; 2481 2482 /* get the rest of the data */ 2483 host->pull_data(host, buf, cnt); 2484} 2485 2486static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) 2487{ 2488 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2489 void *buf; 2490 unsigned int offset; 2491 struct mmc_data *data = host->data; 2492 int shift = host->data_shift; 2493 u32 status; 2494 unsigned int len; 2495 unsigned int remain, fcnt; 2496 2497 do { 2498 if (!sg_miter_next(sg_miter)) 2499 goto done; 2500 2501 host->sg = sg_miter->piter.sg; 2502 buf = sg_miter->addr; 2503 remain = sg_miter->length; 2504 offset = 0; 2505 2506 do { 2507 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) 2508 << shift) + host->part_buf_count; 2509 len = min(remain, fcnt); 2510 if (!len) 2511 break; 2512 dw_mci_pull_data(host, (void *)(buf + offset), len); 2513 data->bytes_xfered += len; 2514 offset += len; 2515 remain -= len; 2516 } while (remain); 2517 2518 sg_miter->consumed = offset; 2519 status = mci_readl(host, MINTSTS); 2520 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2521 /* if the RXDR is ready read again */ 2522 } while ((status & SDMMC_INT_RXDR) || 2523 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); 2524 2525 if (!remain) { 2526 if (!sg_miter_next(sg_miter)) 2527 goto done; 2528 sg_miter->consumed = 0; 2529 } 2530 sg_miter_stop(sg_miter); 2531 return; 2532 2533done: 2534 sg_miter_stop(sg_miter); 2535 host->sg = NULL; 2536 smp_wmb(); /* drain writebuffer */ 2537 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2538} 2539 2540static void dw_mci_write_data_pio(struct dw_mci *host) 2541{ 2542 struct sg_mapping_iter *sg_miter = &host->sg_miter; 2543 void *buf; 2544 unsigned int offset; 2545 struct mmc_data *data = host->data; 2546 int shift = host->data_shift; 2547 u32 status; 2548 unsigned int len; 2549 unsigned int fifo_depth = host->fifo_depth; 2550 unsigned int remain, fcnt; 2551 2552 do { 2553 if (!sg_miter_next(sg_miter)) 2554 goto done; 2555 2556 host->sg = sg_miter->piter.sg; 2557 buf = sg_miter->addr; 2558 remain = sg_miter->length; 2559 offset = 0; 2560 2561 do { 2562 fcnt = ((fifo_depth - 2563 SDMMC_GET_FCNT(mci_readl(host, STATUS))) 2564 << shift) - host->part_buf_count; 2565 len = min(remain, fcnt); 2566 if (!len) 2567 break; 2568 host->push_data(host, (void *)(buf + offset), len); 2569 data->bytes_xfered += len; 2570 offset += len; 2571 remain -= len; 2572 } while (remain); 2573 2574 sg_miter->consumed = offset; 2575 status = mci_readl(host, MINTSTS); 2576 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2577 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ 2578 2579 if (!remain) { 2580 if (!sg_miter_next(sg_miter)) 2581 goto done; 2582 sg_miter->consumed = 0; 2583 } 2584 sg_miter_stop(sg_miter); 2585 return; 2586 2587done: 2588 sg_miter_stop(sg_miter); 2589 host->sg = NULL; 2590 smp_wmb(); /* drain writebuffer */ 2591 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); 2592} 2593 2594static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) 2595{ 2596 del_timer(&host->cto_timer); 2597 2598 if (!host->cmd_status) 2599 host->cmd_status = status; 2600 2601 smp_wmb(); /* drain writebuffer */ 2602 2603 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2604 tasklet_schedule(&host->tasklet); 2605} 2606 2607static void dw_mci_handle_cd(struct dw_mci *host) 2608{ 2609 struct dw_mci_slot *slot = host->slot; 2610 2611 if (slot->mmc->ops->card_event) 2612 slot->mmc->ops->card_event(slot->mmc); 2613 mmc_detect_change(slot->mmc, 2614 msecs_to_jiffies(host->pdata->detect_delay_ms)); 2615} 2616 2617static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) 2618{ 2619 struct dw_mci *host = dev_id; 2620 u32 pending; 2621 struct dw_mci_slot *slot = host->slot; 2622 unsigned long irqflags; 2623 2624 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2625 2626 if (pending) { 2627 /* Check volt switch first, since it can look like an error */ 2628 if ((host->state == STATE_SENDING_CMD11) && 2629 (pending & SDMMC_INT_VOLT_SWITCH)) { 2630 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); 2631 pending &= ~SDMMC_INT_VOLT_SWITCH; 2632 2633 /* 2634 * Hold the lock; we know cmd11_timer can't be kicked 2635 * off after the lock is released, so safe to delete. 2636 */ 2637 spin_lock_irqsave(&host->irq_lock, irqflags); 2638 dw_mci_cmd_interrupt(host, pending); 2639 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2640 2641 del_timer(&host->cmd11_timer); 2642 } 2643 2644 if (pending & DW_MCI_CMD_ERROR_FLAGS) { 2645 spin_lock_irqsave(&host->irq_lock, irqflags); 2646 2647 del_timer(&host->cto_timer); 2648 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); 2649 host->cmd_status = pending; 2650 smp_wmb(); /* drain writebuffer */ 2651 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2652 2653 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2654 } 2655 2656 if (pending & DW_MCI_DATA_ERROR_FLAGS) { 2657 /* if there is an error report DATA_ERROR */ 2658 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); 2659 host->data_status = pending; 2660 smp_wmb(); /* drain writebuffer */ 2661 set_bit(EVENT_DATA_ERROR, &host->pending_events); 2662 tasklet_schedule(&host->tasklet); 2663 } 2664 2665 if (pending & SDMMC_INT_DATA_OVER) { 2666 spin_lock_irqsave(&host->irq_lock, irqflags); 2667 2668 del_timer(&host->dto_timer); 2669 2670 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); 2671 if (!host->data_status) 2672 host->data_status = pending; 2673 smp_wmb(); /* drain writebuffer */ 2674 if (host->dir_status == DW_MCI_RECV_STATUS) { 2675 if (host->sg != NULL) 2676 dw_mci_read_data_pio(host, true); 2677 } 2678 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 2679 tasklet_schedule(&host->tasklet); 2680 2681 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2682 } 2683 2684 if (pending & SDMMC_INT_RXDR) { 2685 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); 2686 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) 2687 dw_mci_read_data_pio(host, false); 2688 } 2689 2690 if (pending & SDMMC_INT_TXDR) { 2691 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); 2692 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) 2693 dw_mci_write_data_pio(host); 2694 } 2695 2696 if (pending & SDMMC_INT_CMD_DONE) { 2697 spin_lock_irqsave(&host->irq_lock, irqflags); 2698 2699 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); 2700 dw_mci_cmd_interrupt(host, pending); 2701 2702 spin_unlock_irqrestore(&host->irq_lock, irqflags); 2703 } 2704 2705 if (pending & SDMMC_INT_CD) { 2706 mci_writel(host, RINTSTS, SDMMC_INT_CD); 2707 dw_mci_handle_cd(host); 2708 } 2709 2710 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { 2711 mci_writel(host, RINTSTS, 2712 SDMMC_INT_SDIO(slot->sdio_id)); 2713 __dw_mci_enable_sdio_irq(slot, 0); 2714 sdio_signal_irq(slot->mmc); 2715 } 2716 2717 } 2718 2719 if (host->use_dma != TRANS_MODE_IDMAC) 2720 return IRQ_HANDLED; 2721 2722 /* Handle IDMA interrupts */ 2723 if (host->dma_64bit_address == 1) { 2724 pending = mci_readl(host, IDSTS64); 2725 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2726 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | 2727 SDMMC_IDMAC_INT_RI); 2728 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); 2729 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2730 host->dma_ops->complete((void *)host); 2731 } 2732 } else { 2733 pending = mci_readl(host, IDSTS); 2734 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { 2735 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | 2736 SDMMC_IDMAC_INT_RI); 2737 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); 2738 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) 2739 host->dma_ops->complete((void *)host); 2740 } 2741 } 2742 2743 return IRQ_HANDLED; 2744} 2745 2746static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) 2747{ 2748 struct dw_mci *host = slot->host; 2749 const struct dw_mci_drv_data *drv_data = host->drv_data; 2750 struct mmc_host *mmc = slot->mmc; 2751 int ctrl_id; 2752 2753 if (host->pdata->caps) 2754 mmc->caps = host->pdata->caps; 2755 2756 if (host->pdata->pm_caps) 2757 mmc->pm_caps = host->pdata->pm_caps; 2758 2759 if (host->dev->of_node) { 2760 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); 2761 if (ctrl_id < 0) 2762 ctrl_id = 0; 2763 } else { 2764 ctrl_id = to_platform_device(host->dev)->id; 2765 } 2766 2767 if (drv_data && drv_data->caps) { 2768 if (ctrl_id >= drv_data->num_caps) { 2769 dev_err(host->dev, "invalid controller id %d\n", 2770 ctrl_id); 2771 return -EINVAL; 2772 } 2773 mmc->caps |= drv_data->caps[ctrl_id]; 2774 } 2775 2776 if (host->pdata->caps2) 2777 mmc->caps2 = host->pdata->caps2; 2778 2779 mmc->f_min = DW_MCI_FREQ_MIN; 2780 if (!mmc->f_max) 2781 mmc->f_max = DW_MCI_FREQ_MAX; 2782 2783 /* Process SDIO IRQs through the sdio_irq_work. */ 2784 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2785 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2786 2787 return 0; 2788} 2789 2790static int dw_mci_init_slot(struct dw_mci *host) 2791{ 2792 struct mmc_host *mmc; 2793 struct dw_mci_slot *slot; 2794 int ret; 2795 2796 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 2797 if (!mmc) 2798 return -ENOMEM; 2799 2800 slot = mmc_priv(mmc); 2801 slot->id = 0; 2802 slot->sdio_id = host->sdio_id0 + slot->id; 2803 slot->mmc = mmc; 2804 slot->host = host; 2805 host->slot = slot; 2806 2807 mmc->ops = &dw_mci_ops; 2808 2809 /*if there are external regulators, get them*/ 2810 ret = mmc_regulator_get_supply(mmc); 2811 if (ret) 2812 goto err_host_allocated; 2813 2814 if (!mmc->ocr_avail) 2815 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 2816 2817 ret = mmc_of_parse(mmc); 2818 if (ret) 2819 goto err_host_allocated; 2820 2821 ret = dw_mci_init_slot_caps(slot); 2822 if (ret) 2823 goto err_host_allocated; 2824 2825 /* Useful defaults if platform data is unset. */ 2826 if (host->use_dma == TRANS_MODE_IDMAC) { 2827 mmc->max_segs = host->ring_size; 2828 mmc->max_blk_size = 65535; 2829 mmc->max_seg_size = 0x1000; 2830 mmc->max_req_size = mmc->max_seg_size * host->ring_size; 2831 mmc->max_blk_count = mmc->max_req_size / 512; 2832 } else if (host->use_dma == TRANS_MODE_EDMAC) { 2833 mmc->max_segs = 64; 2834 mmc->max_blk_size = 65535; 2835 mmc->max_blk_count = 65535; 2836 mmc->max_req_size = 2837 mmc->max_blk_size * mmc->max_blk_count; 2838 mmc->max_seg_size = mmc->max_req_size; 2839 } else { 2840 /* TRANS_MODE_PIO */ 2841 mmc->max_segs = 64; 2842 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ 2843 mmc->max_blk_count = 512; 2844 mmc->max_req_size = mmc->max_blk_size * 2845 mmc->max_blk_count; 2846 mmc->max_seg_size = mmc->max_req_size; 2847 } 2848 2849 dw_mci_get_cd(mmc); 2850 2851 ret = mmc_add_host(mmc); 2852 if (ret) 2853 goto err_host_allocated; 2854 2855#if defined(CONFIG_DEBUG_FS) 2856 dw_mci_init_debugfs(slot); 2857#endif 2858 2859 return 0; 2860 2861err_host_allocated: 2862 mmc_free_host(mmc); 2863 return ret; 2864} 2865 2866static void dw_mci_cleanup_slot(struct dw_mci_slot *slot) 2867{ 2868 /* Debugfs stuff is cleaned up by mmc core */ 2869 mmc_remove_host(slot->mmc); 2870 slot->host->slot = NULL; 2871 mmc_free_host(slot->mmc); 2872} 2873 2874static void dw_mci_init_dma(struct dw_mci *host) 2875{ 2876 int addr_config; 2877 struct device *dev = host->dev; 2878 2879 /* 2880 * Check tansfer mode from HCON[17:16] 2881 * Clear the ambiguous description of dw_mmc databook: 2882 * 2b'00: No DMA Interface -> Actually means using Internal DMA block 2883 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block 2884 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block 2885 * 2b'11: Non DW DMA Interface -> pio only 2886 * Compared to DesignWare DMA Interface, Generic DMA Interface has a 2887 * simpler request/acknowledge handshake mechanism and both of them 2888 * are regarded as external dma master for dw_mmc. 2889 */ 2890 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); 2891 if (host->use_dma == DMA_INTERFACE_IDMA) { 2892 host->use_dma = TRANS_MODE_IDMAC; 2893 } else if (host->use_dma == DMA_INTERFACE_DWDMA || 2894 host->use_dma == DMA_INTERFACE_GDMA) { 2895 host->use_dma = TRANS_MODE_EDMAC; 2896 } else { 2897 goto no_dma; 2898 } 2899 2900 /* Determine which DMA interface to use */ 2901 if (host->use_dma == TRANS_MODE_IDMAC) { 2902 /* 2903 * Check ADDR_CONFIG bit in HCON to find 2904 * IDMAC address bus width 2905 */ 2906 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON)); 2907 2908 if (addr_config == 1) { 2909 /* host supports IDMAC in 64-bit address mode */ 2910 host->dma_64bit_address = 1; 2911 dev_info(host->dev, 2912 "IDMAC supports 64-bit address mode.\n"); 2913 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) 2914 dma_set_coherent_mask(host->dev, 2915 DMA_BIT_MASK(64)); 2916 } else { 2917 /* host supports IDMAC in 32-bit address mode */ 2918 host->dma_64bit_address = 0; 2919 dev_info(host->dev, 2920 "IDMAC supports 32-bit address mode.\n"); 2921 } 2922 2923 /* Alloc memory for sg translation */ 2924 host->sg_cpu = dmam_alloc_coherent(host->dev, 2925 DESC_RING_BUF_SZ, 2926 &host->sg_dma, GFP_KERNEL); 2927 if (!host->sg_cpu) { 2928 dev_err(host->dev, 2929 "%s: could not alloc DMA memory\n", 2930 __func__); 2931 goto no_dma; 2932 } 2933 2934 host->dma_ops = &dw_mci_idmac_ops; 2935 dev_info(host->dev, "Using internal DMA controller.\n"); 2936 } else { 2937 /* TRANS_MODE_EDMAC: check dma bindings again */ 2938 if ((device_property_read_string_array(dev, "dma-names", 2939 NULL, 0) < 0) || 2940 !device_property_present(dev, "dmas")) { 2941 goto no_dma; 2942 } 2943 host->dma_ops = &dw_mci_edmac_ops; 2944 dev_info(host->dev, "Using external DMA controller.\n"); 2945 } 2946 2947 if (host->dma_ops->init && host->dma_ops->start && 2948 host->dma_ops->stop && host->dma_ops->cleanup) { 2949 if (host->dma_ops->init(host)) { 2950 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", 2951 __func__); 2952 goto no_dma; 2953 } 2954 } else { 2955 dev_err(host->dev, "DMA initialization not found.\n"); 2956 goto no_dma; 2957 } 2958 2959 return; 2960 2961no_dma: 2962 dev_info(host->dev, "Using PIO mode.\n"); 2963 host->use_dma = TRANS_MODE_PIO; 2964} 2965 2966static void dw_mci_cmd11_timer(struct timer_list *t) 2967{ 2968 struct dw_mci *host = from_timer(host, t, cmd11_timer); 2969 2970 if (host->state != STATE_SENDING_CMD11) { 2971 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); 2972 return; 2973 } 2974 2975 host->cmd_status = SDMMC_INT_RTO; 2976 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 2977 tasklet_schedule(&host->tasklet); 2978} 2979 2980static void dw_mci_cto_timer(struct timer_list *t) 2981{ 2982 struct dw_mci *host = from_timer(host, t, cto_timer); 2983 unsigned long irqflags; 2984 u32 pending; 2985 2986 spin_lock_irqsave(&host->irq_lock, irqflags); 2987 2988 /* 2989 * If somehow we have very bad interrupt latency it's remotely possible 2990 * that the timer could fire while the interrupt is still pending or 2991 * while the interrupt is midway through running. Let's be paranoid 2992 * and detect those two cases. Note that this is paranoia is somewhat 2993 * justified because in this function we don't actually cancel the 2994 * pending command in the controller--we just assume it will never come. 2995 */ 2996 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 2997 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) { 2998 /* The interrupt should fire; no need to act but we can warn */ 2999 dev_warn(host->dev, "Unexpected interrupt latency\n"); 3000 goto exit; 3001 } 3002 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { 3003 /* Presumably interrupt handler couldn't delete the timer */ 3004 dev_warn(host->dev, "CTO timeout when already completed\n"); 3005 goto exit; 3006 } 3007 3008 /* 3009 * Continued paranoia to make sure we're in the state we expect. 3010 * This paranoia isn't really justified but it seems good to be safe. 3011 */ 3012 switch (host->state) { 3013 case STATE_SENDING_CMD11: 3014 case STATE_SENDING_CMD: 3015 case STATE_SENDING_STOP: 3016 /* 3017 * If CMD_DONE interrupt does NOT come in sending command 3018 * state, we should notify the driver to terminate current 3019 * transfer and report a command timeout to the core. 3020 */ 3021 host->cmd_status = SDMMC_INT_RTO; 3022 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); 3023 tasklet_schedule(&host->tasklet); 3024 break; 3025 default: 3026 dev_warn(host->dev, "Unexpected command timeout, state %d\n", 3027 host->state); 3028 break; 3029 } 3030 3031exit: 3032 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3033} 3034 3035static void dw_mci_dto_timer(struct timer_list *t) 3036{ 3037 struct dw_mci *host = from_timer(host, t, dto_timer); 3038 unsigned long irqflags; 3039 u32 pending; 3040 3041 spin_lock_irqsave(&host->irq_lock, irqflags); 3042 3043 /* 3044 * The DTO timer is much longer than the CTO timer, so it's even less 3045 * likely that we'll these cases, but it pays to be paranoid. 3046 */ 3047 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ 3048 if (pending & SDMMC_INT_DATA_OVER) { 3049 /* The interrupt should fire; no need to act but we can warn */ 3050 dev_warn(host->dev, "Unexpected data interrupt latency\n"); 3051 goto exit; 3052 } 3053 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { 3054 /* Presumably interrupt handler couldn't delete the timer */ 3055 dev_warn(host->dev, "DTO timeout when already completed\n"); 3056 goto exit; 3057 } 3058 3059 /* 3060 * Continued paranoia to make sure we're in the state we expect. 3061 * This paranoia isn't really justified but it seems good to be safe. 3062 */ 3063 switch (host->state) { 3064 case STATE_SENDING_DATA: 3065 case STATE_DATA_BUSY: 3066 /* 3067 * If DTO interrupt does NOT come in sending data state, 3068 * we should notify the driver to terminate current transfer 3069 * and report a data timeout to the core. 3070 */ 3071 host->data_status = SDMMC_INT_DRTO; 3072 set_bit(EVENT_DATA_ERROR, &host->pending_events); 3073 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); 3074 tasklet_schedule(&host->tasklet); 3075 break; 3076 default: 3077 dev_warn(host->dev, "Unexpected data timeout, state %d\n", 3078 host->state); 3079 break; 3080 } 3081 3082exit: 3083 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3084} 3085 3086#ifdef CONFIG_OF 3087static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3088{ 3089 struct dw_mci_board *pdata; 3090 struct device *dev = host->dev; 3091 const struct dw_mci_drv_data *drv_data = host->drv_data; 3092 int ret; 3093 u32 clock_frequency; 3094 3095 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3096 if (!pdata) 3097 return ERR_PTR(-ENOMEM); 3098 3099 /* find reset controller when exist */ 3100 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); 3101 if (IS_ERR(pdata->rstc)) { 3102 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) 3103 return ERR_PTR(-EPROBE_DEFER); 3104 } 3105 3106 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) 3107 dev_info(dev, 3108 "fifo-depth property not found, using value of FIFOTH register as default\n"); 3109 3110 device_property_read_u32(dev, "card-detect-delay", 3111 &pdata->detect_delay_ms); 3112 3113 device_property_read_u32(dev, "data-addr", &host->data_addr_override); 3114 3115 if (device_property_present(dev, "fifo-watermark-aligned")) 3116 host->wm_aligned = true; 3117 3118 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) 3119 pdata->bus_hz = clock_frequency; 3120 3121 if (drv_data && drv_data->parse_dt) { 3122 ret = drv_data->parse_dt(host); 3123 if (ret) 3124 return ERR_PTR(ret); 3125 } 3126 3127 return pdata; 3128} 3129 3130#else /* CONFIG_OF */ 3131static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) 3132{ 3133 return ERR_PTR(-EINVAL); 3134} 3135#endif /* CONFIG_OF */ 3136 3137static void dw_mci_enable_cd(struct dw_mci *host) 3138{ 3139 unsigned long irqflags; 3140 u32 temp; 3141 3142 /* 3143 * No need for CD if all slots have a non-error GPIO 3144 * as well as broken card detection is found. 3145 */ 3146 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) 3147 return; 3148 3149 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { 3150 spin_lock_irqsave(&host->irq_lock, irqflags); 3151 temp = mci_readl(host, INTMASK); 3152 temp |= SDMMC_INT_CD; 3153 mci_writel(host, INTMASK, temp); 3154 spin_unlock_irqrestore(&host->irq_lock, irqflags); 3155 } 3156} 3157 3158int dw_mci_probe(struct dw_mci *host) 3159{ 3160 const struct dw_mci_drv_data *drv_data = host->drv_data; 3161 int width, i, ret = 0; 3162 u32 fifo_size; 3163 3164 if (!host->pdata) { 3165 host->pdata = dw_mci_parse_dt(host); 3166 if (IS_ERR(host->pdata)) 3167 return dev_err_probe(host->dev, PTR_ERR(host->pdata), 3168 "platform data not available\n"); 3169 } 3170 3171 host->biu_clk = devm_clk_get(host->dev, "biu"); 3172 if (IS_ERR(host->biu_clk)) { 3173 dev_dbg(host->dev, "biu clock not available\n"); 3174 } else { 3175 ret = clk_prepare_enable(host->biu_clk); 3176 if (ret) { 3177 dev_err(host->dev, "failed to enable biu clock\n"); 3178 return ret; 3179 } 3180 } 3181 3182 host->ciu_clk = devm_clk_get(host->dev, "ciu"); 3183 if (IS_ERR(host->ciu_clk)) { 3184 dev_dbg(host->dev, "ciu clock not available\n"); 3185 host->bus_hz = host->pdata->bus_hz; 3186 } else { 3187 ret = clk_prepare_enable(host->ciu_clk); 3188 if (ret) { 3189 dev_err(host->dev, "failed to enable ciu clock\n"); 3190 goto err_clk_biu; 3191 } 3192 3193 if (host->pdata->bus_hz) { 3194 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); 3195 if (ret) 3196 dev_warn(host->dev, 3197 "Unable to set bus rate to %uHz\n", 3198 host->pdata->bus_hz); 3199 } 3200 host->bus_hz = clk_get_rate(host->ciu_clk); 3201 } 3202 3203 if (!host->bus_hz) { 3204 dev_err(host->dev, 3205 "Platform data must supply bus speed\n"); 3206 ret = -ENODEV; 3207 goto err_clk_ciu; 3208 } 3209 3210 if (!IS_ERR(host->pdata->rstc)) { 3211 reset_control_assert(host->pdata->rstc); 3212 usleep_range(10, 50); 3213 reset_control_deassert(host->pdata->rstc); 3214 } 3215 3216 if (drv_data && drv_data->init) { 3217 ret = drv_data->init(host); 3218 if (ret) { 3219 dev_err(host->dev, 3220 "implementation specific init failed\n"); 3221 goto err_clk_ciu; 3222 } 3223 } 3224 3225 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); 3226 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); 3227 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); 3228 3229 spin_lock_init(&host->lock); 3230 spin_lock_init(&host->irq_lock); 3231 INIT_LIST_HEAD(&host->queue); 3232 3233 /* 3234 * Get the host data width - this assumes that HCON has been set with 3235 * the correct values. 3236 */ 3237 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON)); 3238 if (!i) { 3239 host->push_data = dw_mci_push_data16; 3240 host->pull_data = dw_mci_pull_data16; 3241 width = 16; 3242 host->data_shift = 1; 3243 } else if (i == 2) { 3244 host->push_data = dw_mci_push_data64; 3245 host->pull_data = dw_mci_pull_data64; 3246 width = 64; 3247 host->data_shift = 3; 3248 } else { 3249 /* Check for a reserved value, and warn if it is */ 3250 WARN((i != 1), 3251 "HCON reports a reserved host data width!\n" 3252 "Defaulting to 32-bit access.\n"); 3253 host->push_data = dw_mci_push_data32; 3254 host->pull_data = dw_mci_pull_data32; 3255 width = 32; 3256 host->data_shift = 2; 3257 } 3258 3259 /* Reset all blocks */ 3260 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3261 ret = -ENODEV; 3262 goto err_clk_ciu; 3263 } 3264 3265 host->dma_ops = host->pdata->dma_ops; 3266 dw_mci_init_dma(host); 3267 3268 /* Clear the interrupts for the host controller */ 3269 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3270 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3271 3272 /* Put in max timeout */ 3273 mci_writel(host, TMOUT, 0xFFFFFFFF); 3274 3275 /* 3276 * FIFO threshold settings RxMark = fifo_size / 2 - 1, 3277 * Tx Mark = fifo_size / 2 DMA Size = 8 3278 */ 3279 if (!host->pdata->fifo_depth) { 3280 /* 3281 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may 3282 * have been overwritten by the bootloader, just like we're 3283 * about to do, so if you know the value for your hardware, you 3284 * should put it in the platform data. 3285 */ 3286 fifo_size = mci_readl(host, FIFOTH); 3287 fifo_size = 1 + ((fifo_size >> 16) & 0xfff); 3288 } else { 3289 fifo_size = host->pdata->fifo_depth; 3290 } 3291 host->fifo_depth = fifo_size; 3292 host->fifoth_val = 3293 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); 3294 mci_writel(host, FIFOTH, host->fifoth_val); 3295 3296 /* disable clock to CIU */ 3297 mci_writel(host, CLKENA, 0); 3298 mci_writel(host, CLKSRC, 0); 3299 3300 /* 3301 * In 2.40a spec, Data offset is changed. 3302 * Need to check the version-id and set data-offset for DATA register. 3303 */ 3304 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); 3305 dev_info(host->dev, "Version ID is %04x\n", host->verid); 3306 3307 if (host->data_addr_override) 3308 host->fifo_reg = host->regs + host->data_addr_override; 3309 else if (host->verid < DW_MMC_240A) 3310 host->fifo_reg = host->regs + DATA_OFFSET; 3311 else 3312 host->fifo_reg = host->regs + DATA_240A_OFFSET; 3313 3314 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); 3315 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, 3316 host->irq_flags, "dw-mci", host); 3317 if (ret) 3318 goto err_dmaunmap; 3319 3320 /* 3321 * Enable interrupts for command done, data over, data empty, 3322 * receive ready and error such as transmit, receive timeout, crc error 3323 */ 3324 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3325 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3326 DW_MCI_ERROR_FLAGS); 3327 /* Enable mci interrupt */ 3328 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3329 3330 dev_info(host->dev, 3331 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", 3332 host->irq, width, fifo_size); 3333 3334 /* We need at least one slot to succeed */ 3335 ret = dw_mci_init_slot(host); 3336 if (ret) { 3337 dev_dbg(host->dev, "slot %d init failed\n", i); 3338 goto err_dmaunmap; 3339 } 3340 3341 /* Now that slots are all setup, we can enable card detect */ 3342 dw_mci_enable_cd(host); 3343 3344 return 0; 3345 3346err_dmaunmap: 3347 if (host->use_dma && host->dma_ops->exit) 3348 host->dma_ops->exit(host); 3349 3350 if (!IS_ERR(host->pdata->rstc)) 3351 reset_control_assert(host->pdata->rstc); 3352 3353err_clk_ciu: 3354 clk_disable_unprepare(host->ciu_clk); 3355 3356err_clk_biu: 3357 clk_disable_unprepare(host->biu_clk); 3358 3359 return ret; 3360} 3361EXPORT_SYMBOL(dw_mci_probe); 3362 3363void dw_mci_remove(struct dw_mci *host) 3364{ 3365 dev_dbg(host->dev, "remove slot\n"); 3366 if (host->slot) 3367 dw_mci_cleanup_slot(host->slot); 3368 3369 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3370 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ 3371 3372 /* disable clock to CIU */ 3373 mci_writel(host, CLKENA, 0); 3374 mci_writel(host, CLKSRC, 0); 3375 3376 if (host->use_dma && host->dma_ops->exit) 3377 host->dma_ops->exit(host); 3378 3379 if (!IS_ERR(host->pdata->rstc)) 3380 reset_control_assert(host->pdata->rstc); 3381 3382 clk_disable_unprepare(host->ciu_clk); 3383 clk_disable_unprepare(host->biu_clk); 3384} 3385EXPORT_SYMBOL(dw_mci_remove); 3386 3387 3388 3389#ifdef CONFIG_PM 3390int dw_mci_runtime_suspend(struct device *dev) 3391{ 3392 struct dw_mci *host = dev_get_drvdata(dev); 3393 3394 if (host->use_dma && host->dma_ops->exit) 3395 host->dma_ops->exit(host); 3396 3397 clk_disable_unprepare(host->ciu_clk); 3398 3399 if (host->slot && 3400 (mmc_can_gpio_cd(host->slot->mmc) || 3401 !mmc_card_is_removable(host->slot->mmc))) 3402 clk_disable_unprepare(host->biu_clk); 3403 3404 return 0; 3405} 3406EXPORT_SYMBOL(dw_mci_runtime_suspend); 3407 3408int dw_mci_runtime_resume(struct device *dev) 3409{ 3410 int ret = 0; 3411 struct dw_mci *host = dev_get_drvdata(dev); 3412 3413 if (host->slot && 3414 (mmc_can_gpio_cd(host->slot->mmc) || 3415 !mmc_card_is_removable(host->slot->mmc))) { 3416 ret = clk_prepare_enable(host->biu_clk); 3417 if (ret) 3418 return ret; 3419 } 3420 3421 ret = clk_prepare_enable(host->ciu_clk); 3422 if (ret) 3423 goto err; 3424 3425 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { 3426 clk_disable_unprepare(host->ciu_clk); 3427 ret = -ENODEV; 3428 goto err; 3429 } 3430 3431 if (host->use_dma && host->dma_ops->init) 3432 host->dma_ops->init(host); 3433 3434 /* 3435 * Restore the initial value at FIFOTH register 3436 * And Invalidate the prev_blksz with zero 3437 */ 3438 mci_writel(host, FIFOTH, host->fifoth_val); 3439 host->prev_blksz = 0; 3440 3441 /* Put in max timeout */ 3442 mci_writel(host, TMOUT, 0xFFFFFFFF); 3443 3444 mci_writel(host, RINTSTS, 0xFFFFFFFF); 3445 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | 3446 SDMMC_INT_TXDR | SDMMC_INT_RXDR | 3447 DW_MCI_ERROR_FLAGS); 3448 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); 3449 3450 3451 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) 3452 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); 3453 3454 /* Force setup bus to guarantee available clock output */ 3455 dw_mci_setup_bus(host->slot, true); 3456 3457 /* Re-enable SDIO interrupts. */ 3458 if (sdio_irq_claimed(host->slot->mmc)) 3459 __dw_mci_enable_sdio_irq(host->slot, 1); 3460 3461 /* Now that slots are all setup, we can enable card detect */ 3462 dw_mci_enable_cd(host); 3463 3464 return 0; 3465 3466err: 3467 if (host->slot && 3468 (mmc_can_gpio_cd(host->slot->mmc) || 3469 !mmc_card_is_removable(host->slot->mmc))) 3470 clk_disable_unprepare(host->biu_clk); 3471 3472 return ret; 3473} 3474EXPORT_SYMBOL(dw_mci_runtime_resume); 3475#endif /* CONFIG_PM */ 3476 3477static int __init dw_mci_init(void) 3478{ 3479 pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); 3480 return 0; 3481} 3482 3483static void __exit dw_mci_exit(void) 3484{ 3485} 3486 3487module_init(dw_mci_init); 3488module_exit(dw_mci_exit); 3489 3490MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); 3491MODULE_AUTHOR("NXP Semiconductor VietNam"); 3492MODULE_AUTHOR("Imagination Technologies Ltd"); 3493MODULE_LICENSE("GPL v2"); 3494