18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
48c2ecf20Sopenharmony_ci * Intel Management Engine Interface (Intel MEI) Linux driver
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci#ifndef _MEI_INTERFACE_H_
88c2ecf20Sopenharmony_ci#define _MEI_INTERFACE_H_
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci#include <linux/irqreturn.h>
118c2ecf20Sopenharmony_ci#include <linux/pci.h>
128c2ecf20Sopenharmony_ci#include <linux/mei.h>
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci#include "mei_dev.h"
158c2ecf20Sopenharmony_ci#include "client.h"
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci/*
188c2ecf20Sopenharmony_ci * mei_cfg - mei device configuration
198c2ecf20Sopenharmony_ci *
208c2ecf20Sopenharmony_ci * @fw_status: FW status
218c2ecf20Sopenharmony_ci * @quirk_probe: device exclusion quirk
228c2ecf20Sopenharmony_ci * @kind: MEI head kind
238c2ecf20Sopenharmony_ci * @dma_size: device DMA buffers size
248c2ecf20Sopenharmony_ci * @fw_ver_supported: is fw version retrievable from FW
258c2ecf20Sopenharmony_ci * @hw_trc_supported: does the hw support trc register
268c2ecf20Sopenharmony_ci */
278c2ecf20Sopenharmony_cistruct mei_cfg {
288c2ecf20Sopenharmony_ci	const struct mei_fw_status fw_status;
298c2ecf20Sopenharmony_ci	bool (*quirk_probe)(const struct pci_dev *pdev);
308c2ecf20Sopenharmony_ci	const char *kind;
318c2ecf20Sopenharmony_ci	size_t dma_size[DMA_DSCR_NUM];
328c2ecf20Sopenharmony_ci	u32 fw_ver_supported:1;
338c2ecf20Sopenharmony_ci	u32 hw_trc_supported:1;
348c2ecf20Sopenharmony_ci};
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ci#define MEI_PCI_DEVICE(dev, cfg) \
388c2ecf20Sopenharmony_ci	.vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
398c2ecf20Sopenharmony_ci	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
408c2ecf20Sopenharmony_ci	.driver_data = (kernel_ulong_t)(cfg),
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci#define MEI_ME_RPM_TIMEOUT    500 /* ms */
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci/**
458c2ecf20Sopenharmony_ci * struct mei_me_hw - me hw specific data
468c2ecf20Sopenharmony_ci *
478c2ecf20Sopenharmony_ci * @cfg: per device generation config and ops
488c2ecf20Sopenharmony_ci * @mem_addr: io memory address
498c2ecf20Sopenharmony_ci * @irq: irq number
508c2ecf20Sopenharmony_ci * @pg_state: power gating state
518c2ecf20Sopenharmony_ci * @d0i3_supported: di03 support
528c2ecf20Sopenharmony_ci * @hbuf_depth: depth of hardware host/write buffer in slots
538c2ecf20Sopenharmony_ci * @read_fws: read FW status register handler
548c2ecf20Sopenharmony_ci */
558c2ecf20Sopenharmony_cistruct mei_me_hw {
568c2ecf20Sopenharmony_ci	const struct mei_cfg *cfg;
578c2ecf20Sopenharmony_ci	void __iomem *mem_addr;
588c2ecf20Sopenharmony_ci	int irq;
598c2ecf20Sopenharmony_ci	enum mei_pg_state pg_state;
608c2ecf20Sopenharmony_ci	bool d0i3_supported;
618c2ecf20Sopenharmony_ci	u8 hbuf_depth;
628c2ecf20Sopenharmony_ci	int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
638c2ecf20Sopenharmony_ci};
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ci#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
668c2ecf20Sopenharmony_ci
678c2ecf20Sopenharmony_ci/**
688c2ecf20Sopenharmony_ci * enum mei_cfg_idx - indices to platform specific configurations.
698c2ecf20Sopenharmony_ci *
708c2ecf20Sopenharmony_ci * Note: has to be synchronized with mei_cfg_list[]
718c2ecf20Sopenharmony_ci *
728c2ecf20Sopenharmony_ci * @MEI_ME_UNDEF_CFG:      Lower sentinel.
738c2ecf20Sopenharmony_ci * @MEI_ME_ICH_CFG:        I/O Controller Hub legacy devices.
748c2ecf20Sopenharmony_ci * @MEI_ME_ICH10_CFG:      I/O Controller Hub platforms Gen10
758c2ecf20Sopenharmony_ci * @MEI_ME_PCH6_CFG:       Platform Controller Hub platforms (Gen6).
768c2ecf20Sopenharmony_ci * @MEI_ME_PCH7_CFG:       Platform Controller Hub platforms (Gen7).
778c2ecf20Sopenharmony_ci * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
788c2ecf20Sopenharmony_ci *                         with quirk for Node Manager exclusion.
798c2ecf20Sopenharmony_ci * @MEI_ME_PCH8_CFG:       Platform Controller Hub Gen8 and newer
808c2ecf20Sopenharmony_ci *                         client platforms.
818c2ecf20Sopenharmony_ci * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
828c2ecf20Sopenharmony_ci *                         client platforms (iTouch).
838c2ecf20Sopenharmony_ci * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
848c2ecf20Sopenharmony_ci *                         servers platforms with quirk for
858c2ecf20Sopenharmony_ci *                         SPS firmware exclusion.
868c2ecf20Sopenharmony_ci * @MEI_ME_PCH12_CFG:      Platform Controller Hub Gen12 and newer
878c2ecf20Sopenharmony_ci * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
888c2ecf20Sopenharmony_ci *                         servers platforms with quirk for
898c2ecf20Sopenharmony_ci *                         SPS firmware exclusion.
908c2ecf20Sopenharmony_ci * @MEI_ME_PCH12_SPS_CFG:  Platform Controller Hub Gen12 5.0 and newer
918c2ecf20Sopenharmony_ci *                         servers platforms with quirk for
928c2ecf20Sopenharmony_ci *                         SPS firmware exclusion.
938c2ecf20Sopenharmony_ci * @MEI_ME_PCH15_CFG:      Platform Controller Hub Gen15 and newer
948c2ecf20Sopenharmony_ci * @MEI_ME_PCH15_SPS_CFG:  Platform Controller Hub Gen15 and newer
958c2ecf20Sopenharmony_ci *                         servers platforms with quirk for
968c2ecf20Sopenharmony_ci *                         SPS firmware exclusion.
978c2ecf20Sopenharmony_ci * @MEI_ME_NUM_CFG:        Upper Sentinel.
988c2ecf20Sopenharmony_ci */
998c2ecf20Sopenharmony_cienum mei_cfg_idx {
1008c2ecf20Sopenharmony_ci	MEI_ME_UNDEF_CFG,
1018c2ecf20Sopenharmony_ci	MEI_ME_ICH_CFG,
1028c2ecf20Sopenharmony_ci	MEI_ME_ICH10_CFG,
1038c2ecf20Sopenharmony_ci	MEI_ME_PCH6_CFG,
1048c2ecf20Sopenharmony_ci	MEI_ME_PCH7_CFG,
1058c2ecf20Sopenharmony_ci	MEI_ME_PCH_CPT_PBG_CFG,
1068c2ecf20Sopenharmony_ci	MEI_ME_PCH8_CFG,
1078c2ecf20Sopenharmony_ci	MEI_ME_PCH8_ITOUCH_CFG,
1088c2ecf20Sopenharmony_ci	MEI_ME_PCH8_SPS_4_CFG,
1098c2ecf20Sopenharmony_ci	MEI_ME_PCH12_CFG,
1108c2ecf20Sopenharmony_ci	MEI_ME_PCH12_SPS_4_CFG,
1118c2ecf20Sopenharmony_ci	MEI_ME_PCH12_SPS_CFG,
1128c2ecf20Sopenharmony_ci	MEI_ME_PCH12_SPS_ITOUCH_CFG,
1138c2ecf20Sopenharmony_ci	MEI_ME_PCH15_CFG,
1148c2ecf20Sopenharmony_ci	MEI_ME_PCH15_SPS_CFG,
1158c2ecf20Sopenharmony_ci	MEI_ME_NUM_CFG,
1168c2ecf20Sopenharmony_ci};
1178c2ecf20Sopenharmony_ci
1188c2ecf20Sopenharmony_ciconst struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
1198c2ecf20Sopenharmony_ci
1208c2ecf20Sopenharmony_cistruct mei_device *mei_me_dev_init(struct device *parent,
1218c2ecf20Sopenharmony_ci				   const struct mei_cfg *cfg);
1228c2ecf20Sopenharmony_ci
1238c2ecf20Sopenharmony_ciint mei_me_pg_enter_sync(struct mei_device *dev);
1248c2ecf20Sopenharmony_ciint mei_me_pg_exit_sync(struct mei_device *dev);
1258c2ecf20Sopenharmony_ci
1268c2ecf20Sopenharmony_ciirqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
1278c2ecf20Sopenharmony_ciirqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
1288c2ecf20Sopenharmony_ci
1298c2ecf20Sopenharmony_ci#endif /* _MEI_INTERFACE_H_ */
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