1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2019 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8#ifndef GOYAP_H_
9#define GOYAP_H_
10
11#include <uapi/misc/habanalabs.h>
12#include "../common/habanalabs.h"
13#include "../include/common/hl_boot_if.h"
14#include "../include/goya/goya_packets.h"
15#include "../include/goya/goya.h"
16#include "../include/goya/goya_async_events.h"
17#include "../include/goya/goya_fw_if.h"
18
19#define NUMBER_OF_CMPLT_QUEUES		5
20#define NUMBER_OF_EXT_HW_QUEUES		5
21#define NUMBER_OF_CPU_HW_QUEUES		1
22#define NUMBER_OF_INT_HW_QUEUES		9
23#define NUMBER_OF_HW_QUEUES		(NUMBER_OF_EXT_HW_QUEUES + \
24					NUMBER_OF_CPU_HW_QUEUES + \
25					NUMBER_OF_INT_HW_QUEUES)
26
27/*
28 * Number of MSIX interrupts IDS:
29 * Each completion queue has 1 ID
30 * The event queue has 1 ID
31 */
32#define NUMBER_OF_INTERRUPTS		(NUMBER_OF_CMPLT_QUEUES + 1)
33
34#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
35#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
36#endif
37
38#define QMAN_FENCE_TIMEOUT_USEC		10000		/* 10 ms */
39
40#define QMAN_STOP_TIMEOUT_USEC		100000		/* 100 ms */
41
42#define CORESIGHT_TIMEOUT_USEC		100000		/* 100 ms */
43
44#define GOYA_CPU_TIMEOUT_USEC		15000000	/* 15s */
45
46#define TPC_ENABLED_MASK		0xFF
47
48#define PLL_HIGH_DEFAULT		1575000000	/* 1.575 GHz */
49
50#define MAX_POWER_DEFAULT		200000		/* 200W */
51
52#define DRAM_PHYS_DEFAULT_SIZE		0x100000000ull	/* 4GB */
53
54#define GOYA_DEFAULT_CARD_NAME		"HL1000"
55
56#define GOYA_MAX_PENDING_CS		64
57
58#if !IS_MAX_PENDING_CS_VALID(GOYA_MAX_PENDING_CS)
59#error "GOYA_MAX_PENDING_CS must be power of 2 and greater than 1"
60#endif
61
62/* DRAM Memory Map */
63
64#define CPU_FW_IMAGE_SIZE		0x10000000	/* 256MB */
65#define MMU_PAGE_TABLES_SIZE		0x0FC00000	/* 252MB */
66#define MMU_DRAM_DEFAULT_PAGE_SIZE	0x00200000	/* 2MB */
67#define MMU_CACHE_MNG_SIZE		0x00001000	/* 4KB */
68
69#define CPU_FW_IMAGE_ADDR		DRAM_PHYS_BASE
70#define MMU_PAGE_TABLES_ADDR		(CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
71#define MMU_DRAM_DEFAULT_PAGE_ADDR	(MMU_PAGE_TABLES_ADDR + \
72						MMU_PAGE_TABLES_SIZE)
73#define MMU_CACHE_MNG_ADDR		(MMU_DRAM_DEFAULT_PAGE_ADDR + \
74					MMU_DRAM_DEFAULT_PAGE_SIZE)
75#define DRAM_DRIVER_END_ADDR		(MMU_CACHE_MNG_ADDR + \
76						MMU_CACHE_MNG_SIZE)
77
78#define DRAM_BASE_ADDR_USER		0x20000000
79
80#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
81#error "Driver must reserve no more than 512MB"
82#endif
83
84/*
85 * SRAM Memory Map for Driver
86 *
87 * Driver occupies DRIVER_SRAM_SIZE bytes from the start of SRAM. It is used for
88 * MME/TPC QMANs
89 *
90 */
91
92#define MME_QMAN_BASE_OFFSET	0x000000	/* Must be 0 */
93#define MME_QMAN_LENGTH		64
94#define TPC_QMAN_LENGTH		64
95
96#define TPC0_QMAN_BASE_OFFSET	(MME_QMAN_BASE_OFFSET + \
97				(MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
98#define TPC1_QMAN_BASE_OFFSET	(TPC0_QMAN_BASE_OFFSET + \
99				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
100#define TPC2_QMAN_BASE_OFFSET	(TPC1_QMAN_BASE_OFFSET + \
101				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
102#define TPC3_QMAN_BASE_OFFSET	(TPC2_QMAN_BASE_OFFSET + \
103				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
104#define TPC4_QMAN_BASE_OFFSET	(TPC3_QMAN_BASE_OFFSET + \
105				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
106#define TPC5_QMAN_BASE_OFFSET	(TPC4_QMAN_BASE_OFFSET + \
107				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
108#define TPC6_QMAN_BASE_OFFSET	(TPC5_QMAN_BASE_OFFSET + \
109				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
110#define TPC7_QMAN_BASE_OFFSET	(TPC6_QMAN_BASE_OFFSET + \
111				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
112
113#define SRAM_DRIVER_RES_OFFSET	(TPC7_QMAN_BASE_OFFSET + \
114				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
115
116#if (SRAM_DRIVER_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
117#error "MME/TPC QMANs SRAM space exceeds limit"
118#endif
119
120#define SRAM_USER_BASE_OFFSET	GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
121
122/* Virtual address space */
123#define VA_HOST_SPACE_START	0x1000000000000ull	/* 256TB */
124#define VA_HOST_SPACE_END	0x3FF8000000000ull	/* 1PB - 1TB */
125#define VA_HOST_SPACE_SIZE	(VA_HOST_SPACE_END - \
126					VA_HOST_SPACE_START) /* 767TB */
127
128#define VA_DDR_SPACE_START	0x800000000ull		/* 32GB */
129#define VA_DDR_SPACE_END	0x2000000000ull		/* 128GB */
130#define VA_DDR_SPACE_SIZE	(VA_DDR_SPACE_END - \
131					VA_DDR_SPACE_START)	/* 128GB */
132
133#if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
134#error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
135#endif
136
137#define VA_CPU_ACCESSIBLE_MEM_ADDR	0x8000000000ull
138
139#define DMA_MAX_TRANSFER_SIZE	U32_MAX
140
141#define HW_CAP_PLL		0x00000001
142#define HW_CAP_DDR_0		0x00000002
143#define HW_CAP_DDR_1		0x00000004
144#define HW_CAP_MME		0x00000008
145#define HW_CAP_CPU		0x00000010
146#define HW_CAP_DMA		0x00000020
147#define HW_CAP_MSIX		0x00000040
148#define HW_CAP_CPU_Q		0x00000080
149#define HW_CAP_MMU		0x00000100
150#define HW_CAP_TPC_MBIST	0x00000200
151#define HW_CAP_GOLDEN		0x00000400
152#define HW_CAP_TPC		0x00000800
153
154struct goya_device {
155	/* TODO: remove hw_queues_lock after moving to scheduler code */
156	spinlock_t	hw_queues_lock;
157
158	u64		mme_clk;
159	u64		tpc_clk;
160	u64		ic_clk;
161
162	u64		ddr_bar_cur_addr;
163	u32		events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
164	u32		events_stat_aggregate[GOYA_ASYNC_EVENT_ID_SIZE];
165	u32		hw_cap_initialized;
166	u8		device_cpu_mmu_mappings_done;
167};
168
169int goya_get_fixed_properties(struct hl_device *hdev);
170int goya_mmu_init(struct hl_device *hdev);
171void goya_init_dma_qmans(struct hl_device *hdev);
172void goya_init_mme_qmans(struct hl_device *hdev);
173void goya_init_tpc_qmans(struct hl_device *hdev);
174int goya_init_cpu_queues(struct hl_device *hdev);
175void goya_init_security(struct hl_device *hdev);
176int goya_late_init(struct hl_device *hdev);
177void goya_late_fini(struct hl_device *hdev);
178
179void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
180void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
181void goya_update_eq_ci(struct hl_device *hdev, u32 val);
182void goya_restore_phase_topology(struct hl_device *hdev);
183int goya_context_switch(struct hl_device *hdev, u32 asid);
184
185int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
186			u8 i2c_addr, u8 i2c_reg, u32 *val);
187int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
188			u8 i2c_addr, u8 i2c_reg, u32 val);
189void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
190
191int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
192int goya_test_queues(struct hl_device *hdev);
193int goya_test_cpu_queue(struct hl_device *hdev);
194int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
195				u32 timeout, long *result);
196
197long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
198long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
199long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
200long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
201long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
202void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
203			long value);
204u64 goya_get_max_power(struct hl_device *hdev);
205void goya_set_max_power(struct hl_device *hdev, u64 value);
206
207void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
208void goya_add_device_attr(struct hl_device *hdev,
209			struct attribute_group *dev_attr_grp);
210int goya_cpucp_info_get(struct hl_device *hdev);
211int goya_debug_coresight(struct hl_device *hdev, void *data);
212void goya_halt_coresight(struct hl_device *hdev);
213
214int goya_suspend(struct hl_device *hdev);
215int goya_resume(struct hl_device *hdev);
216
217void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
218void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size);
219
220void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
221				u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
222				bool eb);
223int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
224void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
225				dma_addr_t *dma_handle,	u16 *queue_len);
226u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
227int goya_send_heartbeat(struct hl_device *hdev);
228void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
229					dma_addr_t *dma_handle);
230void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
231					void *vaddr);
232void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
233
234int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
235u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
236u64 goya_get_device_time(struct hl_device *hdev);
237
238#endif /* GOYAP_H_ */
239