1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Rui FENG <rui_feng@realsil.com.cn> 8 * Wei WANG <wei_wang@realsil.com.cn> 9 */ 10#ifndef RTS5261_H 11#define RTS5261_H 12 13/*New add*/ 14#define rts5261_vendor_setting_valid(reg) ((reg) & 0x010000) 15#define rts5261_reg_to_aspm(reg) (((reg) >> 28) ^ 0x03) 16#define rts5261_reg_check_reverse_socket(reg) ((reg) & 0x04) 17#define rts5261_reg_to_card_drive_sel(reg) ((((reg) >> 6) & 0x01) << 6) 18#define rts5261_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) ^ 0x03) 19#define rts5261_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) ^ 0x03) 20 21 22#define RTS5261_AUTOLOAD_CFG0 0xFF7B 23#define RTS5261_AUTOLOAD_CFG1 0xFF7C 24#define RTS5261_AUTOLOAD_CFG2 0xFF7D 25#define RTS5261_AUTOLOAD_CFG3 0xFF7E 26#define RTS5261_AUTOLOAD_CFG4 0xFF7F 27#define RTS5261_FORCE_PRSNT_LOW (1 << 6) 28#define RTS5261_AUX_CLK_16M_EN (1 << 5) 29 30#define RTS5261_REG_VREF 0xFE97 31#define RTS5261_PWD_SUSPND_EN (1 << 4) 32 33#define RTS5261_PAD_H3L1 0xFF79 34#define PAD_GPIO_H3L1 (1 << 3) 35 36/* SSC_CTL2 0xFC12 */ 37#define RTS5261_SSC_DEPTH_MASK 0x07 38#define RTS5261_SSC_DEPTH_DISALBE 0x00 39#define RTS5261_SSC_DEPTH_8M 0x01 40#define RTS5261_SSC_DEPTH_4M 0x02 41#define RTS5261_SSC_DEPTH_2M 0x03 42#define RTS5261_SSC_DEPTH_1M 0x04 43#define RTS5261_SSC_DEPTH_512K 0x05 44#define RTS5261_SSC_DEPTH_256K 0x06 45#define RTS5261_SSC_DEPTH_128K 0x07 46 47/* efuse control register*/ 48#define RTS5261_EFUSE_CTL 0xFC30 49#define RTS5261_EFUSE_ENABLE 0x80 50/* EFUSE_MODE: 0=READ 1=PROGRAM */ 51#define RTS5261_EFUSE_MODE_MASK 0x40 52#define RTS5261_EFUSE_PROGRAM 0x40 53 54#define RTS5261_EFUSE_ADDR 0xFC31 55#define RTS5261_EFUSE_ADDR_MASK 0x3F 56 57#define RTS5261_EFUSE_WRITE_DATA 0xFC32 58#define RTS5261_EFUSE_READ_DATA 0xFC34 59 60/* DMACTL 0xFE2C */ 61#define RTS5261_DMA_PACK_SIZE_MASK 0xF0 62 63/* FW config info register */ 64#define RTS5261_FW_CFG_INFO0 0xFF50 65#define RTS5261_FW_EXPRESS_TEST_MASK (0x01<<0) 66#define RTS5261_FW_EA_MODE_MASK (0x01<<5) 67 68/* FW config register */ 69#define RTS5261_FW_CFG0 0xFF54 70#define RTS5261_FW_ENTER_EXPRESS (0x01<<0) 71 72#define RTS5261_FW_CFG1 0xFF55 73#define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01<<7) 74#define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01<<6) 75#define RTS5261_FAKE_MCU_CLOCK_GATING (0x01<<5) 76/*MCU_bus_mode_sel: 0=real 8051 1=fake mcu*/ 77#define RTS5261_MCU_BUS_SEL_MASK (0x01<<4) 78/*MCU_clock_sel:VerA 00=aux16M 01=aux400K 1x=REFCLK100M*/ 79/*MCU_clock_sel:VerB 00=aux400K 01=aux16M 10=REFCLK100M*/ 80#define RTS5261_MCU_CLOCK_SEL_MASK (0x03<<2) 81#define RTS5261_MCU_CLOCK_SEL_16M (0x01<<2) 82#define RTS5261_MCU_CLOCK_GATING (0x01<<1) 83#define RTS5261_DRIVER_ENABLE_FW (0x01<<0) 84 85/* FW status register */ 86#define RTS5261_FW_STATUS 0xFF56 87#define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7) 88 89/* FW control register */ 90#define RTS5261_FW_CTL 0xFF5F 91#define RTS5261_INFORM_RTD3_COLD (0x01<<5) 92 93#define RTS5261_REG_FPDCTL 0xFF60 94 95#define RTS5261_REG_LDO12_CFG 0xFF6E 96#define RTS5261_LDO12_VO_TUNE_MASK (0x07<<1) 97#define RTS5261_LDO12_115 (0x03<<1) 98#define RTS5261_LDO12_120 (0x04<<1) 99#define RTS5261_LDO12_125 (0x05<<1) 100#define RTS5261_LDO12_130 (0x06<<1) 101#define RTS5261_LDO12_135 (0x07<<1) 102 103/* LDO control register */ 104#define RTS5261_CARD_PWR_CTL 0xFD50 105#define RTS5261_SD_CLK_ISO (0x01<<7) 106#define RTS5261_PAD_SD_DAT_FW_CTRL (0x01<<6) 107#define RTS5261_PUPDC (0x01<<5) 108#define RTS5261_SD_CMD_ISO (0x01<<4) 109#define RTS5261_SD_DAT_ISO_MASK (0x0F<<0) 110 111#define RTS5261_LDO1233318_POW_CTL 0xFF70 112#define RTS5261_LDO3318_POWERON (0x01<<3) 113#define RTS5261_LDO3_POWERON (0x01<<2) 114#define RTS5261_LDO2_POWERON (0x01<<1) 115#define RTS5261_LDO1_POWERON (0x01<<0) 116#define RTS5261_LDO_POWERON_MASK (0x0F<<0) 117 118#define RTS5261_DV3318_CFG 0xFF71 119#define RTS5261_DV3318_TUNE_MASK (0x07<<4) 120#define RTS5261_DV3318_18 (0x02<<4) 121#define RTS5261_DV3318_19 (0x04<<4) 122#define RTS5261_DV3318_33 (0x07<<4) 123 124#define RTS5261_LDO1_CFG0 0xFF72 125#define RTS5261_LDO1_OCP_THD_MASK (0x07<<5) 126#define RTS5261_LDO1_OCP_EN (0x01<<4) 127#define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03<<2) 128#define RTS5261_LDO1_OCP_LMT_EN (0x01<<1) 129 130/* CRD6603-433 190319 request changed */ 131#define RTS5261_LDO1_OCP_THD_740 (0x00<<5) 132#define RTS5261_LDO1_OCP_THD_800 (0x01<<5) 133#define RTS5261_LDO1_OCP_THD_860 (0x02<<5) 134#define RTS5261_LDO1_OCP_THD_920 (0x03<<5) 135#define RTS5261_LDO1_OCP_THD_980 (0x04<<5) 136#define RTS5261_LDO1_OCP_THD_1040 (0x05<<5) 137#define RTS5261_LDO1_OCP_THD_1100 (0x06<<5) 138#define RTS5261_LDO1_OCP_THD_1160 (0x07<<5) 139 140#define RTS5261_LDO1_LMT_THD_450 (0x00<<2) 141#define RTS5261_LDO1_LMT_THD_1000 (0x01<<2) 142#define RTS5261_LDO1_LMT_THD_1500 (0x02<<2) 143#define RTS5261_LDO1_LMT_THD_2000 (0x03<<2) 144 145#define RTS5261_LDO1_CFG1 0xFF73 146#define RTS5261_LDO1_TUNE_MASK (0x07<<1) 147#define RTS5261_LDO1_18 (0x05<<1) 148#define RTS5261_LDO1_33 (0x07<<1) 149#define RTS5261_LDO1_PWD_MASK (0x01<<0) 150 151#define RTS5261_LDO2_CFG0 0xFF74 152#define RTS5261_LDO2_OCP_THD_MASK (0x07<<5) 153#define RTS5261_LDO2_OCP_EN (0x01<<4) 154#define RTS5261_LDO2_OCP_LMT_THD_MASK (0x03<<2) 155#define RTS5261_LDO2_OCP_LMT_EN (0x01<<1) 156 157#define RTS5261_LDO2_OCP_THD_620 (0x00<<5) 158#define RTS5261_LDO2_OCP_THD_650 (0x01<<5) 159#define RTS5261_LDO2_OCP_THD_680 (0x02<<5) 160#define RTS5261_LDO2_OCP_THD_720 (0x03<<5) 161#define RTS5261_LDO2_OCP_THD_750 (0x04<<5) 162#define RTS5261_LDO2_OCP_THD_780 (0x05<<5) 163#define RTS5261_LDO2_OCP_THD_810 (0x06<<5) 164#define RTS5261_LDO2_OCP_THD_840 (0x07<<5) 165 166#define RTS5261_LDO2_CFG1 0xFF75 167#define RTS5261_LDO2_TUNE_MASK (0x07<<1) 168#define RTS5261_LDO2_18 (0x05<<1) 169#define RTS5261_LDO2_33 (0x07<<1) 170#define RTS5261_LDO2_PWD_MASK (0x01<<0) 171 172#define RTS5261_LDO3_CFG0 0xFF76 173#define RTS5261_LDO3_OCP_THD_MASK (0x07<<5) 174#define RTS5261_LDO3_OCP_EN (0x01<<4) 175#define RTS5261_LDO3_OCP_LMT_THD_MASK (0x03<<2) 176#define RTS5261_LDO3_OCP_LMT_EN (0x01<<1) 177 178#define RTS5261_LDO3_OCP_THD_620 (0x00<<5) 179#define RTS5261_LDO3_OCP_THD_650 (0x01<<5) 180#define RTS5261_LDO3_OCP_THD_680 (0x02<<5) 181#define RTS5261_LDO3_OCP_THD_720 (0x03<<5) 182#define RTS5261_LDO3_OCP_THD_750 (0x04<<5) 183#define RTS5261_LDO3_OCP_THD_780 (0x05<<5) 184#define RTS5261_LDO3_OCP_THD_810 (0x06<<5) 185#define RTS5261_LDO3_OCP_THD_840 (0x07<<5) 186 187#define RTS5261_LDO3_CFG1 0xFF77 188#define RTS5261_LDO3_TUNE_MASK (0x07<<1) 189#define RTS5261_LDO3_18 (0x05<<1) 190#define RTS5261_LDO3_33 (0x07<<1) 191#define RTS5261_LDO3_PWD_MASK (0x01<<0) 192 193#define RTS5261_REG_PME_FORCE_CTL 0xFF78 194#define FORCE_PM_CONTROL 0x20 195#define FORCE_PM_VALUE 0x10 196#define REG_EFUSE_BYPASS 0x08 197#define REG_EFUSE_POR 0x04 198#define REG_EFUSE_POWER_MASK 0x03 199#define REG_EFUSE_POWERON 0x03 200#define REG_EFUSE_POWEROFF 0x00 201 202 203/* Single LUN, support SD/SD EXPRESS */ 204#define DEFAULT_SINGLE 0 205#define SD_LUN 1 206#define SD_EXPRESS_LUN 2 207 208/* For Change_FPGA_SSCClock Function */ 209#define MULTIPLY_BY_1 0x00 210#define MULTIPLY_BY_2 0x01 211#define MULTIPLY_BY_3 0x02 212#define MULTIPLY_BY_4 0x03 213#define MULTIPLY_BY_5 0x04 214#define MULTIPLY_BY_6 0x05 215#define MULTIPLY_BY_7 0x06 216#define MULTIPLY_BY_8 0x07 217#define MULTIPLY_BY_9 0x08 218#define MULTIPLY_BY_10 0x09 219 220#define DIVIDE_BY_2 0x01 221#define DIVIDE_BY_3 0x02 222#define DIVIDE_BY_4 0x03 223#define DIVIDE_BY_5 0x04 224#define DIVIDE_BY_6 0x05 225#define DIVIDE_BY_7 0x06 226#define DIVIDE_BY_8 0x07 227#define DIVIDE_BY_9 0x08 228#define DIVIDE_BY_10 0x09 229 230int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 231 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 232 233#endif /* RTS5261_H */ 234