1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
4 */
5
6#include <linux/of.h>
7#include <linux/mm.h>
8
9#include <dt-bindings/memory/tegra30-mc.h>
10
11#include "mc.h"
12
13static const unsigned long tegra30_mc_emem_regs[] = {
14	MC_EMEM_ARB_CFG,
15	MC_EMEM_ARB_OUTSTANDING_REQ,
16	MC_EMEM_ARB_TIMING_RCD,
17	MC_EMEM_ARB_TIMING_RP,
18	MC_EMEM_ARB_TIMING_RC,
19	MC_EMEM_ARB_TIMING_RAS,
20	MC_EMEM_ARB_TIMING_FAW,
21	MC_EMEM_ARB_TIMING_RRD,
22	MC_EMEM_ARB_TIMING_RAP2PRE,
23	MC_EMEM_ARB_TIMING_WAP2PRE,
24	MC_EMEM_ARB_TIMING_R2R,
25	MC_EMEM_ARB_TIMING_W2W,
26	MC_EMEM_ARB_TIMING_R2W,
27	MC_EMEM_ARB_TIMING_W2R,
28	MC_EMEM_ARB_DA_TURNS,
29	MC_EMEM_ARB_DA_COVERS,
30	MC_EMEM_ARB_MISC0,
31	MC_EMEM_ARB_RING1_THROTTLE,
32};
33
34static const struct tegra_mc_client tegra30_mc_clients[] = {
35	{
36		.id = 0x00,
37		.name = "ptcr",
38		.swgroup = TEGRA_SWGROUP_PTC,
39	}, {
40		.id = 0x01,
41		.name = "display0a",
42		.swgroup = TEGRA_SWGROUP_DC,
43		.smmu = {
44			.reg = 0x228,
45			.bit = 1,
46		},
47		.la = {
48			.reg = 0x2e8,
49			.shift = 0,
50			.mask = 0xff,
51			.def = 0x4e,
52		},
53	}, {
54		.id = 0x02,
55		.name = "display0ab",
56		.swgroup = TEGRA_SWGROUP_DCB,
57		.smmu = {
58			.reg = 0x228,
59			.bit = 2,
60		},
61		.la = {
62			.reg = 0x2f4,
63			.shift = 0,
64			.mask = 0xff,
65			.def = 0x4e,
66		},
67	}, {
68		.id = 0x03,
69		.name = "display0b",
70		.swgroup = TEGRA_SWGROUP_DC,
71		.smmu = {
72			.reg = 0x228,
73			.bit = 3,
74		},
75		.la = {
76			.reg = 0x2e8,
77			.shift = 16,
78			.mask = 0xff,
79			.def = 0x4e,
80		},
81	}, {
82		.id = 0x04,
83		.name = "display0bb",
84		.swgroup = TEGRA_SWGROUP_DCB,
85		.smmu = {
86			.reg = 0x228,
87			.bit = 4,
88		},
89		.la = {
90			.reg = 0x2f4,
91			.shift = 16,
92			.mask = 0xff,
93			.def = 0x4e,
94		},
95	}, {
96		.id = 0x05,
97		.name = "display0c",
98		.swgroup = TEGRA_SWGROUP_DC,
99		.smmu = {
100			.reg = 0x228,
101			.bit = 5,
102		},
103		.la = {
104			.reg = 0x2ec,
105			.shift = 0,
106			.mask = 0xff,
107			.def = 0x4e,
108		},
109	}, {
110		.id = 0x06,
111		.name = "display0cb",
112		.swgroup = TEGRA_SWGROUP_DCB,
113		.smmu = {
114			.reg = 0x228,
115			.bit = 6,
116		},
117		.la = {
118			.reg = 0x2f8,
119			.shift = 0,
120			.mask = 0xff,
121			.def = 0x4e,
122		},
123	}, {
124		.id = 0x07,
125		.name = "display1b",
126		.swgroup = TEGRA_SWGROUP_DC,
127		.smmu = {
128			.reg = 0x228,
129			.bit = 7,
130		},
131		.la = {
132			.reg = 0x2ec,
133			.shift = 16,
134			.mask = 0xff,
135			.def = 0x4e,
136		},
137	}, {
138		.id = 0x08,
139		.name = "display1bb",
140		.swgroup = TEGRA_SWGROUP_DCB,
141		.smmu = {
142			.reg = 0x228,
143			.bit = 8,
144		},
145		.la = {
146			.reg = 0x2f8,
147			.shift = 16,
148			.mask = 0xff,
149			.def = 0x4e,
150		},
151	}, {
152		.id = 0x09,
153		.name = "eppup",
154		.swgroup = TEGRA_SWGROUP_EPP,
155		.smmu = {
156			.reg = 0x228,
157			.bit = 9,
158		},
159		.la = {
160			.reg = 0x300,
161			.shift = 0,
162			.mask = 0xff,
163			.def = 0x17,
164		},
165	}, {
166		.id = 0x0a,
167		.name = "g2pr",
168		.swgroup = TEGRA_SWGROUP_G2,
169		.smmu = {
170			.reg = 0x228,
171			.bit = 10,
172		},
173		.la = {
174			.reg = 0x308,
175			.shift = 0,
176			.mask = 0xff,
177			.def = 0x09,
178		},
179	}, {
180		.id = 0x0b,
181		.name = "g2sr",
182		.swgroup = TEGRA_SWGROUP_G2,
183		.smmu = {
184			.reg = 0x228,
185			.bit = 11,
186		},
187		.la = {
188			.reg = 0x308,
189			.shift = 16,
190			.mask = 0xff,
191			.def = 0x09,
192		},
193	}, {
194		.id = 0x0c,
195		.name = "mpeunifbr",
196		.swgroup = TEGRA_SWGROUP_MPE,
197		.smmu = {
198			.reg = 0x228,
199			.bit = 12,
200		},
201		.la = {
202			.reg = 0x328,
203			.shift = 0,
204			.mask = 0xff,
205			.def = 0x50,
206		},
207	}, {
208		.id = 0x0d,
209		.name = "viruv",
210		.swgroup = TEGRA_SWGROUP_VI,
211		.smmu = {
212			.reg = 0x228,
213			.bit = 13,
214		},
215		.la = {
216			.reg = 0x364,
217			.shift = 0,
218			.mask = 0xff,
219			.def = 0x2c,
220		},
221	}, {
222		.id = 0x0e,
223		.name = "afir",
224		.swgroup = TEGRA_SWGROUP_AFI,
225		.smmu = {
226			.reg = 0x228,
227			.bit = 14,
228		},
229		.la = {
230			.reg = 0x2e0,
231			.shift = 0,
232			.mask = 0xff,
233			.def = 0x10,
234		},
235	}, {
236		.id = 0x0f,
237		.name = "avpcarm7r",
238		.swgroup = TEGRA_SWGROUP_AVPC,
239		.smmu = {
240			.reg = 0x228,
241			.bit = 15,
242		},
243		.la = {
244			.reg = 0x2e4,
245			.shift = 0,
246			.mask = 0xff,
247			.def = 0x04,
248		},
249	}, {
250		.id = 0x10,
251		.name = "displayhc",
252		.swgroup = TEGRA_SWGROUP_DC,
253		.smmu = {
254			.reg = 0x228,
255			.bit = 16,
256		},
257		.la = {
258			.reg = 0x2f0,
259			.shift = 0,
260			.mask = 0xff,
261			.def = 0xff,
262		},
263	}, {
264		.id = 0x11,
265		.name = "displayhcb",
266		.swgroup = TEGRA_SWGROUP_DCB,
267		.smmu = {
268			.reg = 0x228,
269			.bit = 17,
270		},
271		.la = {
272			.reg = 0x2fc,
273			.shift = 0,
274			.mask = 0xff,
275			.def = 0xff,
276		},
277	}, {
278		.id = 0x12,
279		.name = "fdcdrd",
280		.swgroup = TEGRA_SWGROUP_NV,
281		.smmu = {
282			.reg = 0x228,
283			.bit = 18,
284		},
285		.la = {
286			.reg = 0x334,
287			.shift = 0,
288			.mask = 0xff,
289			.def = 0x0a,
290		},
291	}, {
292		.id = 0x13,
293		.name = "fdcdrd2",
294		.swgroup = TEGRA_SWGROUP_NV2,
295		.smmu = {
296			.reg = 0x228,
297			.bit = 19,
298		},
299		.la = {
300			.reg = 0x33c,
301			.shift = 0,
302			.mask = 0xff,
303			.def = 0x0a,
304		},
305	}, {
306		.id = 0x14,
307		.name = "g2dr",
308		.swgroup = TEGRA_SWGROUP_G2,
309		.smmu = {
310			.reg = 0x228,
311			.bit = 20,
312		},
313		.la = {
314			.reg = 0x30c,
315			.shift = 0,
316			.mask = 0xff,
317			.def = 0x0a,
318		},
319	}, {
320		.id = 0x15,
321		.name = "hdar",
322		.swgroup = TEGRA_SWGROUP_HDA,
323		.smmu = {
324			.reg = 0x228,
325			.bit = 21,
326		},
327		.la = {
328			.reg = 0x318,
329			.shift = 0,
330			.mask = 0xff,
331			.def = 0xff,
332		},
333	}, {
334		.id = 0x16,
335		.name = "host1xdmar",
336		.swgroup = TEGRA_SWGROUP_HC,
337		.smmu = {
338			.reg = 0x228,
339			.bit = 22,
340		},
341		.la = {
342			.reg = 0x310,
343			.shift = 0,
344			.mask = 0xff,
345			.def = 0x05,
346		},
347	}, {
348		.id = 0x17,
349		.name = "host1xr",
350		.swgroup = TEGRA_SWGROUP_HC,
351		.smmu = {
352			.reg = 0x228,
353			.bit = 23,
354		},
355		.la = {
356			.reg = 0x310,
357			.shift = 16,
358			.mask = 0xff,
359			.def = 0x50,
360		},
361	}, {
362		.id = 0x18,
363		.name = "idxsrd",
364		.swgroup = TEGRA_SWGROUP_NV,
365		.smmu = {
366			.reg = 0x228,
367			.bit = 24,
368		},
369		.la = {
370			.reg = 0x334,
371			.shift = 16,
372			.mask = 0xff,
373			.def = 0x13,
374		},
375	}, {
376		.id = 0x19,
377		.name = "idxsrd2",
378		.swgroup = TEGRA_SWGROUP_NV2,
379		.smmu = {
380			.reg = 0x228,
381			.bit = 25,
382		},
383		.la = {
384			.reg = 0x33c,
385			.shift = 16,
386			.mask = 0xff,
387			.def = 0x13,
388		},
389	}, {
390		.id = 0x1a,
391		.name = "mpe_ipred",
392		.swgroup = TEGRA_SWGROUP_MPE,
393		.smmu = {
394			.reg = 0x228,
395			.bit = 26,
396		},
397		.la = {
398			.reg = 0x328,
399			.shift = 16,
400			.mask = 0xff,
401			.def = 0x80,
402		},
403	}, {
404		.id = 0x1b,
405		.name = "mpeamemrd",
406		.swgroup = TEGRA_SWGROUP_MPE,
407		.smmu = {
408			.reg = 0x228,
409			.bit = 27,
410		},
411		.la = {
412			.reg = 0x32c,
413			.shift = 0,
414			.mask = 0xff,
415			.def = 0x42,
416		},
417	}, {
418		.id = 0x1c,
419		.name = "mpecsrd",
420		.swgroup = TEGRA_SWGROUP_MPE,
421		.smmu = {
422			.reg = 0x228,
423			.bit = 28,
424		},
425		.la = {
426			.reg = 0x32c,
427			.shift = 16,
428			.mask = 0xff,
429			.def = 0xff,
430		},
431	}, {
432		.id = 0x1d,
433		.name = "ppcsahbdmar",
434		.swgroup = TEGRA_SWGROUP_PPCS,
435		.smmu = {
436			.reg = 0x228,
437			.bit = 29,
438		},
439		.la = {
440			.reg = 0x344,
441			.shift = 0,
442			.mask = 0xff,
443			.def = 0x10,
444		},
445	}, {
446		.id = 0x1e,
447		.name = "ppcsahbslvr",
448		.swgroup = TEGRA_SWGROUP_PPCS,
449		.smmu = {
450			.reg = 0x228,
451			.bit = 30,
452		},
453		.la = {
454			.reg = 0x344,
455			.shift = 16,
456			.mask = 0xff,
457			.def = 0x12,
458		},
459	}, {
460		.id = 0x1f,
461		.name = "satar",
462		.swgroup = TEGRA_SWGROUP_SATA,
463		.smmu = {
464			.reg = 0x228,
465			.bit = 31,
466		},
467		.la = {
468			.reg = 0x350,
469			.shift = 0,
470			.mask = 0xff,
471			.def = 0x33,
472		},
473	}, {
474		.id = 0x20,
475		.name = "texsrd",
476		.swgroup = TEGRA_SWGROUP_NV,
477		.smmu = {
478			.reg = 0x22c,
479			.bit = 0,
480		},
481		.la = {
482			.reg = 0x338,
483			.shift = 0,
484			.mask = 0xff,
485			.def = 0x13,
486		},
487	}, {
488		.id = 0x21,
489		.name = "texsrd2",
490		.swgroup = TEGRA_SWGROUP_NV2,
491		.smmu = {
492			.reg = 0x22c,
493			.bit = 1,
494		},
495		.la = {
496			.reg = 0x340,
497			.shift = 0,
498			.mask = 0xff,
499			.def = 0x13,
500		},
501	}, {
502		.id = 0x22,
503		.name = "vdebsevr",
504		.swgroup = TEGRA_SWGROUP_VDE,
505		.smmu = {
506			.reg = 0x22c,
507			.bit = 2,
508		},
509		.la = {
510			.reg = 0x354,
511			.shift = 0,
512			.mask = 0xff,
513			.def = 0xff,
514		},
515	}, {
516		.id = 0x23,
517		.name = "vdember",
518		.swgroup = TEGRA_SWGROUP_VDE,
519		.smmu = {
520			.reg = 0x22c,
521			.bit = 3,
522		},
523		.la = {
524			.reg = 0x354,
525			.shift = 16,
526			.mask = 0xff,
527			.def = 0xd0,
528		},
529	}, {
530		.id = 0x24,
531		.name = "vdemcer",
532		.swgroup = TEGRA_SWGROUP_VDE,
533		.smmu = {
534			.reg = 0x22c,
535			.bit = 4,
536		},
537		.la = {
538			.reg = 0x358,
539			.shift = 0,
540			.mask = 0xff,
541			.def = 0x2a,
542		},
543	}, {
544		.id = 0x25,
545		.name = "vdetper",
546		.swgroup = TEGRA_SWGROUP_VDE,
547		.smmu = {
548			.reg = 0x22c,
549			.bit = 5,
550		},
551		.la = {
552			.reg = 0x358,
553			.shift = 16,
554			.mask = 0xff,
555			.def = 0x74,
556		},
557	}, {
558		.id = 0x26,
559		.name = "mpcorelpr",
560		.swgroup = TEGRA_SWGROUP_MPCORELP,
561		.la = {
562			.reg = 0x324,
563			.shift = 0,
564			.mask = 0xff,
565			.def = 0x04,
566		},
567	}, {
568		.id = 0x27,
569		.name = "mpcorer",
570		.swgroup = TEGRA_SWGROUP_MPCORE,
571		.la = {
572			.reg = 0x320,
573			.shift = 0,
574			.mask = 0xff,
575			.def = 0x04,
576		},
577	}, {
578		.id = 0x28,
579		.name = "eppu",
580		.swgroup = TEGRA_SWGROUP_EPP,
581		.smmu = {
582			.reg = 0x22c,
583			.bit = 8,
584		},
585		.la = {
586			.reg = 0x300,
587			.shift = 16,
588			.mask = 0xff,
589			.def = 0x6c,
590		},
591	}, {
592		.id = 0x29,
593		.name = "eppv",
594		.swgroup = TEGRA_SWGROUP_EPP,
595		.smmu = {
596			.reg = 0x22c,
597			.bit = 9,
598		},
599		.la = {
600			.reg = 0x304,
601			.shift = 0,
602			.mask = 0xff,
603			.def = 0x6c,
604		},
605	}, {
606		.id = 0x2a,
607		.name = "eppy",
608		.swgroup = TEGRA_SWGROUP_EPP,
609		.smmu = {
610			.reg = 0x22c,
611			.bit = 10,
612		},
613		.la = {
614			.reg = 0x304,
615			.shift = 16,
616			.mask = 0xff,
617			.def = 0x6c,
618		},
619	}, {
620		.id = 0x2b,
621		.name = "mpeunifbw",
622		.swgroup = TEGRA_SWGROUP_MPE,
623		.smmu = {
624			.reg = 0x22c,
625			.bit = 11,
626		},
627		.la = {
628			.reg = 0x330,
629			.shift = 0,
630			.mask = 0xff,
631			.def = 0x13,
632		},
633	}, {
634		.id = 0x2c,
635		.name = "viwsb",
636		.swgroup = TEGRA_SWGROUP_VI,
637		.smmu = {
638			.reg = 0x22c,
639			.bit = 12,
640		},
641		.la = {
642			.reg = 0x364,
643			.shift = 16,
644			.mask = 0xff,
645			.def = 0x12,
646		},
647	}, {
648		.id = 0x2d,
649		.name = "viwu",
650		.swgroup = TEGRA_SWGROUP_VI,
651		.smmu = {
652			.reg = 0x22c,
653			.bit = 13,
654		},
655		.la = {
656			.reg = 0x368,
657			.shift = 0,
658			.mask = 0xff,
659			.def = 0xb2,
660		},
661	}, {
662		.id = 0x2e,
663		.name = "viwv",
664		.swgroup = TEGRA_SWGROUP_VI,
665		.smmu = {
666			.reg = 0x22c,
667			.bit = 14,
668		},
669		.la = {
670			.reg = 0x368,
671			.shift = 16,
672			.mask = 0xff,
673			.def = 0xb2,
674		},
675	}, {
676		.id = 0x2f,
677		.name = "viwy",
678		.swgroup = TEGRA_SWGROUP_VI,
679		.smmu = {
680			.reg = 0x22c,
681			.bit = 15,
682		},
683		.la = {
684			.reg = 0x36c,
685			.shift = 0,
686			.mask = 0xff,
687			.def = 0x12,
688		},
689	}, {
690		.id = 0x30,
691		.name = "g2dw",
692		.swgroup = TEGRA_SWGROUP_G2,
693		.smmu = {
694			.reg = 0x22c,
695			.bit = 16,
696		},
697		.la = {
698			.reg = 0x30c,
699			.shift = 16,
700			.mask = 0xff,
701			.def = 0x9,
702		},
703	}, {
704		.id = 0x31,
705		.name = "afiw",
706		.swgroup = TEGRA_SWGROUP_AFI,
707		.smmu = {
708			.reg = 0x22c,
709			.bit = 17,
710		},
711		.la = {
712			.reg = 0x2e0,
713			.shift = 16,
714			.mask = 0xff,
715			.def = 0x0c,
716		},
717	}, {
718		.id = 0x32,
719		.name = "avpcarm7w",
720		.swgroup = TEGRA_SWGROUP_AVPC,
721		.smmu = {
722			.reg = 0x22c,
723			.bit = 18,
724		},
725		.la = {
726			.reg = 0x2e4,
727			.shift = 16,
728			.mask = 0xff,
729			.def = 0x0e,
730		},
731	}, {
732		.id = 0x33,
733		.name = "fdcdwr",
734		.swgroup = TEGRA_SWGROUP_NV,
735		.smmu = {
736			.reg = 0x22c,
737			.bit = 19,
738		},
739		.la = {
740			.reg = 0x338,
741			.shift = 16,
742			.mask = 0xff,
743			.def = 0x0a,
744		},
745	}, {
746		.id = 0x34,
747		.name = "fdcdwr2",
748		.swgroup = TEGRA_SWGROUP_NV2,
749		.smmu = {
750			.reg = 0x22c,
751			.bit = 20,
752		},
753		.la = {
754			.reg = 0x340,
755			.shift = 16,
756			.mask = 0xff,
757			.def = 0x0a,
758		},
759	}, {
760		.id = 0x35,
761		.name = "hdaw",
762		.swgroup = TEGRA_SWGROUP_HDA,
763		.smmu = {
764			.reg = 0x22c,
765			.bit = 21,
766		},
767		.la = {
768			.reg = 0x318,
769			.shift = 16,
770			.mask = 0xff,
771			.def = 0xff,
772		},
773	}, {
774		.id = 0x36,
775		.name = "host1xw",
776		.swgroup = TEGRA_SWGROUP_HC,
777		.smmu = {
778			.reg = 0x22c,
779			.bit = 22,
780		},
781		.la = {
782			.reg = 0x314,
783			.shift = 0,
784			.mask = 0xff,
785			.def = 0x10,
786		},
787	}, {
788		.id = 0x37,
789		.name = "ispw",
790		.swgroup = TEGRA_SWGROUP_ISP,
791		.smmu = {
792			.reg = 0x22c,
793			.bit = 23,
794		},
795		.la = {
796			.reg = 0x31c,
797			.shift = 0,
798			.mask = 0xff,
799			.def = 0xff,
800		},
801	}, {
802		.id = 0x38,
803		.name = "mpcorelpw",
804		.swgroup = TEGRA_SWGROUP_MPCORELP,
805		.la = {
806			.reg = 0x324,
807			.shift = 16,
808			.mask = 0xff,
809			.def = 0x0e,
810		},
811	}, {
812		.id = 0x39,
813		.name = "mpcorew",
814		.swgroup = TEGRA_SWGROUP_MPCORE,
815		.la = {
816			.reg = 0x320,
817			.shift = 16,
818			.mask = 0xff,
819			.def = 0x0e,
820		},
821	}, {
822		.id = 0x3a,
823		.name = "mpecswr",
824		.swgroup = TEGRA_SWGROUP_MPE,
825		.smmu = {
826			.reg = 0x22c,
827			.bit = 26,
828		},
829		.la = {
830			.reg = 0x330,
831			.shift = 16,
832			.mask = 0xff,
833			.def = 0xff,
834		},
835	}, {
836		.id = 0x3b,
837		.name = "ppcsahbdmaw",
838		.swgroup = TEGRA_SWGROUP_PPCS,
839		.smmu = {
840			.reg = 0x22c,
841			.bit = 27,
842		},
843		.la = {
844			.reg = 0x348,
845			.shift = 0,
846			.mask = 0xff,
847			.def = 0x10,
848		},
849	}, {
850		.id = 0x3c,
851		.name = "ppcsahbslvw",
852		.swgroup = TEGRA_SWGROUP_PPCS,
853		.smmu = {
854			.reg = 0x22c,
855			.bit = 28,
856		},
857		.la = {
858			.reg = 0x348,
859			.shift = 16,
860			.mask = 0xff,
861			.def = 0x06,
862		},
863	}, {
864		.id = 0x3d,
865		.name = "sataw",
866		.swgroup = TEGRA_SWGROUP_SATA,
867		.smmu = {
868			.reg = 0x22c,
869			.bit = 29,
870		},
871		.la = {
872			.reg = 0x350,
873			.shift = 16,
874			.mask = 0xff,
875			.def = 0x33,
876		},
877	}, {
878		.id = 0x3e,
879		.name = "vdebsevw",
880		.swgroup = TEGRA_SWGROUP_VDE,
881		.smmu = {
882			.reg = 0x22c,
883			.bit = 30,
884		},
885		.la = {
886			.reg = 0x35c,
887			.shift = 0,
888			.mask = 0xff,
889			.def = 0xff,
890		},
891	}, {
892		.id = 0x3f,
893		.name = "vdedbgw",
894		.swgroup = TEGRA_SWGROUP_VDE,
895		.smmu = {
896			.reg = 0x22c,
897			.bit = 31,
898		},
899		.la = {
900			.reg = 0x35c,
901			.shift = 16,
902			.mask = 0xff,
903			.def = 0xff,
904		},
905	}, {
906		.id = 0x40,
907		.name = "vdembew",
908		.swgroup = TEGRA_SWGROUP_VDE,
909		.smmu = {
910			.reg = 0x230,
911			.bit = 0,
912		},
913		.la = {
914			.reg = 0x360,
915			.shift = 0,
916			.mask = 0xff,
917			.def = 0x42,
918		},
919	}, {
920		.id = 0x41,
921		.name = "vdetpmw",
922		.swgroup = TEGRA_SWGROUP_VDE,
923		.smmu = {
924			.reg = 0x230,
925			.bit = 1,
926		},
927		.la = {
928			.reg = 0x360,
929			.shift = 16,
930			.mask = 0xff,
931			.def = 0x2a,
932		},
933	},
934};
935
936static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
937	{ .name = "dc",   .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },
938	{ .name = "dcb",  .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },
939	{ .name = "epp",  .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },
940	{ .name = "g2",   .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },
941	{ .name = "mpe",  .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },
942	{ .name = "vi",   .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },
943	{ .name = "afi",  .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },
944	{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
945	{ .name = "nv",   .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },
946	{ .name = "nv2",  .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },
947	{ .name = "hda",  .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },
948	{ .name = "hc",   .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },
949	{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
950	{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
951	{ .name = "vde",  .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },
952	{ .name = "isp",  .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },
953};
954
955static const unsigned int tegra30_group_drm[] = {
956	TEGRA_SWGROUP_DC,
957	TEGRA_SWGROUP_DCB,
958	TEGRA_SWGROUP_G2,
959	TEGRA_SWGROUP_NV,
960	TEGRA_SWGROUP_NV2,
961};
962
963static const struct tegra_smmu_group_soc tegra30_groups[] = {
964	{
965		.name = "drm",
966		.swgroups = tegra30_group_drm,
967		.num_swgroups = ARRAY_SIZE(tegra30_group_drm),
968	},
969};
970
971static const struct tegra_smmu_soc tegra30_smmu_soc = {
972	.clients = tegra30_mc_clients,
973	.num_clients = ARRAY_SIZE(tegra30_mc_clients),
974	.swgroups = tegra30_swgroups,
975	.num_swgroups = ARRAY_SIZE(tegra30_swgroups),
976	.groups = tegra30_groups,
977	.num_groups = ARRAY_SIZE(tegra30_groups),
978	.supports_round_robin_arbitration = false,
979	.supports_request_limit = false,
980	.num_tlb_lines = 16,
981	.num_asids = 4,
982};
983
984#define TEGRA30_MC_RESET(_name, _control, _status, _bit)	\
985	{							\
986		.name = #_name,					\
987		.id = TEGRA30_MC_RESET_##_name,			\
988		.control = _control,				\
989		.status = _status,				\
990		.bit = _bit,					\
991	}
992
993static const struct tegra_mc_reset tegra30_mc_resets[] = {
994	TEGRA30_MC_RESET(AFI,      0x200, 0x204,  0),
995	TEGRA30_MC_RESET(AVPC,     0x200, 0x204,  1),
996	TEGRA30_MC_RESET(DC,       0x200, 0x204,  2),
997	TEGRA30_MC_RESET(DCB,      0x200, 0x204,  3),
998	TEGRA30_MC_RESET(EPP,      0x200, 0x204,  4),
999	TEGRA30_MC_RESET(2D,       0x200, 0x204,  5),
1000	TEGRA30_MC_RESET(HC,       0x200, 0x204,  6),
1001	TEGRA30_MC_RESET(HDA,      0x200, 0x204,  7),
1002	TEGRA30_MC_RESET(ISP,      0x200, 0x204,  8),
1003	TEGRA30_MC_RESET(MPCORE,   0x200, 0x204,  9),
1004	TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1005	TEGRA30_MC_RESET(MPE,      0x200, 0x204, 11),
1006	TEGRA30_MC_RESET(3D,       0x200, 0x204, 12),
1007	TEGRA30_MC_RESET(3D2,      0x200, 0x204, 13),
1008	TEGRA30_MC_RESET(PPCS,     0x200, 0x204, 14),
1009	TEGRA30_MC_RESET(SATA,     0x200, 0x204, 15),
1010	TEGRA30_MC_RESET(VDE,      0x200, 0x204, 16),
1011	TEGRA30_MC_RESET(VI,       0x200, 0x204, 17),
1012};
1013
1014const struct tegra_mc_soc tegra30_mc_soc = {
1015	.clients = tegra30_mc_clients,
1016	.num_clients = ARRAY_SIZE(tegra30_mc_clients),
1017	.num_address_bits = 32,
1018	.atom_size = 16,
1019	.client_id_mask = 0x7f,
1020	.smmu = &tegra30_smmu_soc,
1021	.emem_regs = tegra30_mc_emem_regs,
1022	.num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
1023	.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1024		   MC_INT_DECERR_EMEM,
1025	.reset_ops = &tegra_mc_reset_ops_common,
1026	.resets = tegra30_mc_resets,
1027	.num_resets = ARRAY_SIZE(tegra30_mc_resets),
1028};
1029