1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * EMIF driver 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * 7 * Aneesh V <aneesh@ti.com> 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 */ 10#include <linux/err.h> 11#include <linux/kernel.h> 12#include <linux/reboot.h> 13#include <linux/platform_data/emif_plat.h> 14#include <linux/io.h> 15#include <linux/device.h> 16#include <linux/platform_device.h> 17#include <linux/interrupt.h> 18#include <linux/slab.h> 19#include <linux/of.h> 20#include <linux/debugfs.h> 21#include <linux/seq_file.h> 22#include <linux/module.h> 23#include <linux/list.h> 24#include <linux/spinlock.h> 25#include <linux/pm.h> 26 27#include "emif.h" 28#include "jedec_ddr.h" 29#include "of_memory.h" 30 31/** 32 * struct emif_data - Per device static data for driver's use 33 * @duplicate: Whether the DDR devices attached to this EMIF 34 * instance are exactly same as that on EMIF1. In 35 * this case we can save some memory and processing 36 * @temperature_level: Maximum temperature of LPDDR2 devices attached 37 * to this EMIF - read from MR4 register. If there 38 * are two devices attached to this EMIF, this 39 * value is the maximum of the two temperature 40 * levels. 41 * @node: node in the device list 42 * @base: base address of memory-mapped IO registers. 43 * @dev: device pointer. 44 * @addressing table with addressing information from the spec 45 * @regs_cache: An array of 'struct emif_regs' that stores 46 * calculated register values for different 47 * frequencies, to avoid re-calculating them on 48 * each DVFS transition. 49 * @curr_regs: The set of register values used in the last 50 * frequency change (i.e. corresponding to the 51 * frequency in effect at the moment) 52 * @plat_data: Pointer to saved platform data. 53 * @debugfs_root: dentry to the root folder for EMIF in debugfs 54 * @np_ddr: Pointer to ddr device tree node 55 */ 56struct emif_data { 57 u8 duplicate; 58 u8 temperature_level; 59 u8 lpmode; 60 struct list_head node; 61 unsigned long irq_state; 62 void __iomem *base; 63 struct device *dev; 64 const struct lpddr2_addressing *addressing; 65 struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES]; 66 struct emif_regs *curr_regs; 67 struct emif_platform_data *plat_data; 68 struct dentry *debugfs_root; 69 struct device_node *np_ddr; 70}; 71 72static struct emif_data *emif1; 73static spinlock_t emif_lock; 74static unsigned long irq_state; 75static u32 t_ck; /* DDR clock period in ps */ 76static LIST_HEAD(device_list); 77 78#ifdef CONFIG_DEBUG_FS 79static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif, 80 struct emif_regs *regs) 81{ 82 u32 type = emif->plat_data->device_info->type; 83 u32 ip_rev = emif->plat_data->ip_rev; 84 85 seq_printf(s, "EMIF register cache dump for %dMHz\n", 86 regs->freq/1000000); 87 88 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); 89 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); 90 seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw); 91 seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw); 92 93 if (ip_rev == EMIF_4D) { 94 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n", 95 regs->read_idle_ctrl_shdw_normal); 96 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n", 97 regs->read_idle_ctrl_shdw_volt_ramp); 98 } else if (ip_rev == EMIF_4D5) { 99 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n", 100 regs->dll_calib_ctrl_shdw_normal); 101 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n", 102 regs->dll_calib_ctrl_shdw_volt_ramp); 103 } 104 105 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { 106 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n", 107 regs->ref_ctrl_shdw_derated); 108 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n", 109 regs->sdram_tim1_shdw_derated); 110 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n", 111 regs->sdram_tim3_shdw_derated); 112 } 113} 114 115static int emif_regdump_show(struct seq_file *s, void *unused) 116{ 117 struct emif_data *emif = s->private; 118 struct emif_regs **regs_cache; 119 int i; 120 121 if (emif->duplicate) 122 regs_cache = emif1->regs_cache; 123 else 124 regs_cache = emif->regs_cache; 125 126 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { 127 do_emif_regdump_show(s, emif, regs_cache[i]); 128 seq_putc(s, '\n'); 129 } 130 131 return 0; 132} 133 134DEFINE_SHOW_ATTRIBUTE(emif_regdump); 135 136static int emif_mr4_show(struct seq_file *s, void *unused) 137{ 138 struct emif_data *emif = s->private; 139 140 seq_printf(s, "MR4=%d\n", emif->temperature_level); 141 return 0; 142} 143 144DEFINE_SHOW_ATTRIBUTE(emif_mr4); 145 146static int __init_or_module emif_debugfs_init(struct emif_data *emif) 147{ 148 emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL); 149 debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif, 150 &emif_regdump_fops); 151 debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif, 152 &emif_mr4_fops); 153 return 0; 154} 155 156static void __exit emif_debugfs_exit(struct emif_data *emif) 157{ 158 debugfs_remove_recursive(emif->debugfs_root); 159 emif->debugfs_root = NULL; 160} 161#else 162static inline int __init_or_module emif_debugfs_init(struct emif_data *emif) 163{ 164 return 0; 165} 166 167static inline void __exit emif_debugfs_exit(struct emif_data *emif) 168{ 169} 170#endif 171 172/* 173 * Calculate the period of DDR clock from frequency value 174 */ 175static void set_ddr_clk_period(u32 freq) 176{ 177 /* Divide 10^12 by frequency to get period in ps */ 178 t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq); 179} 180 181/* 182 * Get bus width used by EMIF. Note that this may be different from the 183 * bus width of the DDR devices used. For instance two 16-bit DDR devices 184 * may be connected to a given CS of EMIF. In this case bus width as far 185 * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. 186 */ 187static u32 get_emif_bus_width(struct emif_data *emif) 188{ 189 u32 width; 190 void __iomem *base = emif->base; 191 192 width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) 193 >> NARROW_MODE_SHIFT; 194 width = width == 0 ? 32 : 16; 195 196 return width; 197} 198 199/* 200 * Get the CL from SDRAM_CONFIG register 201 */ 202static u32 get_cl(struct emif_data *emif) 203{ 204 u32 cl; 205 void __iomem *base = emif->base; 206 207 cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; 208 209 return cl; 210} 211 212static void set_lpmode(struct emif_data *emif, u8 lpmode) 213{ 214 u32 temp; 215 void __iomem *base = emif->base; 216 217 /* 218 * Workaround for errata i743 - LPDDR2 Power-Down State is Not 219 * Efficient 220 * 221 * i743 DESCRIPTION: 222 * The EMIF supports power-down state for low power. The EMIF 223 * automatically puts the SDRAM into power-down after the memory is 224 * not accessed for a defined number of cycles and the 225 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4. 226 * As the EMIF supports automatic output impedance calibration, a ZQ 227 * calibration long command is issued every time it exits active 228 * power-down and precharge power-down modes. The EMIF waits and 229 * blocks any other command during this calibration. 230 * The EMIF does not allow selective disabling of ZQ calibration upon 231 * exit of power-down mode. Due to very short periods of power-down 232 * cycles, ZQ calibration overhead creates bandwidth issues and 233 * increases overall system power consumption. On the other hand, 234 * issuing ZQ calibration long commands when exiting self-refresh is 235 * still required. 236 * 237 * WORKAROUND 238 * Because there is no power consumption benefit of the power-down due 239 * to the calibration and there is a performance risk, the guideline 240 * is to not allow power-down state and, therefore, to not have set 241 * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4. 242 */ 243 if ((emif->plat_data->ip_rev == EMIF_4D) && 244 (lpmode == EMIF_LP_MODE_PWR_DN)) { 245 WARN_ONCE(1, 246 "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n"); 247 /* rollback LP_MODE to Self-refresh mode */ 248 lpmode = EMIF_LP_MODE_SELF_REFRESH; 249 } 250 251 temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); 252 temp &= ~LP_MODE_MASK; 253 temp |= (lpmode << LP_MODE_SHIFT); 254 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); 255} 256 257static void do_freq_update(void) 258{ 259 struct emif_data *emif; 260 261 /* 262 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE 263 * 264 * i728 DESCRIPTION: 265 * The EMIF automatically puts the SDRAM into self-refresh mode 266 * after the EMIF has not performed accesses during 267 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles 268 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set 269 * to 0x2. If during a small window the following three events 270 * occur: 271 * - The SR_TIMING counter expires 272 * - And frequency change is requested 273 * - And OCP access is requested 274 * Then it causes instable clock on the DDR interface. 275 * 276 * WORKAROUND 277 * To avoid the occurrence of the three events, the workaround 278 * is to disable the self-refresh when requesting a frequency 279 * change. Before requesting a frequency change the software must 280 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the 281 * frequency change has been done, the software can reprogram 282 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 283 */ 284 list_for_each_entry(emif, &device_list, node) { 285 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) 286 set_lpmode(emif, EMIF_LP_MODE_DISABLE); 287 } 288 289 /* 290 * TODO: Do FREQ_UPDATE here when an API 291 * is available for this as part of the new 292 * clock framework 293 */ 294 295 list_for_each_entry(emif, &device_list, node) { 296 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) 297 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); 298 } 299} 300 301/* Find addressing table entry based on the device's type and density */ 302static const struct lpddr2_addressing *get_addressing_table( 303 const struct ddr_device_info *device_info) 304{ 305 u32 index, type, density; 306 307 type = device_info->type; 308 density = device_info->density; 309 310 switch (type) { 311 case DDR_TYPE_LPDDR2_S4: 312 index = density - 1; 313 break; 314 case DDR_TYPE_LPDDR2_S2: 315 switch (density) { 316 case DDR_DENSITY_1Gb: 317 case DDR_DENSITY_2Gb: 318 index = density + 3; 319 break; 320 default: 321 index = density - 1; 322 } 323 break; 324 default: 325 return NULL; 326 } 327 328 return &lpddr2_jedec_addressing_table[index]; 329} 330 331/* 332 * Find the the right timing table from the array of timing 333 * tables of the device using DDR clock frequency 334 */ 335static const struct lpddr2_timings *get_timings_table(struct emif_data *emif, 336 u32 freq) 337{ 338 u32 i, min, max, freq_nearest; 339 const struct lpddr2_timings *timings = NULL; 340 const struct lpddr2_timings *timings_arr = emif->plat_data->timings; 341 struct device *dev = emif->dev; 342 343 /* Start with a very high frequency - 1GHz */ 344 freq_nearest = 1000000000; 345 346 /* 347 * Find the timings table such that: 348 * 1. the frequency range covers the required frequency(safe) AND 349 * 2. the max_freq is closest to the required frequency(optimal) 350 */ 351 for (i = 0; i < emif->plat_data->timings_arr_size; i++) { 352 max = timings_arr[i].max_freq; 353 min = timings_arr[i].min_freq; 354 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) { 355 freq_nearest = max; 356 timings = &timings_arr[i]; 357 } 358 } 359 360 if (!timings) 361 dev_err(dev, "%s: couldn't find timings for - %dHz\n", 362 __func__, freq); 363 364 dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n", 365 __func__, freq, freq_nearest); 366 367 return timings; 368} 369 370static u32 get_sdram_ref_ctrl_shdw(u32 freq, 371 const struct lpddr2_addressing *addressing) 372{ 373 u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; 374 375 /* Scale down frequency and t_refi to avoid overflow */ 376 freq_khz = freq / 1000; 377 t_refi = addressing->tREFI_ns / 100; 378 379 /* 380 * refresh rate to be set is 'tREFI(in us) * freq in MHz 381 * division by 10000 to account for change in units 382 */ 383 val = t_refi * freq_khz / 10000; 384 ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; 385 386 return ref_ctrl_shdw; 387} 388 389static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, 390 const struct lpddr2_min_tck *min_tck, 391 const struct lpddr2_addressing *addressing) 392{ 393 u32 tim1 = 0, val = 0; 394 395 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; 396 tim1 |= val << T_WTR_SHIFT; 397 398 if (addressing->num_banks == B8) 399 val = DIV_ROUND_UP(timings->tFAW, t_ck*4); 400 else 401 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); 402 tim1 |= (val - 1) << T_RRD_SHIFT; 403 404 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; 405 tim1 |= val << T_RC_SHIFT; 406 407 val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); 408 tim1 |= (val - 1) << T_RAS_SHIFT; 409 410 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; 411 tim1 |= val << T_WR_SHIFT; 412 413 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; 414 tim1 |= val << T_RCD_SHIFT; 415 416 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; 417 tim1 |= val << T_RP_SHIFT; 418 419 return tim1; 420} 421 422static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings, 423 const struct lpddr2_min_tck *min_tck, 424 const struct lpddr2_addressing *addressing) 425{ 426 u32 tim1 = 0, val = 0; 427 428 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; 429 tim1 = val << T_WTR_SHIFT; 430 431 /* 432 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps 433 * to tFAW for de-rating 434 */ 435 if (addressing->num_banks == B8) { 436 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; 437 } else { 438 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); 439 val = max(min_tck->tRRD, val) - 1; 440 } 441 tim1 |= val << T_RRD_SHIFT; 442 443 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); 444 tim1 |= (val - 1) << T_RC_SHIFT; 445 446 val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); 447 val = max(min_tck->tRASmin, val) - 1; 448 tim1 |= val << T_RAS_SHIFT; 449 450 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; 451 tim1 |= val << T_WR_SHIFT; 452 453 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); 454 tim1 |= (val - 1) << T_RCD_SHIFT; 455 456 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); 457 tim1 |= (val - 1) << T_RP_SHIFT; 458 459 return tim1; 460} 461 462static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings, 463 const struct lpddr2_min_tck *min_tck, 464 const struct lpddr2_addressing *addressing, 465 u32 type) 466{ 467 u32 tim2 = 0, val = 0; 468 469 val = min_tck->tCKE - 1; 470 tim2 |= val << T_CKE_SHIFT; 471 472 val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; 473 tim2 |= val << T_RTP_SHIFT; 474 475 /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */ 476 val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; 477 tim2 |= val << T_XSNR_SHIFT; 478 479 /* XSRD same as XSNR for LPDDR2 */ 480 tim2 |= val << T_XSRD_SHIFT; 481 482 val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; 483 tim2 |= val << T_XP_SHIFT; 484 485 return tim2; 486} 487 488static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings, 489 const struct lpddr2_min_tck *min_tck, 490 const struct lpddr2_addressing *addressing, 491 u32 type, u32 ip_rev, u32 derated) 492{ 493 u32 tim3 = 0, val = 0, t_dqsck; 494 495 val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; 496 val = val > 0xF ? 0xF : val; 497 tim3 |= val << T_RAS_MAX_SHIFT; 498 499 val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; 500 tim3 |= val << T_RFC_SHIFT; 501 502 t_dqsck = (derated == EMIF_DERATED_TIMINGS) ? 503 timings->tDQSCK_max_derated : timings->tDQSCK_max; 504 if (ip_rev == EMIF_4D5) 505 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; 506 else 507 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; 508 509 tim3 |= val << T_TDQSCKMAX_SHIFT; 510 511 val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; 512 tim3 |= val << ZQ_ZQCS_SHIFT; 513 514 val = DIV_ROUND_UP(timings->tCKESR, t_ck); 515 val = max(min_tck->tCKESR, val) - 1; 516 tim3 |= val << T_CKESR_SHIFT; 517 518 if (ip_rev == EMIF_4D5) { 519 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT; 520 521 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; 522 tim3 |= val << T_PDLL_UL_SHIFT; 523 } 524 525 return tim3; 526} 527 528static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing, 529 bool cs1_used, bool cal_resistors_per_cs) 530{ 531 u32 zq = 0, val = 0; 532 533 val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns; 534 zq |= val << ZQ_REFINTERVAL_SHIFT; 535 536 val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1; 537 zq |= val << ZQ_ZQCL_MULT_SHIFT; 538 539 val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1; 540 zq |= val << ZQ_ZQINIT_MULT_SHIFT; 541 542 zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; 543 544 if (cal_resistors_per_cs) 545 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT; 546 else 547 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; 548 549 zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ 550 551 val = cs1_used ? 1 : 0; 552 zq |= val << ZQ_CS1EN_SHIFT; 553 554 return zq; 555} 556 557static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing, 558 const struct emif_custom_configs *custom_configs, bool cs1_used, 559 u32 sdram_io_width, u32 emif_bus_width) 560{ 561 u32 alert = 0, interval, devcnt; 562 563 if (custom_configs && (custom_configs->mask & 564 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)) 565 interval = custom_configs->temp_alert_poll_interval_ms; 566 else 567 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS; 568 569 interval *= 1000000; /* Convert to ns */ 570 interval /= addressing->tREFI_ns; /* Convert to refresh cycles */ 571 alert |= (interval << TA_REFINTERVAL_SHIFT); 572 573 /* 574 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width 575 * also to this form and subtract to get TA_DEVCNT, which is 576 * in log2(x) form. 577 */ 578 emif_bus_width = __fls(emif_bus_width) - 1; 579 devcnt = emif_bus_width - sdram_io_width; 580 alert |= devcnt << TA_DEVCNT_SHIFT; 581 582 /* DEVWDT is in 'log2(x) - 3' form */ 583 alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT; 584 585 alert |= 1 << TA_SFEXITEN_SHIFT; 586 alert |= 1 << TA_CS0EN_SHIFT; 587 alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT; 588 589 return alert; 590} 591 592static u32 get_read_idle_ctrl_shdw(u8 volt_ramp) 593{ 594 u32 idle = 0, val = 0; 595 596 /* 597 * Maximum value in normal conditions and increased frequency 598 * when voltage is ramping 599 */ 600 if (volt_ramp) 601 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; 602 else 603 val = 0x1FF; 604 605 /* 606 * READ_IDLE_CTRL register in EMIF4D has same offset and fields 607 * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts 608 */ 609 idle |= val << DLL_CALIB_INTERVAL_SHIFT; 610 idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT; 611 612 return idle; 613} 614 615static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp) 616{ 617 u32 calib = 0, val = 0; 618 619 if (volt_ramp == DDR_VOLTAGE_RAMPING) 620 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; 621 else 622 val = 0; /* Disabled when voltage is stable */ 623 624 calib |= val << DLL_CALIB_INTERVAL_SHIFT; 625 calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT; 626 627 return calib; 628} 629 630static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings, 631 u32 freq, u8 RL) 632{ 633 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; 634 635 val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; 636 phy |= val << READ_LATENCY_SHIFT_4D; 637 638 if (freq <= 100000000) 639 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; 640 else if (freq <= 200000000) 641 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; 642 else 643 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; 644 645 phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; 646 647 return phy; 648} 649 650static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl) 651{ 652 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay; 653 654 /* 655 * DLL operates at 266 MHz. If DDR frequency is near 266 MHz, 656 * half-delay is not needed else set half-delay 657 */ 658 if (freq >= 265000000 && freq < 267000000) 659 half_delay = 0; 660 else 661 half_delay = 1; 662 663 phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5; 664 phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS, 665 t_ck) - 1) << READ_LATENCY_SHIFT_4D5); 666 667 return phy; 668} 669 670static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void) 671{ 672 u32 fifo_we_slave_ratio; 673 674 fifo_we_slave_ratio = DIV_ROUND_CLOSEST( 675 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck); 676 677 return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 | 678 fifo_we_slave_ratio << 22; 679} 680 681static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void) 682{ 683 u32 fifo_we_slave_ratio; 684 685 fifo_we_slave_ratio = DIV_ROUND_CLOSEST( 686 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck); 687 688 return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 | 689 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23; 690} 691 692static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void) 693{ 694 u32 fifo_we_slave_ratio; 695 696 fifo_we_slave_ratio = DIV_ROUND_CLOSEST( 697 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck); 698 699 return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 | 700 fifo_we_slave_ratio << 13; 701} 702 703static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev) 704{ 705 u32 pwr_mgmt_ctrl = 0, timeout; 706 u32 lpmode = EMIF_LP_MODE_SELF_REFRESH; 707 u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE; 708 u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER; 709 u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD; 710 u32 mask; 711 u8 shift; 712 713 struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; 714 715 if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { 716 lpmode = cust_cfgs->lpmode; 717 timeout_perf = cust_cfgs->lpmode_timeout_performance; 718 timeout_pwr = cust_cfgs->lpmode_timeout_power; 719 freq_threshold = cust_cfgs->lpmode_freq_threshold; 720 } 721 722 /* Timeout based on DDR frequency */ 723 timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; 724 725 /* 726 * The value to be set in register is "log2(timeout) - 3" 727 * if timeout < 16 load 0 in register 728 * if timeout is not a power of 2, round to next highest power of 2 729 */ 730 if (timeout < 16) { 731 timeout = 0; 732 } else { 733 if (timeout & (timeout - 1)) 734 timeout <<= 1; 735 timeout = __fls(timeout) - 3; 736 } 737 738 switch (lpmode) { 739 case EMIF_LP_MODE_CLOCK_STOP: 740 shift = CS_TIM_SHIFT; 741 mask = CS_TIM_MASK; 742 break; 743 case EMIF_LP_MODE_SELF_REFRESH: 744 /* Workaround for errata i735 */ 745 if (timeout < 6) 746 timeout = 6; 747 748 shift = SR_TIM_SHIFT; 749 mask = SR_TIM_MASK; 750 break; 751 case EMIF_LP_MODE_PWR_DN: 752 shift = PD_TIM_SHIFT; 753 mask = PD_TIM_MASK; 754 break; 755 case EMIF_LP_MODE_DISABLE: 756 default: 757 mask = 0; 758 shift = 0; 759 break; 760 } 761 /* Round to maximum in case of overflow, BUT warn! */ 762 if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) { 763 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n", 764 lpmode, 765 timeout_perf, 766 timeout_pwr, 767 freq_threshold); 768 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n", 769 timeout, mask >> shift); 770 timeout = mask >> shift; 771 } 772 773 /* Setup required timing */ 774 pwr_mgmt_ctrl = (timeout << shift) & mask; 775 /* setup a default mask for rest of the modes */ 776 pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) & 777 ~mask; 778 779 /* No CS_TIM in EMIF_4D5 */ 780 if (ip_rev == EMIF_4D5) 781 pwr_mgmt_ctrl &= ~CS_TIM_MASK; 782 783 pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; 784 785 return pwr_mgmt_ctrl; 786} 787 788/* 789 * Get the temperature level of the EMIF instance: 790 * Reads the MR4 register of attached SDRAM parts to find out the temperature 791 * level. If there are two parts attached(one on each CS), then the temperature 792 * level for the EMIF instance is the higher of the two temperatures. 793 */ 794static void get_temperature_level(struct emif_data *emif) 795{ 796 u32 temp, temperature_level; 797 void __iomem *base; 798 799 base = emif->base; 800 801 /* Read mode register 4 */ 802 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); 803 temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA); 804 temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >> 805 MR4_SDRAM_REF_RATE_SHIFT; 806 807 if (emif->plat_data->device_info->cs1_used) { 808 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); 809 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA); 810 temp = (temp & MR4_SDRAM_REF_RATE_MASK) 811 >> MR4_SDRAM_REF_RATE_SHIFT; 812 temperature_level = max(temp, temperature_level); 813 } 814 815 /* treat everything less than nominal(3) in MR4 as nominal */ 816 if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL)) 817 temperature_level = SDRAM_TEMP_NOMINAL; 818 819 /* if we get reserved value in MR4 persist with the existing value */ 820 if (likely(temperature_level != SDRAM_TEMP_RESERVED_4)) 821 emif->temperature_level = temperature_level; 822} 823 824/* 825 * Program EMIF shadow registers that are not dependent on temperature 826 * or voltage 827 */ 828static void setup_registers(struct emif_data *emif, struct emif_regs *regs) 829{ 830 void __iomem *base = emif->base; 831 832 writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); 833 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); 834 writel(regs->pwr_mgmt_ctrl_shdw, 835 base + EMIF_POWER_MANAGEMENT_CTRL_SHDW); 836 837 /* Settings specific for EMIF4D5 */ 838 if (emif->plat_data->ip_rev != EMIF_4D5) 839 return; 840 writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); 841 writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); 842 writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); 843} 844 845/* 846 * When voltage ramps dll calibration and forced read idle should 847 * happen more often 848 */ 849static void setup_volt_sensitive_regs(struct emif_data *emif, 850 struct emif_regs *regs, u32 volt_state) 851{ 852 u32 calib_ctrl; 853 void __iomem *base = emif->base; 854 855 /* 856 * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as 857 * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_* 858 * is an alias of the respective read_idle_ctrl_shdw_* (members of 859 * a union). So, the below code takes care of both cases 860 */ 861 if (volt_state == DDR_VOLTAGE_RAMPING) 862 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp; 863 else 864 calib_ctrl = regs->dll_calib_ctrl_shdw_normal; 865 866 writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); 867} 868 869/* 870 * setup_temperature_sensitive_regs() - set the timings for temperature 871 * sensitive registers. This happens once at initialisation time based 872 * on the temperature at boot time and subsequently based on the temperature 873 * alert interrupt. Temperature alert can happen when the temperature 874 * increases or drops. So this function can have the effect of either 875 * derating the timings or going back to nominal values. 876 */ 877static void setup_temperature_sensitive_regs(struct emif_data *emif, 878 struct emif_regs *regs) 879{ 880 u32 tim1, tim3, ref_ctrl, type; 881 void __iomem *base = emif->base; 882 u32 temperature; 883 884 type = emif->plat_data->device_info->type; 885 886 tim1 = regs->sdram_tim1_shdw; 887 tim3 = regs->sdram_tim3_shdw; 888 ref_ctrl = regs->ref_ctrl_shdw; 889 890 /* No de-rating for non-lpddr2 devices */ 891 if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4) 892 goto out; 893 894 temperature = emif->temperature_level; 895 if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) { 896 ref_ctrl = regs->ref_ctrl_shdw_derated; 897 } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) { 898 tim1 = regs->sdram_tim1_shdw_derated; 899 tim3 = regs->sdram_tim3_shdw_derated; 900 ref_ctrl = regs->ref_ctrl_shdw_derated; 901 } 902 903out: 904 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); 905 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); 906 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); 907} 908 909static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif) 910{ 911 u32 old_temp_level; 912 irqreturn_t ret = IRQ_HANDLED; 913 struct emif_custom_configs *custom_configs; 914 915 spin_lock_irqsave(&emif_lock, irq_state); 916 old_temp_level = emif->temperature_level; 917 get_temperature_level(emif); 918 919 if (unlikely(emif->temperature_level == old_temp_level)) { 920 goto out; 921 } else if (!emif->curr_regs) { 922 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); 923 goto out; 924 } 925 926 custom_configs = emif->plat_data->custom_configs; 927 928 /* 929 * IF we detect higher than "nominal rating" from DDR sensor 930 * on an unsupported DDR part, shutdown system 931 */ 932 if (custom_configs && !(custom_configs->mask & 933 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) { 934 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) { 935 dev_err(emif->dev, 936 "%s:NOT Extended temperature capable memory. Converting MR4=0x%02x as shutdown event\n", 937 __func__, emif->temperature_level); 938 /* 939 * Temperature far too high - do kernel_power_off() 940 * from thread context 941 */ 942 emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN; 943 ret = IRQ_WAKE_THREAD; 944 goto out; 945 } 946 } 947 948 if (emif->temperature_level < old_temp_level || 949 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { 950 /* 951 * Temperature coming down - defer handling to thread OR 952 * Temperature far too high - do kernel_power_off() from 953 * thread context 954 */ 955 ret = IRQ_WAKE_THREAD; 956 } else { 957 /* Temperature is going up - handle immediately */ 958 setup_temperature_sensitive_regs(emif, emif->curr_regs); 959 do_freq_update(); 960 } 961 962out: 963 spin_unlock_irqrestore(&emif_lock, irq_state); 964 return ret; 965} 966 967static irqreturn_t emif_interrupt_handler(int irq, void *dev_id) 968{ 969 u32 interrupts; 970 struct emif_data *emif = dev_id; 971 void __iomem *base = emif->base; 972 struct device *dev = emif->dev; 973 irqreturn_t ret = IRQ_HANDLED; 974 975 /* Save the status and clear it */ 976 interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); 977 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); 978 979 /* 980 * Handle temperature alert 981 * Temperature alert should be same for all ports 982 * So, it's enough to process it only for one of the ports 983 */ 984 if (interrupts & TA_SYS_MASK) 985 ret = handle_temp_alert(base, emif); 986 987 if (interrupts & ERR_SYS_MASK) 988 dev_err(dev, "Access error from SYS port - %x\n", interrupts); 989 990 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { 991 /* Save the status and clear it */ 992 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); 993 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); 994 995 if (interrupts & ERR_LL_MASK) 996 dev_err(dev, "Access error from LL port - %x\n", 997 interrupts); 998 } 999 1000 return ret; 1001} 1002 1003static irqreturn_t emif_threaded_isr(int irq, void *dev_id) 1004{ 1005 struct emif_data *emif = dev_id; 1006 1007 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { 1008 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); 1009 1010 /* If we have Power OFF ability, use it, else try restarting */ 1011 if (pm_power_off) { 1012 kernel_power_off(); 1013 } else { 1014 WARN(1, "FIXME: NO pm_power_off!!! trying restart\n"); 1015 kernel_restart("SDRAM Over-temp Emergency restart"); 1016 } 1017 return IRQ_HANDLED; 1018 } 1019 1020 spin_lock_irqsave(&emif_lock, irq_state); 1021 1022 if (emif->curr_regs) { 1023 setup_temperature_sensitive_regs(emif, emif->curr_regs); 1024 do_freq_update(); 1025 } else { 1026 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); 1027 } 1028 1029 spin_unlock_irqrestore(&emif_lock, irq_state); 1030 1031 return IRQ_HANDLED; 1032} 1033 1034static void clear_all_interrupts(struct emif_data *emif) 1035{ 1036 void __iomem *base = emif->base; 1037 1038 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), 1039 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); 1040 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) 1041 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), 1042 base + EMIF_LL_OCP_INTERRUPT_STATUS); 1043} 1044 1045static void disable_and_clear_all_interrupts(struct emif_data *emif) 1046{ 1047 void __iomem *base = emif->base; 1048 1049 /* Disable all interrupts */ 1050 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), 1051 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR); 1052 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) 1053 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), 1054 base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR); 1055 1056 /* Clear all interrupts */ 1057 clear_all_interrupts(emif); 1058} 1059 1060static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq) 1061{ 1062 u32 interrupts, type; 1063 void __iomem *base = emif->base; 1064 1065 type = emif->plat_data->device_info->type; 1066 1067 clear_all_interrupts(emif); 1068 1069 /* Enable interrupts for SYS interface */ 1070 interrupts = EN_ERR_SYS_MASK; 1071 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) 1072 interrupts |= EN_TA_SYS_MASK; 1073 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); 1074 1075 /* Enable interrupts for LL interface */ 1076 if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { 1077 /* TA need not be enabled for LL */ 1078 interrupts = EN_ERR_LL_MASK; 1079 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); 1080 } 1081 1082 /* setup IRQ handlers */ 1083 return devm_request_threaded_irq(emif->dev, irq, 1084 emif_interrupt_handler, 1085 emif_threaded_isr, 1086 0, dev_name(emif->dev), 1087 emif); 1088 1089} 1090 1091static void __init_or_module emif_onetime_settings(struct emif_data *emif) 1092{ 1093 u32 pwr_mgmt_ctrl, zq, temp_alert_cfg; 1094 void __iomem *base = emif->base; 1095 const struct lpddr2_addressing *addressing; 1096 const struct ddr_device_info *device_info; 1097 1098 device_info = emif->plat_data->device_info; 1099 addressing = get_addressing_table(device_info); 1100 1101 /* 1102 * Init power management settings 1103 * We don't know the frequency yet. Use a high frequency 1104 * value for a conservative timeout setting 1105 */ 1106 pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif, 1107 emif->plat_data->ip_rev); 1108 emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT; 1109 writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); 1110 1111 /* Init ZQ calibration settings */ 1112 zq = get_zq_config_reg(addressing, device_info->cs1_used, 1113 device_info->cal_resistors_per_cs); 1114 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); 1115 1116 /* Check temperature level temperature level*/ 1117 get_temperature_level(emif); 1118 if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) 1119 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); 1120 1121 /* Init temperature polling */ 1122 temp_alert_cfg = get_temp_alert_config(addressing, 1123 emif->plat_data->custom_configs, device_info->cs1_used, 1124 device_info->io_width, get_emif_bus_width(emif)); 1125 writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); 1126 1127 /* 1128 * Program external PHY control registers that are not frequency 1129 * dependent 1130 */ 1131 if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY) 1132 return; 1133 writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); 1134 writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); 1135 writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); 1136 writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); 1137 writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); 1138 writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); 1139 writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); 1140 writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); 1141 writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); 1142 writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); 1143 writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); 1144 writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); 1145 writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); 1146 writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); 1147 writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); 1148 writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); 1149 writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); 1150 writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); 1151 writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); 1152 writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); 1153 writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); 1154} 1155 1156static void get_default_timings(struct emif_data *emif) 1157{ 1158 struct emif_platform_data *pd = emif->plat_data; 1159 1160 pd->timings = lpddr2_jedec_timings; 1161 pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); 1162 1163 dev_warn(emif->dev, "%s: using default timings\n", __func__); 1164} 1165 1166static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, 1167 u32 ip_rev, struct device *dev) 1168{ 1169 int valid; 1170 1171 valid = (type == DDR_TYPE_LPDDR2_S4 || 1172 type == DDR_TYPE_LPDDR2_S2) 1173 && (density >= DDR_DENSITY_64Mb 1174 && density <= DDR_DENSITY_8Gb) 1175 && (io_width >= DDR_IO_WIDTH_8 1176 && io_width <= DDR_IO_WIDTH_32); 1177 1178 /* Combinations of EMIF and PHY revisions that we support today */ 1179 switch (ip_rev) { 1180 case EMIF_4D: 1181 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); 1182 break; 1183 case EMIF_4D5: 1184 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); 1185 break; 1186 default: 1187 valid = 0; 1188 } 1189 1190 if (!valid) 1191 dev_err(dev, "%s: invalid DDR details\n", __func__); 1192 return valid; 1193} 1194 1195static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, 1196 struct device *dev) 1197{ 1198 int valid = 1; 1199 1200 if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && 1201 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) 1202 valid = cust_cfgs->lpmode_freq_threshold && 1203 cust_cfgs->lpmode_timeout_performance && 1204 cust_cfgs->lpmode_timeout_power; 1205 1206 if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) 1207 valid = valid && cust_cfgs->temp_alert_poll_interval_ms; 1208 1209 if (!valid) 1210 dev_warn(dev, "%s: invalid custom configs\n", __func__); 1211 1212 return valid; 1213} 1214 1215#if defined(CONFIG_OF) 1216static void __init_or_module of_get_custom_configs(struct device_node *np_emif, 1217 struct emif_data *emif) 1218{ 1219 struct emif_custom_configs *cust_cfgs = NULL; 1220 int len; 1221 const __be32 *lpmode, *poll_intvl; 1222 1223 lpmode = of_get_property(np_emif, "low-power-mode", &len); 1224 poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len); 1225 1226 if (lpmode || poll_intvl) 1227 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs), 1228 GFP_KERNEL); 1229 1230 if (!cust_cfgs) 1231 return; 1232 1233 if (lpmode) { 1234 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE; 1235 cust_cfgs->lpmode = be32_to_cpup(lpmode); 1236 of_property_read_u32(np_emif, 1237 "low-power-mode-timeout-performance", 1238 &cust_cfgs->lpmode_timeout_performance); 1239 of_property_read_u32(np_emif, 1240 "low-power-mode-timeout-power", 1241 &cust_cfgs->lpmode_timeout_power); 1242 of_property_read_u32(np_emif, 1243 "low-power-mode-freq-threshold", 1244 &cust_cfgs->lpmode_freq_threshold); 1245 } 1246 1247 if (poll_intvl) { 1248 cust_cfgs->mask |= 1249 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL; 1250 cust_cfgs->temp_alert_poll_interval_ms = 1251 be32_to_cpup(poll_intvl); 1252 } 1253 1254 if (of_find_property(np_emif, "extended-temp-part", &len)) 1255 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART; 1256 1257 if (!is_custom_config_valid(cust_cfgs, emif->dev)) { 1258 devm_kfree(emif->dev, cust_cfgs); 1259 return; 1260 } 1261 1262 emif->plat_data->custom_configs = cust_cfgs; 1263} 1264 1265static void __init_or_module of_get_ddr_info(struct device_node *np_emif, 1266 struct device_node *np_ddr, 1267 struct ddr_device_info *dev_info) 1268{ 1269 u32 density = 0, io_width = 0; 1270 int len; 1271 1272 if (of_find_property(np_emif, "cs1-used", &len)) 1273 dev_info->cs1_used = true; 1274 1275 if (of_find_property(np_emif, "cal-resistor-per-cs", &len)) 1276 dev_info->cal_resistors_per_cs = true; 1277 1278 if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s4")) 1279 dev_info->type = DDR_TYPE_LPDDR2_S4; 1280 else if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s2")) 1281 dev_info->type = DDR_TYPE_LPDDR2_S2; 1282 1283 of_property_read_u32(np_ddr, "density", &density); 1284 of_property_read_u32(np_ddr, "io-width", &io_width); 1285 1286 /* Convert from density in Mb to the density encoding in jedc_ddr.h */ 1287 if (density & (density - 1)) 1288 dev_info->density = 0; 1289 else 1290 dev_info->density = __fls(density) - 5; 1291 1292 /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */ 1293 if (io_width & (io_width - 1)) 1294 dev_info->io_width = 0; 1295 else 1296 dev_info->io_width = __fls(io_width) - 1; 1297} 1298 1299static struct emif_data * __init_or_module of_get_memory_device_details( 1300 struct device_node *np_emif, struct device *dev) 1301{ 1302 struct emif_data *emif = NULL; 1303 struct ddr_device_info *dev_info = NULL; 1304 struct emif_platform_data *pd = NULL; 1305 struct device_node *np_ddr; 1306 int len; 1307 1308 np_ddr = of_parse_phandle(np_emif, "device-handle", 0); 1309 if (!np_ddr) 1310 goto error; 1311 emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL); 1312 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 1313 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); 1314 1315 if (!emif || !pd || !dev_info) { 1316 dev_err(dev, "%s: Out of memory!!\n", 1317 __func__); 1318 goto error; 1319 } 1320 1321 emif->plat_data = pd; 1322 pd->device_info = dev_info; 1323 emif->dev = dev; 1324 emif->np_ddr = np_ddr; 1325 emif->temperature_level = SDRAM_TEMP_NOMINAL; 1326 1327 if (of_device_is_compatible(np_emif, "ti,emif-4d")) 1328 emif->plat_data->ip_rev = EMIF_4D; 1329 else if (of_device_is_compatible(np_emif, "ti,emif-4d5")) 1330 emif->plat_data->ip_rev = EMIF_4D5; 1331 1332 of_property_read_u32(np_emif, "phy-type", &pd->phy_type); 1333 1334 if (of_find_property(np_emif, "hw-caps-ll-interface", &len)) 1335 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE; 1336 1337 of_get_ddr_info(np_emif, np_ddr, dev_info); 1338 if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density, 1339 pd->device_info->io_width, pd->phy_type, pd->ip_rev, 1340 emif->dev)) { 1341 dev_err(dev, "%s: invalid device data!!\n", __func__); 1342 goto error; 1343 } 1344 /* 1345 * For EMIF instances other than EMIF1 see if the devices connected 1346 * are exactly same as on EMIF1(which is typically the case). If so, 1347 * mark it as a duplicate of EMIF1. This will save some memory and 1348 * computation. 1349 */ 1350 if (emif1 && emif1->np_ddr == np_ddr) { 1351 emif->duplicate = true; 1352 goto out; 1353 } else if (emif1) { 1354 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", 1355 __func__); 1356 } 1357 1358 of_get_custom_configs(np_emif, emif); 1359 emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev, 1360 emif->plat_data->device_info->type, 1361 &emif->plat_data->timings_arr_size); 1362 1363 emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev); 1364 goto out; 1365 1366error: 1367 return NULL; 1368out: 1369 return emif; 1370} 1371 1372#else 1373 1374static struct emif_data * __init_or_module of_get_memory_device_details( 1375 struct device_node *np_emif, struct device *dev) 1376{ 1377 return NULL; 1378} 1379#endif 1380 1381static struct emif_data *__init_or_module get_device_details( 1382 struct platform_device *pdev) 1383{ 1384 u32 size; 1385 struct emif_data *emif = NULL; 1386 struct ddr_device_info *dev_info; 1387 struct emif_custom_configs *cust_cfgs; 1388 struct emif_platform_data *pd; 1389 struct device *dev; 1390 void *temp; 1391 1392 pd = pdev->dev.platform_data; 1393 dev = &pdev->dev; 1394 1395 if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, 1396 pd->device_info->density, pd->device_info->io_width, 1397 pd->phy_type, pd->ip_rev, dev))) { 1398 dev_err(dev, "%s: invalid device data\n", __func__); 1399 goto error; 1400 } 1401 1402 emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); 1403 temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 1404 dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); 1405 1406 if (!emif || !temp || !dev_info) { 1407 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); 1408 goto error; 1409 } 1410 1411 memcpy(temp, pd, sizeof(*pd)); 1412 pd = temp; 1413 memcpy(dev_info, pd->device_info, sizeof(*dev_info)); 1414 1415 pd->device_info = dev_info; 1416 emif->plat_data = pd; 1417 emif->dev = dev; 1418 emif->temperature_level = SDRAM_TEMP_NOMINAL; 1419 1420 /* 1421 * For EMIF instances other than EMIF1 see if the devices connected 1422 * are exactly same as on EMIF1(which is typically the case). If so, 1423 * mark it as a duplicate of EMIF1 and skip copying timings data. 1424 * This will save some memory and some computation later. 1425 */ 1426 emif->duplicate = emif1 && (memcmp(dev_info, 1427 emif1->plat_data->device_info, 1428 sizeof(struct ddr_device_info)) == 0); 1429 1430 if (emif->duplicate) { 1431 pd->timings = NULL; 1432 pd->min_tck = NULL; 1433 goto out; 1434 } else if (emif1) { 1435 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", 1436 __func__); 1437 } 1438 1439 /* 1440 * Copy custom configs - ignore allocation error, if any, as 1441 * custom_configs is not very critical 1442 */ 1443 cust_cfgs = pd->custom_configs; 1444 if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { 1445 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); 1446 if (temp) 1447 memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); 1448 else 1449 dev_warn(dev, "%s:%d: allocation error\n", __func__, 1450 __LINE__); 1451 pd->custom_configs = temp; 1452 } 1453 1454 /* 1455 * Copy timings and min-tck values from platform data. If it is not 1456 * available or if memory allocation fails, use JEDEC defaults 1457 */ 1458 size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; 1459 if (pd->timings) { 1460 temp = devm_kzalloc(dev, size, GFP_KERNEL); 1461 if (temp) { 1462 memcpy(temp, pd->timings, size); 1463 pd->timings = temp; 1464 } else { 1465 dev_warn(dev, "%s:%d: allocation error\n", __func__, 1466 __LINE__); 1467 get_default_timings(emif); 1468 } 1469 } else { 1470 get_default_timings(emif); 1471 } 1472 1473 if (pd->min_tck) { 1474 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); 1475 if (temp) { 1476 memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); 1477 pd->min_tck = temp; 1478 } else { 1479 dev_warn(dev, "%s:%d: allocation error\n", __func__, 1480 __LINE__); 1481 pd->min_tck = &lpddr2_jedec_min_tck; 1482 } 1483 } else { 1484 pd->min_tck = &lpddr2_jedec_min_tck; 1485 } 1486 1487out: 1488 return emif; 1489 1490error: 1491 return NULL; 1492} 1493 1494static int __init_or_module emif_probe(struct platform_device *pdev) 1495{ 1496 struct emif_data *emif; 1497 struct resource *res; 1498 int irq, ret; 1499 1500 if (pdev->dev.of_node) 1501 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev); 1502 else 1503 emif = get_device_details(pdev); 1504 1505 if (!emif) { 1506 pr_err("%s: error getting device data\n", __func__); 1507 goto error; 1508 } 1509 1510 list_add(&emif->node, &device_list); 1511 emif->addressing = get_addressing_table(emif->plat_data->device_info); 1512 1513 /* Save pointers to each other in emif and device structures */ 1514 emif->dev = &pdev->dev; 1515 platform_set_drvdata(pdev, emif); 1516 1517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1518 emif->base = devm_ioremap_resource(emif->dev, res); 1519 if (IS_ERR(emif->base)) 1520 goto error; 1521 1522 irq = platform_get_irq(pdev, 0); 1523 if (irq < 0) 1524 goto error; 1525 1526 emif_onetime_settings(emif); 1527 emif_debugfs_init(emif); 1528 disable_and_clear_all_interrupts(emif); 1529 ret = setup_interrupts(emif, irq); 1530 if (ret) 1531 goto error; 1532 1533 /* One-time actions taken on probing the first device */ 1534 if (!emif1) { 1535 emif1 = emif; 1536 spin_lock_init(&emif_lock); 1537 1538 /* 1539 * TODO: register notifiers for frequency and voltage 1540 * change here once the respective frameworks are 1541 * available 1542 */ 1543 } 1544 1545 dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n", 1546 __func__, emif->base, irq); 1547 1548 return 0; 1549error: 1550 return -ENODEV; 1551} 1552 1553static int __exit emif_remove(struct platform_device *pdev) 1554{ 1555 struct emif_data *emif = platform_get_drvdata(pdev); 1556 1557 emif_debugfs_exit(emif); 1558 1559 return 0; 1560} 1561 1562static void emif_shutdown(struct platform_device *pdev) 1563{ 1564 struct emif_data *emif = platform_get_drvdata(pdev); 1565 1566 disable_and_clear_all_interrupts(emif); 1567} 1568 1569static int get_emif_reg_values(struct emif_data *emif, u32 freq, 1570 struct emif_regs *regs) 1571{ 1572 u32 ip_rev, phy_type; 1573 u32 cl, type; 1574 const struct lpddr2_timings *timings; 1575 const struct lpddr2_min_tck *min_tck; 1576 const struct ddr_device_info *device_info; 1577 const struct lpddr2_addressing *addressing; 1578 struct emif_data *emif_for_calc; 1579 struct device *dev; 1580 1581 dev = emif->dev; 1582 /* 1583 * If the devices on this EMIF instance is duplicate of EMIF1, 1584 * use EMIF1 details for the calculation 1585 */ 1586 emif_for_calc = emif->duplicate ? emif1 : emif; 1587 timings = get_timings_table(emif_for_calc, freq); 1588 addressing = emif_for_calc->addressing; 1589 if (!timings || !addressing) { 1590 dev_err(dev, "%s: not enough data available for %dHz", 1591 __func__, freq); 1592 return -1; 1593 } 1594 1595 device_info = emif_for_calc->plat_data->device_info; 1596 type = device_info->type; 1597 ip_rev = emif_for_calc->plat_data->ip_rev; 1598 phy_type = emif_for_calc->plat_data->phy_type; 1599 1600 min_tck = emif_for_calc->plat_data->min_tck; 1601 1602 set_ddr_clk_period(freq); 1603 1604 regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing); 1605 regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck, 1606 addressing); 1607 regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck, 1608 addressing, type); 1609 regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck, 1610 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS); 1611 1612 cl = get_cl(emif); 1613 1614 if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) { 1615 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( 1616 timings, freq, cl); 1617 } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) { 1618 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); 1619 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5(); 1620 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5(); 1621 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5(); 1622 } else { 1623 return -1; 1624 } 1625 1626 /* Only timeout values in pwr_mgmt_ctrl_shdw register */ 1627 regs->pwr_mgmt_ctrl_shdw = 1628 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) & 1629 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK); 1630 1631 if (ip_rev & EMIF_4D) { 1632 regs->read_idle_ctrl_shdw_normal = 1633 get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE); 1634 1635 regs->read_idle_ctrl_shdw_volt_ramp = 1636 get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING); 1637 } else if (ip_rev & EMIF_4D5) { 1638 regs->dll_calib_ctrl_shdw_normal = 1639 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE); 1640 1641 regs->dll_calib_ctrl_shdw_volt_ramp = 1642 get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING); 1643 } 1644 1645 if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { 1646 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4, 1647 addressing); 1648 1649 regs->sdram_tim1_shdw_derated = 1650 get_sdram_tim_1_shdw_derated(timings, min_tck, 1651 addressing); 1652 1653 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings, 1654 min_tck, addressing, type, ip_rev, 1655 EMIF_DERATED_TIMINGS); 1656 } 1657 1658 regs->freq = freq; 1659 1660 return 0; 1661} 1662 1663/* 1664 * get_regs() - gets the cached emif_regs structure for a given EMIF instance 1665 * given frequency(freq): 1666 * 1667 * As an optimisation, every EMIF instance other than EMIF1 shares the 1668 * register cache with EMIF1 if the devices connected on this instance 1669 * are same as that on EMIF1(indicated by the duplicate flag) 1670 * 1671 * If we do not have an entry corresponding to the frequency given, we 1672 * allocate a new entry and calculate the values 1673 * 1674 * Upon finding the right reg dump, save it in curr_regs. It can be 1675 * directly used for thermal de-rating and voltage ramping changes. 1676 */ 1677static struct emif_regs *get_regs(struct emif_data *emif, u32 freq) 1678{ 1679 int i; 1680 struct emif_regs **regs_cache; 1681 struct emif_regs *regs = NULL; 1682 struct device *dev; 1683 1684 dev = emif->dev; 1685 if (emif->curr_regs && emif->curr_regs->freq == freq) { 1686 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq); 1687 return emif->curr_regs; 1688 } 1689 1690 if (emif->duplicate) 1691 regs_cache = emif1->regs_cache; 1692 else 1693 regs_cache = emif->regs_cache; 1694 1695 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { 1696 if (regs_cache[i]->freq == freq) { 1697 regs = regs_cache[i]; 1698 dev_dbg(dev, 1699 "%s: reg dump found in reg cache for %u Hz\n", 1700 __func__, freq); 1701 break; 1702 } 1703 } 1704 1705 /* 1706 * If we don't have an entry for this frequency in the cache create one 1707 * and calculate the values 1708 */ 1709 if (!regs) { 1710 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC); 1711 if (!regs) 1712 return NULL; 1713 1714 if (get_emif_reg_values(emif, freq, regs)) { 1715 devm_kfree(emif->dev, regs); 1716 return NULL; 1717 } 1718 1719 /* 1720 * Now look for an un-used entry in the cache and save the 1721 * newly created struct. If there are no free entries 1722 * over-write the last entry 1723 */ 1724 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) 1725 ; 1726 1727 if (i >= EMIF_MAX_NUM_FREQUENCIES) { 1728 dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n", 1729 __func__); 1730 i = EMIF_MAX_NUM_FREQUENCIES - 1; 1731 devm_kfree(emif->dev, regs_cache[i]); 1732 } 1733 regs_cache[i] = regs; 1734 } 1735 1736 return regs; 1737} 1738 1739static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state) 1740{ 1741 dev_dbg(emif->dev, "%s: voltage notification : %d", __func__, 1742 volt_state); 1743 1744 if (!emif->curr_regs) { 1745 dev_err(emif->dev, 1746 "%s: volt-notify before registers are ready: %d\n", 1747 __func__, volt_state); 1748 return; 1749 } 1750 1751 setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state); 1752} 1753 1754/* 1755 * TODO: voltage notify handling should be hooked up to 1756 * regulator framework as soon as the necessary support 1757 * is available in mainline kernel. This function is un-used 1758 * right now. 1759 */ 1760static void __attribute__((unused)) volt_notify_handling(u32 volt_state) 1761{ 1762 struct emif_data *emif; 1763 1764 spin_lock_irqsave(&emif_lock, irq_state); 1765 1766 list_for_each_entry(emif, &device_list, node) 1767 do_volt_notify_handling(emif, volt_state); 1768 do_freq_update(); 1769 1770 spin_unlock_irqrestore(&emif_lock, irq_state); 1771} 1772 1773static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq) 1774{ 1775 struct emif_regs *regs; 1776 1777 regs = get_regs(emif, new_freq); 1778 if (!regs) 1779 return; 1780 1781 emif->curr_regs = regs; 1782 1783 /* 1784 * Update the shadow registers: 1785 * Temperature and voltage-ramp sensitive settings are also configured 1786 * in terms of DDR cycles. So, we need to update them too when there 1787 * is a freq change 1788 */ 1789 dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz", 1790 __func__, new_freq); 1791 setup_registers(emif, regs); 1792 setup_temperature_sensitive_regs(emif, regs); 1793 setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE); 1794 1795 /* 1796 * Part of workaround for errata i728. See do_freq_update() 1797 * for more details 1798 */ 1799 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) 1800 set_lpmode(emif, EMIF_LP_MODE_DISABLE); 1801} 1802 1803/* 1804 * TODO: frequency notify handling should be hooked up to 1805 * clock framework as soon as the necessary support is 1806 * available in mainline kernel. This function is un-used 1807 * right now. 1808 */ 1809static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq) 1810{ 1811 struct emif_data *emif; 1812 1813 /* 1814 * NOTE: we are taking the spin-lock here and releases it 1815 * only in post-notifier. This doesn't look good and 1816 * Sparse complains about it, but this seems to be 1817 * un-avoidable. We need to lock a sequence of events 1818 * that is split between EMIF and clock framework. 1819 * 1820 * 1. EMIF driver updates EMIF timings in shadow registers in the 1821 * frequency pre-notify callback from clock framework 1822 * 2. clock framework sets up the registers for the new frequency 1823 * 3. clock framework initiates a hw-sequence that updates 1824 * the frequency EMIF timings synchronously. 1825 * 1826 * All these 3 steps should be performed as an atomic operation 1827 * vis-a-vis similar sequence in the EMIF interrupt handler 1828 * for temperature events. Otherwise, there could be race 1829 * conditions that could result in incorrect EMIF timings for 1830 * a given frequency 1831 */ 1832 spin_lock_irqsave(&emif_lock, irq_state); 1833 1834 list_for_each_entry(emif, &device_list, node) 1835 do_freq_pre_notify_handling(emif, new_freq); 1836} 1837 1838static void do_freq_post_notify_handling(struct emif_data *emif) 1839{ 1840 /* 1841 * Part of workaround for errata i728. See do_freq_update() 1842 * for more details 1843 */ 1844 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) 1845 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); 1846} 1847 1848/* 1849 * TODO: frequency notify handling should be hooked up to 1850 * clock framework as soon as the necessary support is 1851 * available in mainline kernel. This function is un-used 1852 * right now. 1853 */ 1854static void __attribute__((unused)) freq_post_notify_handling(void) 1855{ 1856 struct emif_data *emif; 1857 1858 list_for_each_entry(emif, &device_list, node) 1859 do_freq_post_notify_handling(emif); 1860 1861 /* 1862 * Lock is done in pre-notify handler. See freq_pre_notify_handling() 1863 * for more details 1864 */ 1865 spin_unlock_irqrestore(&emif_lock, irq_state); 1866} 1867 1868#if defined(CONFIG_OF) 1869static const struct of_device_id emif_of_match[] = { 1870 { .compatible = "ti,emif-4d" }, 1871 { .compatible = "ti,emif-4d5" }, 1872 {}, 1873}; 1874MODULE_DEVICE_TABLE(of, emif_of_match); 1875#endif 1876 1877static struct platform_driver emif_driver = { 1878 .remove = __exit_p(emif_remove), 1879 .shutdown = emif_shutdown, 1880 .driver = { 1881 .name = "emif", 1882 .of_match_table = of_match_ptr(emif_of_match), 1883 }, 1884}; 1885 1886module_platform_driver_probe(emif_driver, emif_probe); 1887 1888MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); 1889MODULE_LICENSE("GPL"); 1890MODULE_ALIAS("platform:emif"); 1891MODULE_AUTHOR("Texas Instruments Inc"); 1892