1// SPDX-License-Identifier: GPL-2.0-or-later 2/* stk-sensor.c: Driver for ov96xx sensor (used in some Syntek webcams) 3 * 4 * Copyright 2007-2008 Jaime Velasco Juan <jsagarribay@gmail.com> 5 * 6 * Some parts derived from ov7670.c: 7 * Copyright 2006 One Laptop Per Child Association, Inc. Written 8 * by Jonathan Corbet with substantial inspiration from Mark 9 * McClelland's ovcamchip code. 10 * 11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 12 * 13 * This file may be distributed under the terms of the GNU General 14 */ 15 16/* Controlling the sensor via the STK1125 vendor specific control interface: 17 * The camera uses an OmniVision sensor and the stk1125 provides an 18 * SCCB(i2c)-USB bridge which let us program the sensor. 19 * In my case the sensor id is 0x9652, it can be read from sensor's register 20 * 0x0A and 0x0B as follows: 21 * - read register #R: 22 * output #R to index 0x0208 23 * output 0x0070 to index 0x0200 24 * input 1 byte from index 0x0201 (some kind of status register) 25 * until its value is 0x01 26 * input 1 byte from index 0x0209. This is the value of #R 27 * - write value V to register #R 28 * output #R to index 0x0204 29 * output V to index 0x0205 30 * output 0x0005 to index 0x0200 31 * input 1 byte from index 0x0201 until its value becomes 0x04 32 */ 33 34/* It seems the i2c bus is controlled with these registers */ 35 36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 37 38#include "stk-webcam.h" 39 40#define STK_IIC_BASE (0x0200) 41# define STK_IIC_OP (STK_IIC_BASE) 42# define STK_IIC_OP_TX (0x05) 43# define STK_IIC_OP_RX (0x70) 44# define STK_IIC_STAT (STK_IIC_BASE+1) 45# define STK_IIC_STAT_TX_OK (0x04) 46# define STK_IIC_STAT_RX_OK (0x01) 47/* I don't know what does this register. 48 * when it is 0x00 or 0x01, we cannot talk to the sensor, 49 * other values work */ 50# define STK_IIC_ENABLE (STK_IIC_BASE+2) 51# define STK_IIC_ENABLE_NO (0x00) 52/* This is what the driver writes in windows */ 53# define STK_IIC_ENABLE_YES (0x1e) 54/* 55 * Address of the slave. Seems like the binary driver look for the 56 * sensor in multiple places, attempting a reset sequence. 57 * We only know about the ov9650 58 */ 59# define STK_IIC_ADDR (STK_IIC_BASE+3) 60# define STK_IIC_TX_INDEX (STK_IIC_BASE+4) 61# define STK_IIC_TX_VALUE (STK_IIC_BASE+5) 62# define STK_IIC_RX_INDEX (STK_IIC_BASE+8) 63# define STK_IIC_RX_VALUE (STK_IIC_BASE+9) 64 65#define MAX_RETRIES (50) 66 67#define SENSOR_ADDRESS (0x60) 68 69/* From ov7670.c (These registers aren't fully accurate) */ 70 71/* Registers */ 72#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 73#define REG_BLUE 0x01 /* blue gain */ 74#define REG_RED 0x02 /* red gain */ 75#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 76#define REG_COM1 0x04 /* Control 1 */ 77#define COM1_CCIR656 0x40 /* CCIR656 enable */ 78#define COM1_QFMT 0x20 /* QVGA/QCIF format */ 79#define COM1_SKIP_0 0x00 /* Do not skip any row */ 80#define COM1_SKIP_2 0x04 /* Skip 2 rows of 4 */ 81#define COM1_SKIP_3 0x08 /* Skip 3 rows of 4 */ 82#define REG_BAVE 0x05 /* U/B Average level */ 83#define REG_GbAVE 0x06 /* Y/Gb Average level */ 84#define REG_AECHH 0x07 /* AEC MS 5 bits */ 85#define REG_RAVE 0x08 /* V/R Average level */ 86#define REG_COM2 0x09 /* Control 2 */ 87#define COM2_SSLEEP 0x10 /* Soft sleep mode */ 88#define REG_PID 0x0a /* Product ID MSB */ 89#define REG_VER 0x0b /* Product ID LSB */ 90#define REG_COM3 0x0c /* Control 3 */ 91#define COM3_SWAP 0x40 /* Byte swap */ 92#define COM3_SCALEEN 0x08 /* Enable scaling */ 93#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 94#define REG_COM4 0x0d /* Control 4 */ 95#define REG_COM5 0x0e /* All "reserved" */ 96#define REG_COM6 0x0f /* Control 6 */ 97#define REG_AECH 0x10 /* More bits of AEC value */ 98#define REG_CLKRC 0x11 /* Clock control */ 99#define CLK_PLL 0x80 /* Enable internal PLL */ 100#define CLK_EXT 0x40 /* Use external clock directly */ 101#define CLK_SCALE 0x3f /* Mask for internal clock scale */ 102#define REG_COM7 0x12 /* Control 7 */ 103#define COM7_RESET 0x80 /* Register reset */ 104#define COM7_FMT_MASK 0x38 105#define COM7_FMT_SXGA 0x00 106#define COM7_FMT_VGA 0x40 107#define COM7_FMT_CIF 0x20 /* CIF format */ 108#define COM7_FMT_QVGA 0x10 /* QVGA format */ 109#define COM7_FMT_QCIF 0x08 /* QCIF format */ 110#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 111#define COM7_YUV 0x00 /* YUV */ 112#define COM7_BAYER 0x01 /* Bayer format */ 113#define COM7_PBAYER 0x05 /* "Processed bayer" */ 114#define REG_COM8 0x13 /* Control 8 */ 115#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 116#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 117#define COM8_BFILT 0x20 /* Band filter enable */ 118#define COM8_AGC 0x04 /* Auto gain enable */ 119#define COM8_AWB 0x02 /* White balance enable */ 120#define COM8_AEC 0x01 /* Auto exposure enable */ 121#define REG_COM9 0x14 /* Control 9 - gain ceiling */ 122#define REG_COM10 0x15 /* Control 10 */ 123#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 124#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 125#define COM10_HREF_REV 0x08 /* Reverse HREF */ 126#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 127#define COM10_VS_NEG 0x02 /* VSYNC negative */ 128#define COM10_HS_NEG 0x01 /* HSYNC negative */ 129#define REG_HSTART 0x17 /* Horiz start high bits */ 130#define REG_HSTOP 0x18 /* Horiz stop high bits */ 131#define REG_VSTART 0x19 /* Vert start high bits */ 132#define REG_VSTOP 0x1a /* Vert stop high bits */ 133#define REG_PSHFT 0x1b /* Pixel delay after HREF */ 134#define REG_MIDH 0x1c /* Manuf. ID high */ 135#define REG_MIDL 0x1d /* Manuf. ID low */ 136#define REG_MVFP 0x1e /* Mirror / vflip */ 137#define MVFP_MIRROR 0x20 /* Mirror image */ 138#define MVFP_FLIP 0x10 /* Vertical flip */ 139 140#define REG_AEW 0x24 /* AGC upper limit */ 141#define REG_AEB 0x25 /* AGC lower limit */ 142#define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 143#define REG_ADVFL 0x2d /* Insert dummy lines (LSB) */ 144#define REG_ADVFH 0x2e /* Insert dummy lines (MSB) */ 145#define REG_HSYST 0x30 /* HSYNC rising edge delay */ 146#define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 147#define REG_HREF 0x32 /* HREF pieces */ 148#define REG_TSLB 0x3a /* lots of stuff */ 149#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 150#define TSLB_BYTEORD 0x08 /* swap bytes in 16bit mode? */ 151#define REG_COM11 0x3b /* Control 11 */ 152#define COM11_NIGHT 0x80 /* NIght mode enable */ 153#define COM11_NMFR 0x60 /* Two bit NM frame rate */ 154#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 155#define COM11_50HZ 0x08 /* Manual 50Hz select */ 156#define COM11_EXP 0x02 157#define REG_COM12 0x3c /* Control 12 */ 158#define COM12_HREF 0x80 /* HREF always */ 159#define REG_COM13 0x3d /* Control 13 */ 160#define COM13_GAMMA 0x80 /* Gamma enable */ 161#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 162#define COM13_CMATRIX 0x10 /* Enable color matrix for RGB or YUV */ 163#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 164#define REG_COM14 0x3e /* Control 14 */ 165#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 166#define REG_EDGE 0x3f /* Edge enhancement factor */ 167#define REG_COM15 0x40 /* Control 15 */ 168#define COM15_R10F0 0x00 /* Data range 10 to F0 */ 169#define COM15_R01FE 0x80 /* 01 to FE */ 170#define COM15_R00FF 0xc0 /* 00 to FF */ 171#define COM15_RGB565 0x10 /* RGB565 output */ 172#define COM15_RGBFIXME 0x20 /* FIXME */ 173#define COM15_RGB555 0x30 /* RGB555 output */ 174#define REG_COM16 0x41 /* Control 16 */ 175#define COM16_AWBGAIN 0x08 /* AWB gain enable */ 176#define REG_COM17 0x42 /* Control 17 */ 177#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 178#define COM17_CBAR 0x08 /* DSP Color bar */ 179 180/* 181 * This matrix defines how the colors are generated, must be 182 * tweaked to adjust hue and saturation. 183 * 184 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 185 * 186 * They are nine-bit signed quantities, with the sign bit 187 * stored in 0x58. Sign for v-red is bit 0, and up from there. 188 */ 189#define REG_CMATRIX_BASE 0x4f 190#define CMATRIX_LEN 6 191#define REG_CMATRIX_SIGN 0x58 192 193 194#define REG_BRIGHT 0x55 /* Brightness */ 195#define REG_CONTRAS 0x56 /* Contrast control */ 196 197#define REG_GFIX 0x69 /* Fix gain control */ 198 199#define REG_RGB444 0x8c /* RGB 444 control */ 200#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 201#define R444_RGBX 0x01 /* Empty nibble at end */ 202 203#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 204#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 205 206#define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 207#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 208#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 209#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 210#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 211#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 212#define REG_BD60MAX 0xab /* 60hz banding step limit */ 213 214 215 216 217/* Returns 0 if OK */ 218static int stk_sensor_outb(struct stk_camera *dev, u8 reg, u8 val) 219{ 220 int i = 0; 221 u8 tmpval = 0; 222 223 if (stk_camera_write_reg(dev, STK_IIC_TX_INDEX, reg)) 224 return 1; 225 if (stk_camera_write_reg(dev, STK_IIC_TX_VALUE, val)) 226 return 1; 227 if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_TX)) 228 return 1; 229 do { 230 if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval)) 231 return 1; 232 i++; 233 } while (tmpval == 0 && i < MAX_RETRIES); 234 if (tmpval != STK_IIC_STAT_TX_OK) { 235 if (tmpval) 236 pr_err("stk_sensor_outb failed, status=0x%02x\n", 237 tmpval); 238 return 1; 239 } else 240 return 0; 241} 242 243static int stk_sensor_inb(struct stk_camera *dev, u8 reg, u8 *val) 244{ 245 int i = 0; 246 u8 tmpval = 0; 247 248 if (stk_camera_write_reg(dev, STK_IIC_RX_INDEX, reg)) 249 return 1; 250 if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_RX)) 251 return 1; 252 do { 253 if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval)) 254 return 1; 255 i++; 256 } while (tmpval == 0 && i < MAX_RETRIES); 257 if (tmpval != STK_IIC_STAT_RX_OK) { 258 if (tmpval) 259 pr_err("stk_sensor_inb failed, status=0x%02x\n", 260 tmpval); 261 return 1; 262 } 263 264 if (stk_camera_read_reg(dev, STK_IIC_RX_VALUE, &tmpval)) 265 return 1; 266 267 *val = tmpval; 268 return 0; 269} 270 271static int stk_sensor_write_regvals(struct stk_camera *dev, 272 struct regval *rv) 273{ 274 int ret; 275 if (rv == NULL) 276 return 0; 277 while (rv->reg != 0xff || rv->val != 0xff) { 278 ret = stk_sensor_outb(dev, rv->reg, rv->val); 279 if (ret != 0) 280 return ret; 281 rv++; 282 } 283 return 0; 284} 285 286int stk_sensor_sleep(struct stk_camera *dev) 287{ 288 u8 tmp; 289 return stk_sensor_inb(dev, REG_COM2, &tmp) 290 || stk_sensor_outb(dev, REG_COM2, tmp|COM2_SSLEEP); 291} 292 293int stk_sensor_wakeup(struct stk_camera *dev) 294{ 295 u8 tmp; 296 return stk_sensor_inb(dev, REG_COM2, &tmp) 297 || stk_sensor_outb(dev, REG_COM2, tmp&~COM2_SSLEEP); 298} 299 300static struct regval ov_initvals[] = { 301 {REG_CLKRC, CLK_PLL}, 302 {REG_COM11, 0x01}, 303 {0x6a, 0x7d}, 304 {REG_AECH, 0x40}, 305 {REG_GAIN, 0x00}, 306 {REG_BLUE, 0x80}, 307 {REG_RED, 0x80}, 308 /* Do not enable fast AEC for now */ 309 /*{REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC},*/ 310 {REG_COM8, COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC}, 311 {0x39, 0x50}, {0x38, 0x93}, 312 {0x37, 0x00}, {0x35, 0x81}, 313 {REG_COM5, 0x20}, 314 {REG_COM1, 0x00}, 315 {REG_COM3, 0x00}, 316 {REG_COM4, 0x00}, 317 {REG_PSHFT, 0x00}, 318 {0x16, 0x07}, 319 {0x33, 0xe2}, {0x34, 0xbf}, 320 {REG_COM16, 0x00}, 321 {0x96, 0x04}, 322 /* Gamma curve values */ 323/* { 0x7a, 0x20 }, { 0x7b, 0x10 }, 324 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 325 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 326 { 0x80, 0x76 }, { 0x81, 0x80 }, 327 { 0x82, 0x88 }, { 0x83, 0x8f }, 328 { 0x84, 0x96 }, { 0x85, 0xa3 }, 329 { 0x86, 0xaf }, { 0x87, 0xc4 }, 330 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 331*/ 332 {REG_GFIX, 0x40}, 333 {0x8e, 0x00}, 334 {REG_COM12, 0x73}, 335 {0x8f, 0xdf}, {0x8b, 0x06}, 336 {0x8c, 0x20}, 337 {0x94, 0x88}, {0x95, 0x88}, 338/* {REG_COM15, 0xc1}, TODO */ 339 {0x29, 0x3f}, 340 {REG_COM6, 0x42}, 341 {REG_BD50MAX, 0x80}, 342 {REG_HAECC6, 0xb8}, {REG_HAECC7, 0x92}, 343 {REG_BD60MAX, 0x0a}, 344 {0x90, 0x00}, {0x91, 0x00}, 345 {REG_HAECC1, 0x00}, {REG_HAECC2, 0x00}, 346 {REG_AEW, 0x68}, {REG_AEB, 0x5c}, 347 {REG_VPT, 0xc3}, 348 {REG_COM9, 0x2e}, 349 {0x2a, 0x00}, {0x2b, 0x00}, 350 351 {0xff, 0xff}, /* END MARKER */ 352}; 353 354/* Probe the I2C bus and initialise the sensor chip */ 355int stk_sensor_init(struct stk_camera *dev) 356{ 357 u8 idl = 0; 358 u8 idh = 0; 359 360 if (stk_camera_write_reg(dev, STK_IIC_ENABLE, STK_IIC_ENABLE_YES) 361 || stk_camera_write_reg(dev, STK_IIC_ADDR, SENSOR_ADDRESS) 362 || stk_sensor_outb(dev, REG_COM7, COM7_RESET)) { 363 pr_err("Sensor resetting failed\n"); 364 return -ENODEV; 365 } 366 msleep(10); 367 /* Read the manufacturer ID: ov = 0x7FA2 */ 368 if (stk_sensor_inb(dev, REG_MIDH, &idh) 369 || stk_sensor_inb(dev, REG_MIDL, &idl)) { 370 pr_err("Strange error reading sensor ID\n"); 371 return -ENODEV; 372 } 373 if (idh != 0x7f || idl != 0xa2) { 374 pr_err("Huh? you don't have a sensor from ovt\n"); 375 return -ENODEV; 376 } 377 if (stk_sensor_inb(dev, REG_PID, &idh) 378 || stk_sensor_inb(dev, REG_VER, &idl)) { 379 pr_err("Could not read sensor model\n"); 380 return -ENODEV; 381 } 382 stk_sensor_write_regvals(dev, ov_initvals); 383 msleep(10); 384 pr_info("OmniVision sensor detected, id %02X%02X at address %x\n", 385 idh, idl, SENSOR_ADDRESS); 386 return 0; 387} 388 389/* V4L2_PIX_FMT_UYVY */ 390static struct regval ov_fmt_uyvy[] = { 391 {REG_TSLB, TSLB_YLAST|0x08 }, 392 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 393 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 394 { 0x51, 0 }, /* vb */ 395 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 396 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 397 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 398 {REG_COM13, COM13_UVSAT|COM13_CMATRIX}, 399 {REG_COM15, COM15_R00FF }, 400 {0xff, 0xff}, /* END MARKER */ 401}; 402/* V4L2_PIX_FMT_YUYV */ 403static struct regval ov_fmt_yuyv[] = { 404 {REG_TSLB, 0 }, 405 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 406 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 407 { 0x51, 0 }, /* vb */ 408 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 409 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 410 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 411 {REG_COM13, COM13_UVSAT|COM13_CMATRIX}, 412 {REG_COM15, COM15_R00FF }, 413 {0xff, 0xff}, /* END MARKER */ 414}; 415 416/* V4L2_PIX_FMT_RGB565X rrrrrggg gggbbbbb */ 417static struct regval ov_fmt_rgbr[] = { 418 { REG_RGB444, 0 }, /* No RGB444 please */ 419 {REG_TSLB, 0x00}, 420 { REG_COM1, 0x0 }, 421 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 422 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 423 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 424 { 0x51, 0 }, /* vb */ 425 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 426 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 427 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 428 { REG_COM13, COM13_GAMMA }, 429 { REG_COM15, COM15_RGB565|COM15_R00FF }, 430 { 0xff, 0xff }, 431}; 432 433/* V4L2_PIX_FMT_RGB565 gggbbbbb rrrrrggg */ 434static struct regval ov_fmt_rgbp[] = { 435 { REG_RGB444, 0 }, /* No RGB444 please */ 436 {REG_TSLB, TSLB_BYTEORD }, 437 { REG_COM1, 0x0 }, 438 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 439 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 440 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 441 { 0x51, 0 }, /* vb */ 442 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 443 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 444 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 445 { REG_COM13, COM13_GAMMA }, 446 { REG_COM15, COM15_RGB565|COM15_R00FF }, 447 { 0xff, 0xff }, 448}; 449 450/* V4L2_PIX_FMT_SRGGB8 */ 451static struct regval ov_fmt_bayer[] = { 452 /* This changes color order */ 453 {REG_TSLB, 0x40}, /* BGGR */ 454 /* {REG_TSLB, 0x08}, */ /* BGGR with vertical image flipping */ 455 {REG_COM15, COM15_R00FF }, 456 {0xff, 0xff}, /* END MARKER */ 457}; 458/* 459 * Store a set of start/stop values into the camera. 460 */ 461static int stk_sensor_set_hw(struct stk_camera *dev, 462 int hstart, int hstop, int vstart, int vstop) 463{ 464 int ret; 465 unsigned char v; 466/* 467 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 468 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 469 * a mystery "edge offset" value in the top two bits of href. 470 */ 471 ret = stk_sensor_outb(dev, REG_HSTART, (hstart >> 3) & 0xff); 472 ret += stk_sensor_outb(dev, REG_HSTOP, (hstop >> 3) & 0xff); 473 ret += stk_sensor_inb(dev, REG_HREF, &v); 474 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 475 msleep(10); 476 ret += stk_sensor_outb(dev, REG_HREF, v); 477/* 478 * Vertical: similar arrangement (note: this is different from ov7670.c) 479 */ 480 ret += stk_sensor_outb(dev, REG_VSTART, (vstart >> 3) & 0xff); 481 ret += stk_sensor_outb(dev, REG_VSTOP, (vstop >> 3) & 0xff); 482 ret += stk_sensor_inb(dev, REG_VREF, &v); 483 v = (v & 0xc0) | ((vstop & 0x7) << 3) | (vstart & 0x7); 484 msleep(10); 485 ret += stk_sensor_outb(dev, REG_VREF, v); 486 return ret; 487} 488 489 490int stk_sensor_configure(struct stk_camera *dev) 491{ 492 int com7; 493 /* 494 * We setup the sensor to output dummy lines in low-res modes, 495 * so we don't get absurdly hight framerates. 496 */ 497 unsigned dummylines; 498 int flip; 499 struct regval *rv; 500 501 switch (dev->vsettings.mode) { 502 case MODE_QCIF: com7 = COM7_FMT_QCIF; 503 dummylines = 604; 504 break; 505 case MODE_QVGA: com7 = COM7_FMT_QVGA; 506 dummylines = 267; 507 break; 508 case MODE_CIF: com7 = COM7_FMT_CIF; 509 dummylines = 412; 510 break; 511 case MODE_VGA: com7 = COM7_FMT_VGA; 512 dummylines = 11; 513 break; 514 case MODE_SXGA: com7 = COM7_FMT_SXGA; 515 dummylines = 0; 516 break; 517 default: 518 pr_err("Unsupported mode %d\n", dev->vsettings.mode); 519 return -EFAULT; 520 } 521 switch (dev->vsettings.palette) { 522 case V4L2_PIX_FMT_UYVY: 523 com7 |= COM7_YUV; 524 rv = ov_fmt_uyvy; 525 break; 526 case V4L2_PIX_FMT_YUYV: 527 com7 |= COM7_YUV; 528 rv = ov_fmt_yuyv; 529 break; 530 case V4L2_PIX_FMT_RGB565: 531 com7 |= COM7_RGB; 532 rv = ov_fmt_rgbp; 533 break; 534 case V4L2_PIX_FMT_RGB565X: 535 com7 |= COM7_RGB; 536 rv = ov_fmt_rgbr; 537 break; 538 case V4L2_PIX_FMT_SBGGR8: 539 com7 |= COM7_PBAYER; 540 rv = ov_fmt_bayer; 541 break; 542 default: 543 pr_err("Unsupported colorspace\n"); 544 return -EFAULT; 545 } 546 /*FIXME sometimes the sensor go to a bad state 547 stk_sensor_write_regvals(dev, ov_initvals); */ 548 stk_sensor_outb(dev, REG_COM7, com7); 549 msleep(50); 550 stk_sensor_write_regvals(dev, rv); 551 flip = (dev->vsettings.vflip?MVFP_FLIP:0) 552 | (dev->vsettings.hflip?MVFP_MIRROR:0); 553 stk_sensor_outb(dev, REG_MVFP, flip); 554 if (dev->vsettings.palette == V4L2_PIX_FMT_SBGGR8 555 && !dev->vsettings.vflip) 556 stk_sensor_outb(dev, REG_TSLB, 0x08); 557 stk_sensor_outb(dev, REG_ADVFH, dummylines >> 8); 558 stk_sensor_outb(dev, REG_ADVFL, dummylines & 0xff); 559 msleep(50); 560 switch (dev->vsettings.mode) { 561 case MODE_VGA: 562 if (stk_sensor_set_hw(dev, 302, 1582, 6, 486)) 563 pr_err("stk_sensor_set_hw failed (VGA)\n"); 564 break; 565 case MODE_SXGA: 566 case MODE_CIF: 567 case MODE_QVGA: 568 case MODE_QCIF: 569 /*FIXME These settings seem ignored by the sensor 570 if (stk_sensor_set_hw(dev, 220, 1500, 10, 1034)) 571 pr_err("stk_sensor_set_hw failed (SXGA)\n"); 572 */ 573 break; 574 } 575 msleep(10); 576 return 0; 577} 578 579int stk_sensor_set_brightness(struct stk_camera *dev, int br) 580{ 581 if (br < 0 || br > 0xff) 582 return -EINVAL; 583 stk_sensor_outb(dev, REG_AEB, max(0x00, br - 6)); 584 stk_sensor_outb(dev, REG_AEW, min(0xff, br + 6)); 585 return 0; 586} 587 588