18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Xilinx Video Timing Controller 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2013-2015 Ideas on Board 68c2ecf20Sopenharmony_ci * Copyright (C) 2013-2015 Xilinx, Inc. 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 98c2ecf20Sopenharmony_ci * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 108c2ecf20Sopenharmony_ci */ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#ifndef __XILINX_VTC_H__ 138c2ecf20Sopenharmony_ci#define __XILINX_VTC_H__ 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_cistruct device_node; 168c2ecf20Sopenharmony_cistruct xvtc_device; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci#define XVTC_MAX_HSIZE 8191 198c2ecf20Sopenharmony_ci#define XVTC_MAX_VSIZE 8191 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_cistruct xvtc_config { 228c2ecf20Sopenharmony_ci unsigned int hblank_start; 238c2ecf20Sopenharmony_ci unsigned int hsync_start; 248c2ecf20Sopenharmony_ci unsigned int hsync_end; 258c2ecf20Sopenharmony_ci unsigned int hsize; 268c2ecf20Sopenharmony_ci unsigned int vblank_start; 278c2ecf20Sopenharmony_ci unsigned int vsync_start; 288c2ecf20Sopenharmony_ci unsigned int vsync_end; 298c2ecf20Sopenharmony_ci unsigned int vsize; 308c2ecf20Sopenharmony_ci}; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_cistruct xvtc_device *xvtc_of_get(struct device_node *np); 338c2ecf20Sopenharmony_civoid xvtc_put(struct xvtc_device *xvtc); 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ciint xvtc_generator_start(struct xvtc_device *xvtc, 368c2ecf20Sopenharmony_ci const struct xvtc_config *config); 378c2ecf20Sopenharmony_ciint xvtc_generator_stop(struct xvtc_device *xvtc); 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci#endif /* __XILINX_VTC_H__ */ 40