1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <linux/delay.h> 9#include <linux/interrupt.h> 10#include <linux/io.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/of_device.h> 14#include <linux/of_graph.h> 15#include <linux/platform_device.h> 16#include <linux/pm_runtime.h> 17#include <linux/reset.h> 18#include <linux/sys_soc.h> 19 20#include <media/v4l2-ctrls.h> 21#include <media/v4l2-device.h> 22#include <media/v4l2-fwnode.h> 23#include <media/v4l2-mc.h> 24#include <media/v4l2-subdev.h> 25 26struct rcar_csi2; 27 28/* Register offsets and bits */ 29 30/* Control Timing Select */ 31#define TREF_REG 0x00 32#define TREF_TREF BIT(0) 33 34/* Software Reset */ 35#define SRST_REG 0x04 36#define SRST_SRST BIT(0) 37 38/* PHY Operation Control */ 39#define PHYCNT_REG 0x08 40#define PHYCNT_SHUTDOWNZ BIT(17) 41#define PHYCNT_RSTZ BIT(16) 42#define PHYCNT_ENABLECLK BIT(4) 43#define PHYCNT_ENABLE_3 BIT(3) 44#define PHYCNT_ENABLE_2 BIT(2) 45#define PHYCNT_ENABLE_1 BIT(1) 46#define PHYCNT_ENABLE_0 BIT(0) 47 48/* Checksum Control */ 49#define CHKSUM_REG 0x0c 50#define CHKSUM_ECC_EN BIT(1) 51#define CHKSUM_CRC_EN BIT(0) 52 53/* 54 * Channel Data Type Select 55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 57 */ 58#define VCDT_REG 0x10 59#define VCDT2_REG 0x14 60#define VCDT_VCDTN_EN BIT(15) 61#define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 62#define VCDT_SEL_DTN_ON BIT(6) 63#define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 64 65/* Frame Data Type Select */ 66#define FRDT_REG 0x18 67 68/* Field Detection Control */ 69#define FLD_REG 0x1c 70#define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 71#define FLD_DET_SEL(n) (((n) & 0x3) << 4) 72#define FLD_FLD_EN4 BIT(3) 73#define FLD_FLD_EN3 BIT(2) 74#define FLD_FLD_EN2 BIT(1) 75#define FLD_FLD_EN BIT(0) 76 77/* Automatic Standby Control */ 78#define ASTBY_REG 0x20 79 80/* Long Data Type Setting 0 */ 81#define LNGDT0_REG 0x28 82 83/* Long Data Type Setting 1 */ 84#define LNGDT1_REG 0x2c 85 86/* Interrupt Enable */ 87#define INTEN_REG 0x30 88#define INTEN_INT_AFIFO_OF BIT(27) 89#define INTEN_INT_ERRSOTHS BIT(4) 90#define INTEN_INT_ERRSOTSYNCHS BIT(3) 91 92/* Interrupt Source Mask */ 93#define INTCLOSE_REG 0x34 94 95/* Interrupt Status Monitor */ 96#define INTSTATE_REG 0x38 97#define INTSTATE_INT_ULPS_START BIT(7) 98#define INTSTATE_INT_ULPS_END BIT(6) 99 100/* Interrupt Error Status Monitor */ 101#define INTERRSTATE_REG 0x3c 102 103/* Short Packet Data */ 104#define SHPDAT_REG 0x40 105 106/* Short Packet Count */ 107#define SHPCNT_REG 0x44 108 109/* LINK Operation Control */ 110#define LINKCNT_REG 0x48 111#define LINKCNT_MONITOR_EN BIT(31) 112#define LINKCNT_REG_MONI_PACT_EN BIT(25) 113#define LINKCNT_ICLK_NONSTOP BIT(24) 114 115/* Lane Swap */ 116#define LSWAP_REG 0x4c 117#define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 118#define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 119#define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 120#define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 121 122/* PHY Test Interface Write Register */ 123#define PHTW_REG 0x50 124#define PHTW_DWEN BIT(24) 125#define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 126#define PHTW_CWEN BIT(8) 127#define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 128 129struct phtw_value { 130 u16 data; 131 u16 code; 132}; 133 134struct rcsi2_mbps_reg { 135 u16 mbps; 136 u16 reg; 137}; 138 139static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = { 140 { .mbps = 80, .reg = 0x86 }, 141 { .mbps = 90, .reg = 0x86 }, 142 { .mbps = 100, .reg = 0x87 }, 143 { .mbps = 110, .reg = 0x87 }, 144 { .mbps = 120, .reg = 0x88 }, 145 { .mbps = 130, .reg = 0x88 }, 146 { .mbps = 140, .reg = 0x89 }, 147 { .mbps = 150, .reg = 0x89 }, 148 { .mbps = 160, .reg = 0x8a }, 149 { .mbps = 170, .reg = 0x8a }, 150 { .mbps = 180, .reg = 0x8b }, 151 { .mbps = 190, .reg = 0x8b }, 152 { .mbps = 205, .reg = 0x8c }, 153 { .mbps = 220, .reg = 0x8d }, 154 { .mbps = 235, .reg = 0x8e }, 155 { .mbps = 250, .reg = 0x8e }, 156 { /* sentinel */ }, 157}; 158 159static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = { 160 { .mbps = 80, .reg = 0x00 }, 161 { .mbps = 90, .reg = 0x20 }, 162 { .mbps = 100, .reg = 0x40 }, 163 { .mbps = 110, .reg = 0x02 }, 164 { .mbps = 130, .reg = 0x22 }, 165 { .mbps = 140, .reg = 0x42 }, 166 { .mbps = 150, .reg = 0x04 }, 167 { .mbps = 170, .reg = 0x24 }, 168 { .mbps = 180, .reg = 0x44 }, 169 { .mbps = 200, .reg = 0x06 }, 170 { .mbps = 220, .reg = 0x26 }, 171 { .mbps = 240, .reg = 0x46 }, 172 { .mbps = 250, .reg = 0x08 }, 173 { .mbps = 270, .reg = 0x28 }, 174 { .mbps = 300, .reg = 0x0a }, 175 { .mbps = 330, .reg = 0x2a }, 176 { .mbps = 360, .reg = 0x4a }, 177 { .mbps = 400, .reg = 0x0c }, 178 { .mbps = 450, .reg = 0x2c }, 179 { .mbps = 500, .reg = 0x0e }, 180 { .mbps = 550, .reg = 0x2e }, 181 { .mbps = 600, .reg = 0x10 }, 182 { .mbps = 650, .reg = 0x30 }, 183 { .mbps = 700, .reg = 0x12 }, 184 { .mbps = 750, .reg = 0x32 }, 185 { .mbps = 800, .reg = 0x52 }, 186 { .mbps = 850, .reg = 0x72 }, 187 { .mbps = 900, .reg = 0x14 }, 188 { .mbps = 950, .reg = 0x34 }, 189 { .mbps = 1000, .reg = 0x54 }, 190 { .mbps = 1050, .reg = 0x74 }, 191 { .mbps = 1125, .reg = 0x16 }, 192 { /* sentinel */ }, 193}; 194 195/* PHY Test Interface Clear */ 196#define PHTC_REG 0x58 197#define PHTC_TESTCLR BIT(0) 198 199/* PHY Frequency Control */ 200#define PHYPLL_REG 0x68 201#define PHYPLL_HSFREQRANGE(n) ((n) << 16) 202 203static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = { 204 { .mbps = 80, .reg = 0x00 }, 205 { .mbps = 90, .reg = 0x10 }, 206 { .mbps = 100, .reg = 0x20 }, 207 { .mbps = 110, .reg = 0x30 }, 208 { .mbps = 120, .reg = 0x01 }, 209 { .mbps = 130, .reg = 0x11 }, 210 { .mbps = 140, .reg = 0x21 }, 211 { .mbps = 150, .reg = 0x31 }, 212 { .mbps = 160, .reg = 0x02 }, 213 { .mbps = 170, .reg = 0x12 }, 214 { .mbps = 180, .reg = 0x22 }, 215 { .mbps = 190, .reg = 0x32 }, 216 { .mbps = 205, .reg = 0x03 }, 217 { .mbps = 220, .reg = 0x13 }, 218 { .mbps = 235, .reg = 0x23 }, 219 { .mbps = 250, .reg = 0x33 }, 220 { .mbps = 275, .reg = 0x04 }, 221 { .mbps = 300, .reg = 0x14 }, 222 { .mbps = 325, .reg = 0x25 }, 223 { .mbps = 350, .reg = 0x35 }, 224 { .mbps = 400, .reg = 0x05 }, 225 { .mbps = 450, .reg = 0x16 }, 226 { .mbps = 500, .reg = 0x26 }, 227 { .mbps = 550, .reg = 0x37 }, 228 { .mbps = 600, .reg = 0x07 }, 229 { .mbps = 650, .reg = 0x18 }, 230 { .mbps = 700, .reg = 0x28 }, 231 { .mbps = 750, .reg = 0x39 }, 232 { .mbps = 800, .reg = 0x09 }, 233 { .mbps = 850, .reg = 0x19 }, 234 { .mbps = 900, .reg = 0x29 }, 235 { .mbps = 950, .reg = 0x3a }, 236 { .mbps = 1000, .reg = 0x0a }, 237 { .mbps = 1050, .reg = 0x1a }, 238 { .mbps = 1100, .reg = 0x2a }, 239 { .mbps = 1150, .reg = 0x3b }, 240 { .mbps = 1200, .reg = 0x0b }, 241 { .mbps = 1250, .reg = 0x1b }, 242 { .mbps = 1300, .reg = 0x2b }, 243 { .mbps = 1350, .reg = 0x3c }, 244 { .mbps = 1400, .reg = 0x0c }, 245 { .mbps = 1450, .reg = 0x1c }, 246 { .mbps = 1500, .reg = 0x2c }, 247 { /* sentinel */ }, 248}; 249 250static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = { 251 { .mbps = 80, .reg = 0x00 }, 252 { .mbps = 90, .reg = 0x10 }, 253 { .mbps = 100, .reg = 0x20 }, 254 { .mbps = 110, .reg = 0x30 }, 255 { .mbps = 120, .reg = 0x01 }, 256 { .mbps = 130, .reg = 0x11 }, 257 { .mbps = 140, .reg = 0x21 }, 258 { .mbps = 150, .reg = 0x31 }, 259 { .mbps = 160, .reg = 0x02 }, 260 { .mbps = 170, .reg = 0x12 }, 261 { .mbps = 180, .reg = 0x22 }, 262 { .mbps = 190, .reg = 0x32 }, 263 { .mbps = 205, .reg = 0x03 }, 264 { .mbps = 220, .reg = 0x13 }, 265 { .mbps = 235, .reg = 0x23 }, 266 { .mbps = 250, .reg = 0x33 }, 267 { .mbps = 275, .reg = 0x04 }, 268 { .mbps = 300, .reg = 0x14 }, 269 { .mbps = 325, .reg = 0x05 }, 270 { .mbps = 350, .reg = 0x15 }, 271 { .mbps = 400, .reg = 0x25 }, 272 { .mbps = 450, .reg = 0x06 }, 273 { .mbps = 500, .reg = 0x16 }, 274 { .mbps = 550, .reg = 0x07 }, 275 { .mbps = 600, .reg = 0x17 }, 276 { .mbps = 650, .reg = 0x08 }, 277 { .mbps = 700, .reg = 0x18 }, 278 { .mbps = 750, .reg = 0x09 }, 279 { .mbps = 800, .reg = 0x19 }, 280 { .mbps = 850, .reg = 0x29 }, 281 { .mbps = 900, .reg = 0x39 }, 282 { .mbps = 950, .reg = 0x0a }, 283 { .mbps = 1000, .reg = 0x1a }, 284 { .mbps = 1050, .reg = 0x2a }, 285 { .mbps = 1100, .reg = 0x3a }, 286 { .mbps = 1150, .reg = 0x0b }, 287 { .mbps = 1200, .reg = 0x1b }, 288 { .mbps = 1250, .reg = 0x2b }, 289 { .mbps = 1300, .reg = 0x3b }, 290 { .mbps = 1350, .reg = 0x0c }, 291 { .mbps = 1400, .reg = 0x1c }, 292 { .mbps = 1450, .reg = 0x2c }, 293 { .mbps = 1500, .reg = 0x3c }, 294 { /* sentinel */ }, 295}; 296 297/* PHY ESC Error Monitor */ 298#define PHEERM_REG 0x74 299 300/* PHY Clock Lane Monitor */ 301#define PHCLM_REG 0x78 302#define PHCLM_STOPSTATECKL BIT(0) 303 304/* PHY Data Lane Monitor */ 305#define PHDLM_REG 0x7c 306 307/* CSI0CLK Frequency Configuration Preset Register */ 308#define CSI0CLKFCPR_REG 0x260 309#define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 310 311struct rcar_csi2_format { 312 u32 code; 313 unsigned int datatype; 314 unsigned int bpp; 315}; 316 317static const struct rcar_csi2_format rcar_csi2_formats[] = { 318 { .code = MEDIA_BUS_FMT_RGB888_1X24, .datatype = 0x24, .bpp = 24 }, 319 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 }, 320 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .datatype = 0x1e, .bpp = 16 }, 321 { .code = MEDIA_BUS_FMT_UYVY8_2X8, .datatype = 0x1e, .bpp = 16 }, 322 { .code = MEDIA_BUS_FMT_YUYV10_2X10, .datatype = 0x1e, .bpp = 20 }, 323 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .datatype = 0x2a, .bpp = 8 }, 324 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .datatype = 0x2a, .bpp = 8 }, 325 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .datatype = 0x2a, .bpp = 8 }, 326 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .datatype = 0x2a, .bpp = 8 }, 327}; 328 329static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 330{ 331 unsigned int i; 332 333 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 334 if (rcar_csi2_formats[i].code == code) 335 return &rcar_csi2_formats[i]; 336 337 return NULL; 338} 339 340enum rcar_csi2_pads { 341 RCAR_CSI2_SINK, 342 RCAR_CSI2_SOURCE_VC0, 343 RCAR_CSI2_SOURCE_VC1, 344 RCAR_CSI2_SOURCE_VC2, 345 RCAR_CSI2_SOURCE_VC3, 346 NR_OF_RCAR_CSI2_PAD, 347}; 348 349struct rcar_csi2_info { 350 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 351 int (*phy_post_init)(struct rcar_csi2 *priv); 352 const struct rcsi2_mbps_reg *hsfreqrange; 353 unsigned int csi0clkfreqrange; 354 unsigned int num_channels; 355 bool clear_ulps; 356}; 357 358struct rcar_csi2 { 359 struct device *dev; 360 void __iomem *base; 361 const struct rcar_csi2_info *info; 362 struct reset_control *rstc; 363 364 struct v4l2_subdev subdev; 365 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 366 367 struct v4l2_async_notifier notifier; 368 struct v4l2_subdev *remote; 369 unsigned int remote_pad; 370 371 struct v4l2_mbus_framefmt mf; 372 373 struct mutex lock; 374 int stream_count; 375 376 unsigned short lanes; 377 unsigned char lane_swap[4]; 378}; 379 380static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 381{ 382 return container_of(sd, struct rcar_csi2, subdev); 383} 384 385static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 386{ 387 return container_of(n, struct rcar_csi2, notifier); 388} 389 390static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 391{ 392 return ioread32(priv->base + reg); 393} 394 395static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 396{ 397 iowrite32(data, priv->base + reg); 398} 399 400static void rcsi2_enter_standby(struct rcar_csi2 *priv) 401{ 402 rcsi2_write(priv, PHYCNT_REG, 0); 403 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 404 reset_control_assert(priv->rstc); 405 usleep_range(100, 150); 406 pm_runtime_put(priv->dev); 407} 408 409static void rcsi2_exit_standby(struct rcar_csi2 *priv) 410{ 411 pm_runtime_get_sync(priv->dev); 412 reset_control_deassert(priv->rstc); 413} 414 415static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 416 unsigned int lanes) 417{ 418 unsigned int timeout; 419 420 /* Wait for the clock and data lanes to enter LP-11 state. */ 421 for (timeout = 0; timeout <= 20; timeout++) { 422 const u32 lane_mask = (1 << lanes) - 1; 423 424 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 425 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 426 return 0; 427 428 usleep_range(1000, 2000); 429 } 430 431 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 432 433 return -ETIMEDOUT; 434} 435 436static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 437{ 438 const struct rcsi2_mbps_reg *hsfreq; 439 const struct rcsi2_mbps_reg *hsfreq_prev = NULL; 440 441 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) { 442 if (hsfreq->mbps >= mbps) 443 break; 444 hsfreq_prev = hsfreq; 445 } 446 447 if (!hsfreq->mbps) { 448 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 449 return -ERANGE; 450 } 451 452 if (hsfreq_prev && 453 ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps))) 454 hsfreq = hsfreq_prev; 455 456 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg)); 457 458 return 0; 459} 460 461static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, 462 unsigned int lanes) 463{ 464 struct v4l2_subdev *source; 465 struct v4l2_ctrl *ctrl; 466 u64 mbps; 467 468 if (!priv->remote) 469 return -ENODEV; 470 471 source = priv->remote; 472 473 /* Read the pixel rate control from remote. */ 474 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE); 475 if (!ctrl) { 476 dev_err(priv->dev, "no pixel rate control in subdev %s\n", 477 source->name); 478 return -EINVAL; 479 } 480 481 /* 482 * Calculate the phypll in mbps. 483 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes) 484 * bps = link_freq * 2 485 */ 486 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp; 487 do_div(mbps, lanes * 1000000); 488 489 return mbps; 490} 491 492static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 493 unsigned int *lanes) 494{ 495 struct v4l2_mbus_config mbus_config = { 0 }; 496 unsigned int num_lanes = UINT_MAX; 497 int ret; 498 499 *lanes = priv->lanes; 500 501 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 502 priv->remote_pad, &mbus_config); 503 if (ret == -ENOIOCTLCMD) { 504 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 505 return 0; 506 } 507 508 if (ret) { 509 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 510 return ret; 511 } 512 513 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) { 514 dev_err(priv->dev, "Unsupported media bus type %u\n", 515 mbus_config.type); 516 return -EINVAL; 517 } 518 519 if (mbus_config.flags & V4L2_MBUS_CSI2_1_LANE) 520 num_lanes = 1; 521 else if (mbus_config.flags & V4L2_MBUS_CSI2_2_LANE) 522 num_lanes = 2; 523 else if (mbus_config.flags & V4L2_MBUS_CSI2_3_LANE) 524 num_lanes = 3; 525 else if (mbus_config.flags & V4L2_MBUS_CSI2_4_LANE) 526 num_lanes = 4; 527 528 if (num_lanes > priv->lanes) { 529 dev_err(priv->dev, 530 "Unsupported mbus config: too many data lanes %u\n", 531 num_lanes); 532 return -EINVAL; 533 } 534 535 *lanes = num_lanes; 536 537 return 0; 538} 539 540static int rcsi2_start_receiver(struct rcar_csi2 *priv) 541{ 542 const struct rcar_csi2_format *format; 543 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 544 unsigned int lanes; 545 unsigned int i; 546 int mbps, ret; 547 548 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 549 priv->mf.width, priv->mf.height, 550 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i'); 551 552 /* Code is validated in set_fmt. */ 553 format = rcsi2_code_to_fmt(priv->mf.code); 554 if (!format) 555 return -EINVAL; 556 557 /* 558 * Enable all supported CSI-2 channels with virtual channel and 559 * data type matching. 560 * 561 * NOTE: It's not possible to get individual datatype for each 562 * source virtual channel. Once this is possible in V4L2 563 * it should be used here. 564 */ 565 for (i = 0; i < priv->info->num_channels; i++) { 566 u32 vcdt_part; 567 568 vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON | 569 VCDT_SEL_DT(format->datatype); 570 571 /* Store in correct reg and offset. */ 572 if (i < 2) 573 vcdt |= vcdt_part << ((i % 2) * 16); 574 else 575 vcdt2 |= vcdt_part << ((i % 2) * 16); 576 } 577 578 if (priv->mf.field == V4L2_FIELD_ALTERNATE) { 579 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 580 | FLD_FLD_EN; 581 582 if (priv->mf.height == 240) 583 fld |= FLD_FLD_NUM(0); 584 else 585 fld |= FLD_FLD_NUM(1); 586 } 587 588 /* 589 * Get the number of active data lanes inspecting the remote mbus 590 * configuration. 591 */ 592 ret = rcsi2_get_active_lanes(priv, &lanes); 593 if (ret) 594 return ret; 595 596 phycnt = PHYCNT_ENABLECLK; 597 phycnt |= (1 << lanes) - 1; 598 599 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 600 if (mbps < 0) 601 return mbps; 602 603 /* Enable interrupts. */ 604 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 605 | INTEN_INT_ERRSOTSYNCHS); 606 607 /* Init */ 608 rcsi2_write(priv, TREF_REG, TREF_TREF); 609 rcsi2_write(priv, PHTC_REG, 0); 610 611 /* Configure */ 612 rcsi2_write(priv, VCDT_REG, vcdt); 613 if (vcdt2) 614 rcsi2_write(priv, VCDT2_REG, vcdt2); 615 /* Lanes are zero indexed. */ 616 rcsi2_write(priv, LSWAP_REG, 617 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 618 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 619 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 620 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 621 622 /* Start */ 623 if (priv->info->init_phtw) { 624 ret = priv->info->init_phtw(priv, mbps); 625 if (ret) 626 return ret; 627 } 628 629 if (priv->info->hsfreqrange) { 630 ret = rcsi2_set_phypll(priv, mbps); 631 if (ret) 632 return ret; 633 } 634 635 if (priv->info->csi0clkfreqrange) 636 rcsi2_write(priv, CSI0CLKFCPR_REG, 637 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 638 639 rcsi2_write(priv, PHYCNT_REG, phycnt); 640 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 641 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 642 rcsi2_write(priv, FLD_REG, fld); 643 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 644 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 645 646 ret = rcsi2_wait_phy_start(priv, lanes); 647 if (ret) 648 return ret; 649 650 /* Run post PHY start initialization, if needed. */ 651 if (priv->info->phy_post_init) { 652 ret = priv->info->phy_post_init(priv); 653 if (ret) 654 return ret; 655 } 656 657 /* Clear Ultra Low Power interrupt. */ 658 if (priv->info->clear_ulps) 659 rcsi2_write(priv, INTSTATE_REG, 660 INTSTATE_INT_ULPS_START | 661 INTSTATE_INT_ULPS_END); 662 return 0; 663} 664 665static int rcsi2_start(struct rcar_csi2 *priv) 666{ 667 int ret; 668 669 rcsi2_exit_standby(priv); 670 671 ret = rcsi2_start_receiver(priv); 672 if (ret) { 673 rcsi2_enter_standby(priv); 674 return ret; 675 } 676 677 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1); 678 if (ret) { 679 rcsi2_enter_standby(priv); 680 return ret; 681 } 682 683 return 0; 684} 685 686static void rcsi2_stop(struct rcar_csi2 *priv) 687{ 688 rcsi2_enter_standby(priv); 689 v4l2_subdev_call(priv->remote, video, s_stream, 0); 690} 691 692static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable) 693{ 694 struct rcar_csi2 *priv = sd_to_csi2(sd); 695 int ret = 0; 696 697 mutex_lock(&priv->lock); 698 699 if (!priv->remote) { 700 ret = -ENODEV; 701 goto out; 702 } 703 704 if (enable && priv->stream_count == 0) { 705 ret = rcsi2_start(priv); 706 if (ret) 707 goto out; 708 } else if (!enable && priv->stream_count == 1) { 709 rcsi2_stop(priv); 710 } 711 712 priv->stream_count += enable ? 1 : -1; 713out: 714 mutex_unlock(&priv->lock); 715 716 return ret; 717} 718 719static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 720 struct v4l2_subdev_pad_config *cfg, 721 struct v4l2_subdev_format *format) 722{ 723 struct rcar_csi2 *priv = sd_to_csi2(sd); 724 struct v4l2_mbus_framefmt *framefmt; 725 726 if (!rcsi2_code_to_fmt(format->format.code)) 727 format->format.code = rcar_csi2_formats[0].code; 728 729 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 730 priv->mf = format->format; 731 } else { 732 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0); 733 *framefmt = format->format; 734 } 735 736 return 0; 737} 738 739static int rcsi2_get_pad_format(struct v4l2_subdev *sd, 740 struct v4l2_subdev_pad_config *cfg, 741 struct v4l2_subdev_format *format) 742{ 743 struct rcar_csi2 *priv = sd_to_csi2(sd); 744 745 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) 746 format->format = priv->mf; 747 else 748 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0); 749 750 return 0; 751} 752 753static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = { 754 .s_stream = rcsi2_s_stream, 755}; 756 757static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 758 .set_fmt = rcsi2_set_pad_format, 759 .get_fmt = rcsi2_get_pad_format, 760}; 761 762static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 763 .video = &rcar_csi2_video_ops, 764 .pad = &rcar_csi2_pad_ops, 765}; 766 767static irqreturn_t rcsi2_irq(int irq, void *data) 768{ 769 struct rcar_csi2 *priv = data; 770 u32 status, err_status; 771 772 status = rcsi2_read(priv, INTSTATE_REG); 773 err_status = rcsi2_read(priv, INTERRSTATE_REG); 774 775 if (!status) 776 return IRQ_HANDLED; 777 778 rcsi2_write(priv, INTSTATE_REG, status); 779 780 if (!err_status) 781 return IRQ_HANDLED; 782 783 rcsi2_write(priv, INTERRSTATE_REG, err_status); 784 785 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 786 787 return IRQ_WAKE_THREAD; 788} 789 790static irqreturn_t rcsi2_irq_thread(int irq, void *data) 791{ 792 struct rcar_csi2 *priv = data; 793 794 mutex_lock(&priv->lock); 795 rcsi2_stop(priv); 796 usleep_range(1000, 2000); 797 if (rcsi2_start(priv)) 798 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 799 mutex_unlock(&priv->lock); 800 801 return IRQ_HANDLED; 802} 803 804/* ----------------------------------------------------------------------------- 805 * Async handling and registration of subdevices and links. 806 */ 807 808static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 809 struct v4l2_subdev *subdev, 810 struct v4l2_async_subdev *asd) 811{ 812 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 813 int pad; 814 815 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, 816 MEDIA_PAD_FL_SOURCE); 817 if (pad < 0) { 818 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 819 return pad; 820 } 821 822 priv->remote = subdev; 823 priv->remote_pad = pad; 824 825 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 826 827 return media_create_pad_link(&subdev->entity, pad, 828 &priv->subdev.entity, 0, 829 MEDIA_LNK_FL_ENABLED | 830 MEDIA_LNK_FL_IMMUTABLE); 831} 832 833static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 834 struct v4l2_subdev *subdev, 835 struct v4l2_async_subdev *asd) 836{ 837 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 838 839 priv->remote = NULL; 840 841 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 842} 843 844static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 845 .bound = rcsi2_notify_bound, 846 .unbind = rcsi2_notify_unbind, 847}; 848 849static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 850 struct v4l2_fwnode_endpoint *vep) 851{ 852 unsigned int i; 853 854 /* Only port 0 endpoint 0 is valid. */ 855 if (vep->base.port || vep->base.id) 856 return -ENOTCONN; 857 858 if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) { 859 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 860 return -EINVAL; 861 } 862 863 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 864 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 865 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n", 866 priv->lanes); 867 return -EINVAL; 868 } 869 870 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 871 priv->lane_swap[i] = i < priv->lanes ? 872 vep->bus.mipi_csi2.data_lanes[i] : i; 873 874 /* Check for valid lane number. */ 875 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 876 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 877 return -EINVAL; 878 } 879 } 880 881 return 0; 882} 883 884static int rcsi2_parse_dt(struct rcar_csi2 *priv) 885{ 886 struct v4l2_async_subdev *asd; 887 struct fwnode_handle *fwnode; 888 struct device_node *ep; 889 struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; 890 int ret; 891 892 ep = of_graph_get_endpoint_by_regs(priv->dev->of_node, 0, 0); 893 if (!ep) { 894 dev_err(priv->dev, "Not connected to subdevice\n"); 895 return -EINVAL; 896 } 897 898 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep); 899 if (ret) { 900 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 901 of_node_put(ep); 902 return -EINVAL; 903 } 904 905 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 906 if (ret) { 907 of_node_put(ep); 908 return ret; 909 } 910 911 fwnode = fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep)); 912 of_node_put(ep); 913 914 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 915 916 v4l2_async_notifier_init(&priv->notifier); 917 priv->notifier.ops = &rcar_csi2_notify_ops; 918 919 asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, fwnode, 920 sizeof(*asd)); 921 fwnode_handle_put(fwnode); 922 if (IS_ERR(asd)) 923 return PTR_ERR(asd); 924 925 ret = v4l2_async_subdev_notifier_register(&priv->subdev, 926 &priv->notifier); 927 if (ret) 928 v4l2_async_notifier_cleanup(&priv->notifier); 929 930 return ret; 931} 932 933/* ----------------------------------------------------------------------------- 934 * PHTW initialization sequences. 935 * 936 * NOTE: Magic values are from the datasheet and lack documentation. 937 */ 938 939static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code) 940{ 941 unsigned int timeout; 942 943 rcsi2_write(priv, PHTW_REG, 944 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 945 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 946 947 /* Wait for DWEN and CWEN to be cleared by hardware. */ 948 for (timeout = 0; timeout <= 20; timeout++) { 949 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN))) 950 return 0; 951 952 usleep_range(1000, 2000); 953 } 954 955 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 956 957 return -ETIMEDOUT; 958} 959 960static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 961 const struct phtw_value *values) 962{ 963 const struct phtw_value *value; 964 int ret; 965 966 for (value = values; value->data || value->code; value++) { 967 ret = rcsi2_phtw_write(priv, value->data, value->code); 968 if (ret) 969 return ret; 970 } 971 972 return 0; 973} 974 975static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 976 const struct rcsi2_mbps_reg *values, u16 code) 977{ 978 const struct rcsi2_mbps_reg *value; 979 const struct rcsi2_mbps_reg *prev_value = NULL; 980 981 for (value = values; value->mbps; value++) { 982 if (value->mbps >= mbps) 983 break; 984 prev_value = value; 985 } 986 987 if (prev_value && 988 ((mbps - prev_value->mbps) <= (value->mbps - mbps))) 989 value = prev_value; 990 991 if (!value->mbps) { 992 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 993 return -ERANGE; 994 } 995 996 return rcsi2_phtw_write(priv, value->reg, code); 997} 998 999static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 1000 unsigned int mbps) 1001{ 1002 static const struct phtw_value step1[] = { 1003 { .data = 0xcc, .code = 0xe2 }, 1004 { .data = 0x01, .code = 0xe3 }, 1005 { .data = 0x11, .code = 0xe4 }, 1006 { .data = 0x01, .code = 0xe5 }, 1007 { .data = 0x10, .code = 0x04 }, 1008 { /* sentinel */ }, 1009 }; 1010 1011 static const struct phtw_value step2[] = { 1012 { .data = 0x38, .code = 0x08 }, 1013 { .data = 0x01, .code = 0x00 }, 1014 { .data = 0x4b, .code = 0xac }, 1015 { .data = 0x03, .code = 0x00 }, 1016 { .data = 0x80, .code = 0x07 }, 1017 { /* sentinel */ }, 1018 }; 1019 1020 int ret; 1021 1022 ret = rcsi2_phtw_write_array(priv, step1); 1023 if (ret) 1024 return ret; 1025 1026 if (mbps != 0 && mbps <= 250) { 1027 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 1028 if (ret) 1029 return ret; 1030 1031 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 1032 0xf1); 1033 if (ret) 1034 return ret; 1035 } 1036 1037 return rcsi2_phtw_write_array(priv, step2); 1038} 1039 1040static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 1041{ 1042 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 1043} 1044 1045static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 1046{ 1047 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 1048} 1049 1050static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 1051{ 1052 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 1053} 1054 1055static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 1056{ 1057 static const struct phtw_value step1[] = { 1058 { .data = 0xee, .code = 0x34 }, 1059 { .data = 0xee, .code = 0x44 }, 1060 { .data = 0xee, .code = 0x54 }, 1061 { .data = 0xee, .code = 0x84 }, 1062 { .data = 0xee, .code = 0x94 }, 1063 { /* sentinel */ }, 1064 }; 1065 1066 return rcsi2_phtw_write_array(priv, step1); 1067} 1068 1069/* ----------------------------------------------------------------------------- 1070 * Platform Device Driver. 1071 */ 1072 1073static const struct media_entity_operations rcar_csi2_entity_ops = { 1074 .link_validate = v4l2_subdev_link_validate, 1075}; 1076 1077static int rcsi2_probe_resources(struct rcar_csi2 *priv, 1078 struct platform_device *pdev) 1079{ 1080 struct resource *res; 1081 int irq, ret; 1082 1083 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1084 priv->base = devm_ioremap_resource(&pdev->dev, res); 1085 if (IS_ERR(priv->base)) 1086 return PTR_ERR(priv->base); 1087 1088 irq = platform_get_irq(pdev, 0); 1089 if (irq < 0) 1090 return irq; 1091 1092 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 1093 rcsi2_irq_thread, IRQF_SHARED, 1094 KBUILD_MODNAME, priv); 1095 if (ret) 1096 return ret; 1097 1098 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 1099 1100 return PTR_ERR_OR_ZERO(priv->rstc); 1101} 1102 1103static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 1104 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1105 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1106 .csi0clkfreqrange = 0x20, 1107 .num_channels = 4, 1108 .clear_ulps = true, 1109}; 1110 1111static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = { 1112 .hsfreqrange = hsfreqrange_m3w_h3es1, 1113 .num_channels = 4, 1114}; 1115 1116static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 1117 .init_phtw = rcsi2_init_phtw_h3es2, 1118 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1119 .csi0clkfreqrange = 0x20, 1120 .num_channels = 4, 1121 .clear_ulps = true, 1122}; 1123 1124static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 1125 .hsfreqrange = hsfreqrange_m3w_h3es1, 1126 .num_channels = 4, 1127}; 1128 1129static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 1130 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1131 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1132 .csi0clkfreqrange = 0x20, 1133 .num_channels = 4, 1134 .clear_ulps = true, 1135}; 1136 1137static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 1138 .init_phtw = rcsi2_init_phtw_v3m_e3, 1139 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 1140 .num_channels = 4, 1141}; 1142 1143static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 1144 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1145 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1146 .csi0clkfreqrange = 0x20, 1147 .clear_ulps = true, 1148}; 1149 1150static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 1151 .init_phtw = rcsi2_init_phtw_v3m_e3, 1152 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 1153 .num_channels = 2, 1154}; 1155 1156static const struct of_device_id rcar_csi2_of_table[] = { 1157 { 1158 .compatible = "renesas,r8a774a1-csi2", 1159 .data = &rcar_csi2_info_r8a7796, 1160 }, 1161 { 1162 .compatible = "renesas,r8a774b1-csi2", 1163 .data = &rcar_csi2_info_r8a77965, 1164 }, 1165 { 1166 .compatible = "renesas,r8a774c0-csi2", 1167 .data = &rcar_csi2_info_r8a77990, 1168 }, 1169 { 1170 .compatible = "renesas,r8a774e1-csi2", 1171 .data = &rcar_csi2_info_r8a7795, 1172 }, 1173 { 1174 .compatible = "renesas,r8a7795-csi2", 1175 .data = &rcar_csi2_info_r8a7795, 1176 }, 1177 { 1178 .compatible = "renesas,r8a7796-csi2", 1179 .data = &rcar_csi2_info_r8a7796, 1180 }, 1181 { 1182 .compatible = "renesas,r8a77965-csi2", 1183 .data = &rcar_csi2_info_r8a77965, 1184 }, 1185 { 1186 .compatible = "renesas,r8a77970-csi2", 1187 .data = &rcar_csi2_info_r8a77970, 1188 }, 1189 { 1190 .compatible = "renesas,r8a77980-csi2", 1191 .data = &rcar_csi2_info_r8a77980, 1192 }, 1193 { 1194 .compatible = "renesas,r8a77990-csi2", 1195 .data = &rcar_csi2_info_r8a77990, 1196 }, 1197 { /* sentinel */ }, 1198}; 1199MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 1200 1201static const struct soc_device_attribute r8a7795[] = { 1202 { 1203 .soc_id = "r8a7795", .revision = "ES1.*", 1204 .data = &rcar_csi2_info_r8a7795es1, 1205 }, 1206 { 1207 .soc_id = "r8a7795", .revision = "ES2.*", 1208 .data = &rcar_csi2_info_r8a7795es2, 1209 }, 1210 { /* sentinel */ }, 1211}; 1212 1213static int rcsi2_probe(struct platform_device *pdev) 1214{ 1215 const struct soc_device_attribute *attr; 1216 struct rcar_csi2 *priv; 1217 unsigned int i; 1218 int ret; 1219 1220 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1221 if (!priv) 1222 return -ENOMEM; 1223 1224 priv->info = of_device_get_match_data(&pdev->dev); 1225 1226 /* 1227 * The different ES versions of r8a7795 (H3) behave differently but 1228 * share the same compatible string. 1229 */ 1230 attr = soc_device_match(r8a7795); 1231 if (attr) 1232 priv->info = attr->data; 1233 1234 priv->dev = &pdev->dev; 1235 1236 mutex_init(&priv->lock); 1237 priv->stream_count = 0; 1238 1239 ret = rcsi2_probe_resources(priv, pdev); 1240 if (ret) { 1241 dev_err(priv->dev, "Failed to get resources\n"); 1242 return ret; 1243 } 1244 1245 platform_set_drvdata(pdev, priv); 1246 1247 ret = rcsi2_parse_dt(priv); 1248 if (ret) 1249 return ret; 1250 1251 priv->subdev.owner = THIS_MODULE; 1252 priv->subdev.dev = &pdev->dev; 1253 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 1254 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 1255 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s", 1256 KBUILD_MODNAME, dev_name(&pdev->dev)); 1257 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 1258 1259 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 1260 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 1261 1262 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 1263 for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++) 1264 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 1265 1266 ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD, 1267 priv->pads); 1268 if (ret) 1269 goto error; 1270 1271 pm_runtime_enable(&pdev->dev); 1272 1273 ret = v4l2_async_register_subdev(&priv->subdev); 1274 if (ret < 0) 1275 goto error; 1276 1277 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 1278 1279 return 0; 1280 1281error: 1282 v4l2_async_notifier_unregister(&priv->notifier); 1283 v4l2_async_notifier_cleanup(&priv->notifier); 1284 1285 return ret; 1286} 1287 1288static int rcsi2_remove(struct platform_device *pdev) 1289{ 1290 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 1291 1292 v4l2_async_notifier_unregister(&priv->notifier); 1293 v4l2_async_notifier_cleanup(&priv->notifier); 1294 v4l2_async_unregister_subdev(&priv->subdev); 1295 1296 pm_runtime_disable(&pdev->dev); 1297 1298 return 0; 1299} 1300 1301static struct platform_driver rcar_csi2_pdrv = { 1302 .remove = rcsi2_remove, 1303 .probe = rcsi2_probe, 1304 .driver = { 1305 .name = "rcar-csi2", 1306 .of_match_table = rcar_csi2_of_table, 1307 }, 1308}; 1309 1310module_platform_driver(rcar_csi2_pdrv); 1311 1312MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 1313MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 1314MODULE_LICENSE("GPL"); 1315