1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * isp.c 4 * 5 * TI OMAP3 ISP - Core 6 * 7 * Copyright (C) 2006-2010 Nokia Corporation 8 * Copyright (C) 2007-2009 Texas Instruments, Inc. 9 * 10 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11 * Sakari Ailus <sakari.ailus@iki.fi> 12 * 13 * Contributors: 14 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 15 * Sakari Ailus <sakari.ailus@iki.fi> 16 * David Cohen <dacohen@gmail.com> 17 * Stanimir Varbanov <svarbanov@mm-sol.com> 18 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com> 19 * Tuukka Toivonen <tuukkat76@gmail.com> 20 * Sergio Aguirre <saaguirre@ti.com> 21 * Antti Koskipaa <akoskipa@gmail.com> 22 * Ivan T. Ivanov <iivanov@mm-sol.com> 23 * RaniSuneela <r-m@ti.com> 24 * Atanas Filipov <afilipov@mm-sol.com> 25 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com> 26 * Hiroshi DOYU <hiroshi.doyu@nokia.com> 27 * Nayden Kanchev <nkanchev@mm-sol.com> 28 * Phil Carmody <ext-phil.2.carmody@nokia.com> 29 * Artem Bityutskiy <artem.bityutskiy@nokia.com> 30 * Dominic Curran <dcurran@ti.com> 31 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi> 32 * Pallavi Kulkarni <p-kulkarni@ti.com> 33 * Vaibhav Hiremath <hvaibhav@ti.com> 34 * Mohit Jalori <mjalori@ti.com> 35 * Sameer Venkatraman <sameerv@ti.com> 36 * Senthilvadivu Guruswamy <svadivu@ti.com> 37 * Thara Gopinath <thara@ti.com> 38 * Toni Leinonen <toni.leinonen@nokia.com> 39 * Troy Laramy <t-laramy@ti.com> 40 */ 41 42#include <linux/clk.h> 43#include <linux/clkdev.h> 44#include <linux/delay.h> 45#include <linux/device.h> 46#include <linux/dma-mapping.h> 47#include <linux/i2c.h> 48#include <linux/interrupt.h> 49#include <linux/mfd/syscon.h> 50#include <linux/module.h> 51#include <linux/omap-iommu.h> 52#include <linux/platform_device.h> 53#include <linux/property.h> 54#include <linux/regulator/consumer.h> 55#include <linux/slab.h> 56#include <linux/sched.h> 57#include <linux/vmalloc.h> 58 59#ifdef CONFIG_ARM_DMA_USE_IOMMU 60#include <asm/dma-iommu.h> 61#endif 62 63#include <media/v4l2-common.h> 64#include <media/v4l2-fwnode.h> 65#include <media/v4l2-device.h> 66#include <media/v4l2-mc.h> 67 68#include "isp.h" 69#include "ispreg.h" 70#include "ispccdc.h" 71#include "isppreview.h" 72#include "ispresizer.h" 73#include "ispcsi2.h" 74#include "ispccp2.h" 75#include "isph3a.h" 76#include "isphist.h" 77 78static unsigned int autoidle; 79module_param(autoidle, int, 0444); 80MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support"); 81 82static void isp_save_ctx(struct isp_device *isp); 83 84static void isp_restore_ctx(struct isp_device *isp); 85 86static const struct isp_res_mapping isp_res_maps[] = { 87 { 88 .isp_rev = ISP_REVISION_2_0, 89 .offset = { 90 /* first MMIO area */ 91 0x0000, /* base, len 0x0070 */ 92 0x0400, /* ccp2, len 0x01f0 */ 93 0x0600, /* ccdc, len 0x00a8 */ 94 0x0a00, /* hist, len 0x0048 */ 95 0x0c00, /* h3a, len 0x0060 */ 96 0x0e00, /* preview, len 0x00a0 */ 97 0x1000, /* resizer, len 0x00ac */ 98 0x1200, /* sbl, len 0x00fc */ 99 /* second MMIO area */ 100 0x0000, /* csi2a, len 0x0170 */ 101 0x0170, /* csiphy2, len 0x000c */ 102 }, 103 .phy_type = ISP_PHY_TYPE_3430, 104 }, 105 { 106 .isp_rev = ISP_REVISION_15_0, 107 .offset = { 108 /* first MMIO area */ 109 0x0000, /* base, len 0x0070 */ 110 0x0400, /* ccp2, len 0x01f0 */ 111 0x0600, /* ccdc, len 0x00a8 */ 112 0x0a00, /* hist, len 0x0048 */ 113 0x0c00, /* h3a, len 0x0060 */ 114 0x0e00, /* preview, len 0x00a0 */ 115 0x1000, /* resizer, len 0x00ac */ 116 0x1200, /* sbl, len 0x00fc */ 117 /* second MMIO area */ 118 0x0000, /* csi2a, len 0x0170 (1st area) */ 119 0x0170, /* csiphy2, len 0x000c */ 120 0x01c0, /* csi2a, len 0x0040 (2nd area) */ 121 0x0400, /* csi2c, len 0x0170 (1st area) */ 122 0x0570, /* csiphy1, len 0x000c */ 123 0x05c0, /* csi2c, len 0x0040 (2nd area) */ 124 }, 125 .phy_type = ISP_PHY_TYPE_3630, 126 }, 127}; 128 129/* Structure for saving/restoring ISP module registers */ 130static struct isp_reg isp_reg_list[] = { 131 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0}, 132 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0}, 133 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0}, 134 {0, ISP_TOK_TERM, 0} 135}; 136 137/* 138 * omap3isp_flush - Post pending L3 bus writes by doing a register readback 139 * @isp: OMAP3 ISP device 140 * 141 * In order to force posting of pending writes, we need to write and 142 * readback the same register, in this case the revision register. 143 * 144 * See this link for reference: 145 * https://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html 146 */ 147void omap3isp_flush(struct isp_device *isp) 148{ 149 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION); 150 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION); 151} 152 153/* ----------------------------------------------------------------------------- 154 * XCLK 155 */ 156 157#define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw) 158 159static void isp_xclk_update(struct isp_xclk *xclk, u32 divider) 160{ 161 switch (xclk->id) { 162 case ISP_XCLK_A: 163 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 164 ISPTCTRL_CTRL_DIVA_MASK, 165 divider << ISPTCTRL_CTRL_DIVA_SHIFT); 166 break; 167 case ISP_XCLK_B: 168 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 169 ISPTCTRL_CTRL_DIVB_MASK, 170 divider << ISPTCTRL_CTRL_DIVB_SHIFT); 171 break; 172 } 173} 174 175static int isp_xclk_prepare(struct clk_hw *hw) 176{ 177 struct isp_xclk *xclk = to_isp_xclk(hw); 178 179 omap3isp_get(xclk->isp); 180 181 return 0; 182} 183 184static void isp_xclk_unprepare(struct clk_hw *hw) 185{ 186 struct isp_xclk *xclk = to_isp_xclk(hw); 187 188 omap3isp_put(xclk->isp); 189} 190 191static int isp_xclk_enable(struct clk_hw *hw) 192{ 193 struct isp_xclk *xclk = to_isp_xclk(hw); 194 unsigned long flags; 195 196 spin_lock_irqsave(&xclk->lock, flags); 197 isp_xclk_update(xclk, xclk->divider); 198 xclk->enabled = true; 199 spin_unlock_irqrestore(&xclk->lock, flags); 200 201 return 0; 202} 203 204static void isp_xclk_disable(struct clk_hw *hw) 205{ 206 struct isp_xclk *xclk = to_isp_xclk(hw); 207 unsigned long flags; 208 209 spin_lock_irqsave(&xclk->lock, flags); 210 isp_xclk_update(xclk, 0); 211 xclk->enabled = false; 212 spin_unlock_irqrestore(&xclk->lock, flags); 213} 214 215static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw, 216 unsigned long parent_rate) 217{ 218 struct isp_xclk *xclk = to_isp_xclk(hw); 219 220 return parent_rate / xclk->divider; 221} 222 223static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate) 224{ 225 u32 divider; 226 227 if (*rate >= parent_rate) { 228 *rate = parent_rate; 229 return ISPTCTRL_CTRL_DIV_BYPASS; 230 } 231 232 if (*rate == 0) 233 *rate = 1; 234 235 divider = DIV_ROUND_CLOSEST(parent_rate, *rate); 236 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS) 237 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1; 238 239 *rate = parent_rate / divider; 240 return divider; 241} 242 243static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate, 244 unsigned long *parent_rate) 245{ 246 isp_xclk_calc_divider(&rate, *parent_rate); 247 return rate; 248} 249 250static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate, 251 unsigned long parent_rate) 252{ 253 struct isp_xclk *xclk = to_isp_xclk(hw); 254 unsigned long flags; 255 u32 divider; 256 257 divider = isp_xclk_calc_divider(&rate, parent_rate); 258 259 spin_lock_irqsave(&xclk->lock, flags); 260 261 xclk->divider = divider; 262 if (xclk->enabled) 263 isp_xclk_update(xclk, divider); 264 265 spin_unlock_irqrestore(&xclk->lock, flags); 266 267 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n", 268 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider); 269 return 0; 270} 271 272static const struct clk_ops isp_xclk_ops = { 273 .prepare = isp_xclk_prepare, 274 .unprepare = isp_xclk_unprepare, 275 .enable = isp_xclk_enable, 276 .disable = isp_xclk_disable, 277 .recalc_rate = isp_xclk_recalc_rate, 278 .round_rate = isp_xclk_round_rate, 279 .set_rate = isp_xclk_set_rate, 280}; 281 282static const char *isp_xclk_parent_name = "cam_mclk"; 283 284static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data) 285{ 286 unsigned int idx = clkspec->args[0]; 287 struct isp_device *isp = data; 288 289 if (idx >= ARRAY_SIZE(isp->xclks)) 290 return ERR_PTR(-ENOENT); 291 292 return isp->xclks[idx].clk; 293} 294 295static int isp_xclk_init(struct isp_device *isp) 296{ 297 struct device_node *np = isp->dev->of_node; 298 struct clk_init_data init = {}; 299 unsigned int i; 300 301 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) 302 isp->xclks[i].clk = ERR_PTR(-EINVAL); 303 304 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) { 305 struct isp_xclk *xclk = &isp->xclks[i]; 306 307 xclk->isp = isp; 308 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B; 309 xclk->divider = 1; 310 spin_lock_init(&xclk->lock); 311 312 init.name = i == 0 ? "cam_xclka" : "cam_xclkb"; 313 init.ops = &isp_xclk_ops; 314 init.parent_names = &isp_xclk_parent_name; 315 init.num_parents = 1; 316 317 xclk->hw.init = &init; 318 /* 319 * The first argument is NULL in order to avoid circular 320 * reference, as this driver takes reference on the 321 * sensor subdevice modules and the sensors would take 322 * reference on this module through clk_get(). 323 */ 324 xclk->clk = clk_register(NULL, &xclk->hw); 325 if (IS_ERR(xclk->clk)) 326 return PTR_ERR(xclk->clk); 327 } 328 329 if (np) 330 of_clk_add_provider(np, isp_xclk_src_get, isp); 331 332 return 0; 333} 334 335static void isp_xclk_cleanup(struct isp_device *isp) 336{ 337 struct device_node *np = isp->dev->of_node; 338 unsigned int i; 339 340 if (np) 341 of_clk_del_provider(np); 342 343 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) { 344 struct isp_xclk *xclk = &isp->xclks[i]; 345 346 if (!IS_ERR(xclk->clk)) 347 clk_unregister(xclk->clk); 348 } 349} 350 351/* ----------------------------------------------------------------------------- 352 * Interrupts 353 */ 354 355/* 356 * isp_enable_interrupts - Enable ISP interrupts. 357 * @isp: OMAP3 ISP device 358 */ 359static void isp_enable_interrupts(struct isp_device *isp) 360{ 361 static const u32 irq = IRQ0ENABLE_CSIA_IRQ 362 | IRQ0ENABLE_CSIB_IRQ 363 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ 364 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ 365 | IRQ0ENABLE_CCDC_VD0_IRQ 366 | IRQ0ENABLE_CCDC_VD1_IRQ 367 | IRQ0ENABLE_HS_VS_IRQ 368 | IRQ0ENABLE_HIST_DONE_IRQ 369 | IRQ0ENABLE_H3A_AWB_DONE_IRQ 370 | IRQ0ENABLE_H3A_AF_DONE_IRQ 371 | IRQ0ENABLE_PRV_DONE_IRQ 372 | IRQ0ENABLE_RSZ_DONE_IRQ; 373 374 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS); 375 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE); 376} 377 378/* 379 * isp_disable_interrupts - Disable ISP interrupts. 380 * @isp: OMAP3 ISP device 381 */ 382static void isp_disable_interrupts(struct isp_device *isp) 383{ 384 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE); 385} 386 387/* 388 * isp_core_init - ISP core settings 389 * @isp: OMAP3 ISP device 390 * @idle: Consider idle state. 391 * 392 * Set the power settings for the ISP and SBL bus and configure the HS/VS 393 * interrupt source. 394 * 395 * We need to configure the HS/VS interrupt source before interrupts get 396 * enabled, as the sensor might be free-running and the ISP default setting 397 * (HS edge) would put an unnecessary burden on the CPU. 398 */ 399static void isp_core_init(struct isp_device *isp, int idle) 400{ 401 isp_reg_writel(isp, 402 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY : 403 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) << 404 ISP_SYSCONFIG_MIDLEMODE_SHIFT) | 405 ((isp->revision == ISP_REVISION_15_0) ? 406 ISP_SYSCONFIG_AUTOIDLE : 0), 407 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG); 408 409 isp_reg_writel(isp, 410 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) | 411 ISPCTRL_SYNC_DETECT_VSRISE, 412 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL); 413} 414 415/* 416 * Configure the bridge and lane shifter. Valid inputs are 417 * 418 * CCDC_INPUT_PARALLEL: Parallel interface 419 * CCDC_INPUT_CSI2A: CSI2a receiver 420 * CCDC_INPUT_CCP2B: CCP2b receiver 421 * CCDC_INPUT_CSI2C: CSI2c receiver 422 * 423 * The bridge and lane shifter are configured according to the selected input 424 * and the ISP platform data. 425 */ 426void omap3isp_configure_bridge(struct isp_device *isp, 427 enum ccdc_input_entity input, 428 const struct isp_parallel_cfg *parcfg, 429 unsigned int shift, unsigned int bridge) 430{ 431 u32 ispctrl_val; 432 433 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL); 434 ispctrl_val &= ~ISPCTRL_SHIFT_MASK; 435 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV; 436 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK; 437 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK; 438 ispctrl_val |= bridge; 439 440 switch (input) { 441 case CCDC_INPUT_PARALLEL: 442 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL; 443 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT; 444 shift += parcfg->data_lane_shift; 445 break; 446 447 case CCDC_INPUT_CSI2A: 448 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA; 449 break; 450 451 case CCDC_INPUT_CCP2B: 452 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB; 453 break; 454 455 case CCDC_INPUT_CSI2C: 456 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC; 457 break; 458 459 default: 460 return; 461 } 462 463 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK; 464 465 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL); 466} 467 468void omap3isp_hist_dma_done(struct isp_device *isp) 469{ 470 if (omap3isp_ccdc_busy(&isp->isp_ccdc) || 471 omap3isp_stat_pcr_busy(&isp->isp_hist)) { 472 /* Histogram cannot be enabled in this frame anymore */ 473 atomic_set(&isp->isp_hist.buf_err, 1); 474 dev_dbg(isp->dev, 475 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n"); 476 } 477} 478 479static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus) 480{ 481 static const char *name[] = { 482 "CSIA_IRQ", 483 "res1", 484 "res2", 485 "CSIB_LCM_IRQ", 486 "CSIB_IRQ", 487 "res5", 488 "res6", 489 "res7", 490 "CCDC_VD0_IRQ", 491 "CCDC_VD1_IRQ", 492 "CCDC_VD2_IRQ", 493 "CCDC_ERR_IRQ", 494 "H3A_AF_DONE_IRQ", 495 "H3A_AWB_DONE_IRQ", 496 "res14", 497 "res15", 498 "HIST_DONE_IRQ", 499 "CCDC_LSC_DONE", 500 "CCDC_LSC_PREFETCH_COMPLETED", 501 "CCDC_LSC_PREFETCH_ERROR", 502 "PRV_DONE_IRQ", 503 "CBUFF_IRQ", 504 "res22", 505 "res23", 506 "RSZ_DONE_IRQ", 507 "OVF_IRQ", 508 "res26", 509 "res27", 510 "MMU_ERR_IRQ", 511 "OCP_ERR_IRQ", 512 "SEC_ERR_IRQ", 513 "HS_VS_IRQ", 514 }; 515 int i; 516 517 dev_dbg(isp->dev, "ISP IRQ: "); 518 519 for (i = 0; i < ARRAY_SIZE(name); i++) { 520 if ((1 << i) & irqstatus) 521 printk(KERN_CONT "%s ", name[i]); 522 } 523 printk(KERN_CONT "\n"); 524} 525 526static void isp_isr_sbl(struct isp_device *isp) 527{ 528 struct device *dev = isp->dev; 529 struct isp_pipeline *pipe; 530 u32 sbl_pcr; 531 532 /* 533 * Handle shared buffer logic overflows for video buffers. 534 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored. 535 */ 536 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR); 537 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR); 538 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF; 539 540 if (sbl_pcr) 541 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr); 542 543 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) { 544 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity); 545 if (pipe != NULL) 546 pipe->error = true; 547 } 548 549 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) { 550 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity); 551 if (pipe != NULL) 552 pipe->error = true; 553 } 554 555 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) { 556 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity); 557 if (pipe != NULL) 558 pipe->error = true; 559 } 560 561 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) { 562 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity); 563 if (pipe != NULL) 564 pipe->error = true; 565 } 566 567 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF 568 | ISPSBL_PCR_RSZ2_WBL_OVF 569 | ISPSBL_PCR_RSZ3_WBL_OVF 570 | ISPSBL_PCR_RSZ4_WBL_OVF)) { 571 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity); 572 if (pipe != NULL) 573 pipe->error = true; 574 } 575 576 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF) 577 omap3isp_stat_sbl_overflow(&isp->isp_af); 578 579 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF) 580 omap3isp_stat_sbl_overflow(&isp->isp_aewb); 581} 582 583/* 584 * isp_isr - Interrupt Service Routine for Camera ISP module. 585 * @irq: Not used currently. 586 * @_isp: Pointer to the OMAP3 ISP device 587 * 588 * Handles the corresponding callback if plugged in. 589 */ 590static irqreturn_t isp_isr(int irq, void *_isp) 591{ 592 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ | 593 IRQ0STATUS_CCDC_LSC_DONE_IRQ | 594 IRQ0STATUS_CCDC_VD0_IRQ | 595 IRQ0STATUS_CCDC_VD1_IRQ | 596 IRQ0STATUS_HS_VS_IRQ; 597 struct isp_device *isp = _isp; 598 u32 irqstatus; 599 600 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS); 601 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS); 602 603 isp_isr_sbl(isp); 604 605 if (irqstatus & IRQ0STATUS_CSIA_IRQ) 606 omap3isp_csi2_isr(&isp->isp_csi2a); 607 608 if (irqstatus & IRQ0STATUS_CSIB_IRQ) 609 omap3isp_ccp2_isr(&isp->isp_ccp2); 610 611 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) { 612 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW) 613 omap3isp_preview_isr_frame_sync(&isp->isp_prev); 614 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER) 615 omap3isp_resizer_isr_frame_sync(&isp->isp_res); 616 omap3isp_stat_isr_frame_sync(&isp->isp_aewb); 617 omap3isp_stat_isr_frame_sync(&isp->isp_af); 618 omap3isp_stat_isr_frame_sync(&isp->isp_hist); 619 } 620 621 if (irqstatus & ccdc_events) 622 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events); 623 624 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) { 625 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER) 626 omap3isp_resizer_isr_frame_sync(&isp->isp_res); 627 omap3isp_preview_isr(&isp->isp_prev); 628 } 629 630 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ) 631 omap3isp_resizer_isr(&isp->isp_res); 632 633 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ) 634 omap3isp_stat_isr(&isp->isp_aewb); 635 636 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ) 637 omap3isp_stat_isr(&isp->isp_af); 638 639 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ) 640 omap3isp_stat_isr(&isp->isp_hist); 641 642 omap3isp_flush(isp); 643 644#if defined(DEBUG) && defined(ISP_ISR_DEBUG) 645 isp_isr_dbg(isp, irqstatus); 646#endif 647 648 return IRQ_HANDLED; 649} 650 651static const struct media_device_ops isp_media_ops = { 652 .link_notify = v4l2_pipeline_link_notify, 653}; 654 655/* ----------------------------------------------------------------------------- 656 * Pipeline stream management 657 */ 658 659/* 660 * isp_pipeline_enable - Enable streaming on a pipeline 661 * @pipe: ISP pipeline 662 * @mode: Stream mode (single shot or continuous) 663 * 664 * Walk the entities chain starting at the pipeline output video node and start 665 * all modules in the chain in the given mode. 666 * 667 * Return 0 if successful, or the return value of the failed video::s_stream 668 * operation otherwise. 669 */ 670static int isp_pipeline_enable(struct isp_pipeline *pipe, 671 enum isp_pipeline_stream_state mode) 672{ 673 struct isp_device *isp = pipe->output->isp; 674 struct media_entity *entity; 675 struct media_pad *pad; 676 struct v4l2_subdev *subdev; 677 unsigned long flags; 678 int ret; 679 680 /* Refuse to start streaming if an entity included in the pipeline has 681 * crashed. This check must be performed before the loop below to avoid 682 * starting entities if the pipeline won't start anyway (those entities 683 * would then likely fail to stop, making the problem worse). 684 */ 685 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed)) 686 return -EIO; 687 688 spin_lock_irqsave(&pipe->lock, flags); 689 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT); 690 spin_unlock_irqrestore(&pipe->lock, flags); 691 692 pipe->do_propagation = false; 693 694 entity = &pipe->output->video.entity; 695 while (1) { 696 pad = &entity->pads[0]; 697 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 698 break; 699 700 pad = media_entity_remote_pad(pad); 701 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 702 break; 703 704 entity = pad->entity; 705 subdev = media_entity_to_v4l2_subdev(entity); 706 707 ret = v4l2_subdev_call(subdev, video, s_stream, mode); 708 if (ret < 0 && ret != -ENOIOCTLCMD) 709 return ret; 710 711 if (subdev == &isp->isp_ccdc.subdev) { 712 v4l2_subdev_call(&isp->isp_aewb.subdev, video, 713 s_stream, mode); 714 v4l2_subdev_call(&isp->isp_af.subdev, video, 715 s_stream, mode); 716 v4l2_subdev_call(&isp->isp_hist.subdev, video, 717 s_stream, mode); 718 pipe->do_propagation = true; 719 } 720 721 /* Stop at the first external sub-device. */ 722 if (subdev->dev != isp->dev) 723 break; 724 } 725 726 return 0; 727} 728 729static int isp_pipeline_wait_resizer(struct isp_device *isp) 730{ 731 return omap3isp_resizer_busy(&isp->isp_res); 732} 733 734static int isp_pipeline_wait_preview(struct isp_device *isp) 735{ 736 return omap3isp_preview_busy(&isp->isp_prev); 737} 738 739static int isp_pipeline_wait_ccdc(struct isp_device *isp) 740{ 741 return omap3isp_stat_busy(&isp->isp_af) 742 || omap3isp_stat_busy(&isp->isp_aewb) 743 || omap3isp_stat_busy(&isp->isp_hist) 744 || omap3isp_ccdc_busy(&isp->isp_ccdc); 745} 746 747#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000) 748 749static int isp_pipeline_wait(struct isp_device *isp, 750 int(*busy)(struct isp_device *isp)) 751{ 752 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT; 753 754 while (!time_after(jiffies, timeout)) { 755 if (!busy(isp)) 756 return 0; 757 } 758 759 return 1; 760} 761 762/* 763 * isp_pipeline_disable - Disable streaming on a pipeline 764 * @pipe: ISP pipeline 765 * 766 * Walk the entities chain starting at the pipeline output video node and stop 767 * all modules in the chain. Wait synchronously for the modules to be stopped if 768 * necessary. 769 * 770 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module 771 * can't be stopped (in which case a software reset of the ISP is probably 772 * necessary). 773 */ 774static int isp_pipeline_disable(struct isp_pipeline *pipe) 775{ 776 struct isp_device *isp = pipe->output->isp; 777 struct media_entity *entity; 778 struct media_pad *pad; 779 struct v4l2_subdev *subdev; 780 int failure = 0; 781 int ret; 782 783 /* 784 * We need to stop all the modules after CCDC first or they'll 785 * never stop since they may not get a full frame from CCDC. 786 */ 787 entity = &pipe->output->video.entity; 788 while (1) { 789 pad = &entity->pads[0]; 790 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 791 break; 792 793 pad = media_entity_remote_pad(pad); 794 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 795 break; 796 797 entity = pad->entity; 798 subdev = media_entity_to_v4l2_subdev(entity); 799 800 if (subdev == &isp->isp_ccdc.subdev) { 801 v4l2_subdev_call(&isp->isp_aewb.subdev, 802 video, s_stream, 0); 803 v4l2_subdev_call(&isp->isp_af.subdev, 804 video, s_stream, 0); 805 v4l2_subdev_call(&isp->isp_hist.subdev, 806 video, s_stream, 0); 807 } 808 809 ret = v4l2_subdev_call(subdev, video, s_stream, 0); 810 811 /* Stop at the first external sub-device. */ 812 if (subdev->dev != isp->dev) 813 break; 814 815 if (subdev == &isp->isp_res.subdev) 816 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer); 817 else if (subdev == &isp->isp_prev.subdev) 818 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview); 819 else if (subdev == &isp->isp_ccdc.subdev) 820 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc); 821 822 /* Handle stop failures. An entity that fails to stop can 823 * usually just be restarted. Flag the stop failure nonetheless 824 * to trigger an ISP reset the next time the device is released, 825 * just in case. 826 * 827 * The preview engine is a special case. A failure to stop can 828 * mean a hardware crash. When that happens the preview engine 829 * won't respond to read/write operations on the L4 bus anymore, 830 * resulting in a bus fault and a kernel oops next time it gets 831 * accessed. Mark it as crashed to prevent pipelines including 832 * it from being started. 833 */ 834 if (ret) { 835 dev_info(isp->dev, "Unable to stop %s\n", subdev->name); 836 isp->stop_failure = true; 837 if (subdev == &isp->isp_prev.subdev) 838 media_entity_enum_set(&isp->crashed, 839 &subdev->entity); 840 failure = -ETIMEDOUT; 841 } 842 } 843 844 return failure; 845} 846 847/* 848 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline 849 * @pipe: ISP pipeline 850 * @state: Stream state (stopped, single shot or continuous) 851 * 852 * Set the pipeline to the given stream state. Pipelines can be started in 853 * single-shot or continuous mode. 854 * 855 * Return 0 if successful, or the return value of the failed video::s_stream 856 * operation otherwise. The pipeline state is not updated when the operation 857 * fails, except when stopping the pipeline. 858 */ 859int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe, 860 enum isp_pipeline_stream_state state) 861{ 862 int ret; 863 864 if (state == ISP_PIPELINE_STREAM_STOPPED) 865 ret = isp_pipeline_disable(pipe); 866 else 867 ret = isp_pipeline_enable(pipe, state); 868 869 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED) 870 pipe->stream_state = state; 871 872 return ret; 873} 874 875/* 876 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline 877 * @pipe: ISP pipeline 878 * 879 * Cancelling a stream mark all buffers on all video nodes in the pipeline as 880 * erroneous and makes sure no new buffer can be queued. This function is called 881 * when a fatal error that prevents any further operation on the pipeline 882 * occurs. 883 */ 884void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe) 885{ 886 if (pipe->input) 887 omap3isp_video_cancel_stream(pipe->input); 888 if (pipe->output) 889 omap3isp_video_cancel_stream(pipe->output); 890} 891 892/* 893 * isp_pipeline_resume - Resume streaming on a pipeline 894 * @pipe: ISP pipeline 895 * 896 * Resume video output and input and re-enable pipeline. 897 */ 898static void isp_pipeline_resume(struct isp_pipeline *pipe) 899{ 900 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT; 901 902 omap3isp_video_resume(pipe->output, !singleshot); 903 if (singleshot) 904 omap3isp_video_resume(pipe->input, 0); 905 isp_pipeline_enable(pipe, pipe->stream_state); 906} 907 908/* 909 * isp_pipeline_suspend - Suspend streaming on a pipeline 910 * @pipe: ISP pipeline 911 * 912 * Suspend pipeline. 913 */ 914static void isp_pipeline_suspend(struct isp_pipeline *pipe) 915{ 916 isp_pipeline_disable(pipe); 917} 918 919/* 920 * isp_pipeline_is_last - Verify if entity has an enabled link to the output 921 * video node 922 * @me: ISP module's media entity 923 * 924 * Returns 1 if the entity has an enabled link to the output video node or 0 925 * otherwise. It's true only while pipeline can have no more than one output 926 * node. 927 */ 928static int isp_pipeline_is_last(struct media_entity *me) 929{ 930 struct isp_pipeline *pipe; 931 struct media_pad *pad; 932 933 if (!me->pipe) 934 return 0; 935 pipe = to_isp_pipeline(me); 936 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED) 937 return 0; 938 pad = media_entity_remote_pad(&pipe->output->pad); 939 return pad->entity == me; 940} 941 942/* 943 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module 944 * @me: ISP module's media entity 945 * 946 * Suspend the whole pipeline if module's entity has an enabled link to the 947 * output video node. It works only while pipeline can have no more than one 948 * output node. 949 */ 950static void isp_suspend_module_pipeline(struct media_entity *me) 951{ 952 if (isp_pipeline_is_last(me)) 953 isp_pipeline_suspend(to_isp_pipeline(me)); 954} 955 956/* 957 * isp_resume_module_pipeline - Resume pipeline to which belongs the module 958 * @me: ISP module's media entity 959 * 960 * Resume the whole pipeline if module's entity has an enabled link to the 961 * output video node. It works only while pipeline can have no more than one 962 * output node. 963 */ 964static void isp_resume_module_pipeline(struct media_entity *me) 965{ 966 if (isp_pipeline_is_last(me)) 967 isp_pipeline_resume(to_isp_pipeline(me)); 968} 969 970/* 971 * isp_suspend_modules - Suspend ISP submodules. 972 * @isp: OMAP3 ISP device 973 * 974 * Returns 0 if suspend left in idle state all the submodules properly, 975 * or returns 1 if a general Reset is required to suspend the submodules. 976 */ 977static int __maybe_unused isp_suspend_modules(struct isp_device *isp) 978{ 979 unsigned long timeout; 980 981 omap3isp_stat_suspend(&isp->isp_aewb); 982 omap3isp_stat_suspend(&isp->isp_af); 983 omap3isp_stat_suspend(&isp->isp_hist); 984 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity); 985 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity); 986 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity); 987 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity); 988 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity); 989 990 timeout = jiffies + ISP_STOP_TIMEOUT; 991 while (omap3isp_stat_busy(&isp->isp_af) 992 || omap3isp_stat_busy(&isp->isp_aewb) 993 || omap3isp_stat_busy(&isp->isp_hist) 994 || omap3isp_preview_busy(&isp->isp_prev) 995 || omap3isp_resizer_busy(&isp->isp_res) 996 || omap3isp_ccdc_busy(&isp->isp_ccdc)) { 997 if (time_after(jiffies, timeout)) { 998 dev_info(isp->dev, "can't stop modules.\n"); 999 return 1; 1000 } 1001 msleep(1); 1002 } 1003 1004 return 0; 1005} 1006 1007/* 1008 * isp_resume_modules - Resume ISP submodules. 1009 * @isp: OMAP3 ISP device 1010 */ 1011static void __maybe_unused isp_resume_modules(struct isp_device *isp) 1012{ 1013 omap3isp_stat_resume(&isp->isp_aewb); 1014 omap3isp_stat_resume(&isp->isp_af); 1015 omap3isp_stat_resume(&isp->isp_hist); 1016 isp_resume_module_pipeline(&isp->isp_res.subdev.entity); 1017 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity); 1018 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity); 1019 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity); 1020 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity); 1021} 1022 1023/* 1024 * isp_reset - Reset ISP with a timeout wait for idle. 1025 * @isp: OMAP3 ISP device 1026 */ 1027static int isp_reset(struct isp_device *isp) 1028{ 1029 unsigned long timeout = 0; 1030 1031 isp_reg_writel(isp, 1032 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG) 1033 | ISP_SYSCONFIG_SOFTRESET, 1034 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG); 1035 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, 1036 ISP_SYSSTATUS) & 0x1)) { 1037 if (timeout++ > 10000) { 1038 dev_alert(isp->dev, "cannot reset ISP\n"); 1039 return -ETIMEDOUT; 1040 } 1041 udelay(1); 1042 } 1043 1044 isp->stop_failure = false; 1045 media_entity_enum_zero(&isp->crashed); 1046 return 0; 1047} 1048 1049/* 1050 * isp_save_context - Saves the values of the ISP module registers. 1051 * @isp: OMAP3 ISP device 1052 * @reg_list: Structure containing pairs of register address and value to 1053 * modify on OMAP. 1054 */ 1055static void 1056isp_save_context(struct isp_device *isp, struct isp_reg *reg_list) 1057{ 1058 struct isp_reg *next = reg_list; 1059 1060 for (; next->reg != ISP_TOK_TERM; next++) 1061 next->val = isp_reg_readl(isp, next->mmio_range, next->reg); 1062} 1063 1064/* 1065 * isp_restore_context - Restores the values of the ISP module registers. 1066 * @isp: OMAP3 ISP device 1067 * @reg_list: Structure containing pairs of register address and value to 1068 * modify on OMAP. 1069 */ 1070static void 1071isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list) 1072{ 1073 struct isp_reg *next = reg_list; 1074 1075 for (; next->reg != ISP_TOK_TERM; next++) 1076 isp_reg_writel(isp, next->val, next->mmio_range, next->reg); 1077} 1078 1079/* 1080 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context. 1081 * @isp: OMAP3 ISP device 1082 * 1083 * Routine for saving the context of each module in the ISP. 1084 * CCDC, HIST, H3A, PREV, RESZ and MMU. 1085 */ 1086static void isp_save_ctx(struct isp_device *isp) 1087{ 1088 isp_save_context(isp, isp_reg_list); 1089 omap_iommu_save_ctx(isp->dev); 1090} 1091 1092/* 1093 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context. 1094 * @isp: OMAP3 ISP device 1095 * 1096 * Routine for restoring the context of each module in the ISP. 1097 * CCDC, HIST, H3A, PREV, RESZ and MMU. 1098 */ 1099static void isp_restore_ctx(struct isp_device *isp) 1100{ 1101 isp_restore_context(isp, isp_reg_list); 1102 omap_iommu_restore_ctx(isp->dev); 1103 omap3isp_ccdc_restore_context(isp); 1104 omap3isp_preview_restore_context(isp); 1105} 1106 1107/* ----------------------------------------------------------------------------- 1108 * SBL resources management 1109 */ 1110#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \ 1111 OMAP3_ISP_SBL_CCDC_LSC_READ | \ 1112 OMAP3_ISP_SBL_PREVIEW_READ | \ 1113 OMAP3_ISP_SBL_RESIZER_READ) 1114#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \ 1115 OMAP3_ISP_SBL_CSI2A_WRITE | \ 1116 OMAP3_ISP_SBL_CSI2C_WRITE | \ 1117 OMAP3_ISP_SBL_CCDC_WRITE | \ 1118 OMAP3_ISP_SBL_PREVIEW_WRITE) 1119 1120void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res) 1121{ 1122 u32 sbl = 0; 1123 1124 isp->sbl_resources |= res; 1125 1126 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ) 1127 sbl |= ISPCTRL_SBL_SHARED_RPORTA; 1128 1129 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ) 1130 sbl |= ISPCTRL_SBL_SHARED_RPORTB; 1131 1132 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE) 1133 sbl |= ISPCTRL_SBL_SHARED_WPORTC; 1134 1135 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE) 1136 sbl |= ISPCTRL_SBL_WR0_RAM_EN; 1137 1138 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE) 1139 sbl |= ISPCTRL_SBL_WR1_RAM_EN; 1140 1141 if (isp->sbl_resources & OMAP3_ISP_SBL_READ) 1142 sbl |= ISPCTRL_SBL_RD_RAM_EN; 1143 1144 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl); 1145} 1146 1147void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res) 1148{ 1149 u32 sbl = 0; 1150 1151 isp->sbl_resources &= ~res; 1152 1153 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)) 1154 sbl |= ISPCTRL_SBL_SHARED_RPORTA; 1155 1156 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)) 1157 sbl |= ISPCTRL_SBL_SHARED_RPORTB; 1158 1159 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)) 1160 sbl |= ISPCTRL_SBL_SHARED_WPORTC; 1161 1162 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)) 1163 sbl |= ISPCTRL_SBL_WR0_RAM_EN; 1164 1165 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE)) 1166 sbl |= ISPCTRL_SBL_WR1_RAM_EN; 1167 1168 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ)) 1169 sbl |= ISPCTRL_SBL_RD_RAM_EN; 1170 1171 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl); 1172} 1173 1174/* 1175 * isp_module_sync_idle - Helper to sync module with its idle state 1176 * @me: ISP submodule's media entity 1177 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization 1178 * @stopping: flag which tells module wants to stop 1179 * 1180 * This function checks if ISP submodule needs to wait for next interrupt. If 1181 * yes, makes the caller to sleep while waiting for such event. 1182 */ 1183int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, 1184 atomic_t *stopping) 1185{ 1186 struct isp_pipeline *pipe = to_isp_pipeline(me); 1187 1188 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED || 1189 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT && 1190 !isp_pipeline_ready(pipe))) 1191 return 0; 1192 1193 /* 1194 * atomic_set() doesn't include memory barrier on ARM platform for SMP 1195 * scenario. We'll call it here to avoid race conditions. 1196 */ 1197 atomic_set(stopping, 1); 1198 smp_mb(); 1199 1200 /* 1201 * If module is the last one, it's writing to memory. In this case, 1202 * it's necessary to check if the module is already paused due to 1203 * DMA queue underrun or if it has to wait for next interrupt to be 1204 * idle. 1205 * If it isn't the last one, the function won't sleep but *stopping 1206 * will still be set to warn next submodule caller's interrupt the 1207 * module wants to be idle. 1208 */ 1209 if (isp_pipeline_is_last(me)) { 1210 struct isp_video *video = pipe->output; 1211 unsigned long flags; 1212 spin_lock_irqsave(&video->irqlock, flags); 1213 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) { 1214 spin_unlock_irqrestore(&video->irqlock, flags); 1215 atomic_set(stopping, 0); 1216 smp_mb(); 1217 return 0; 1218 } 1219 spin_unlock_irqrestore(&video->irqlock, flags); 1220 if (!wait_event_timeout(*wait, !atomic_read(stopping), 1221 msecs_to_jiffies(1000))) { 1222 atomic_set(stopping, 0); 1223 smp_mb(); 1224 return -ETIMEDOUT; 1225 } 1226 } 1227 1228 return 0; 1229} 1230 1231/* 1232 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping 1233 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization 1234 * @stopping: flag which tells module wants to stop 1235 * 1236 * This function checks if ISP submodule was stopping. In case of yes, it 1237 * notices the caller by setting stopping to 0 and waking up the wait queue. 1238 * Returns 1 if it was stopping or 0 otherwise. 1239 */ 1240int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait, 1241 atomic_t *stopping) 1242{ 1243 if (atomic_cmpxchg(stopping, 1, 0)) { 1244 wake_up(wait); 1245 return 1; 1246 } 1247 1248 return 0; 1249} 1250 1251/* -------------------------------------------------------------------------- 1252 * Clock management 1253 */ 1254 1255#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \ 1256 ISPCTRL_HIST_CLK_EN | \ 1257 ISPCTRL_RSZ_CLK_EN | \ 1258 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \ 1259 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN)) 1260 1261static void __isp_subclk_update(struct isp_device *isp) 1262{ 1263 u32 clk = 0; 1264 1265 /* AEWB and AF share the same clock. */ 1266 if (isp->subclk_resources & 1267 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF)) 1268 clk |= ISPCTRL_H3A_CLK_EN; 1269 1270 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST) 1271 clk |= ISPCTRL_HIST_CLK_EN; 1272 1273 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER) 1274 clk |= ISPCTRL_RSZ_CLK_EN; 1275 1276 /* NOTE: For CCDC & Preview submodules, we need to affect internal 1277 * RAM as well. 1278 */ 1279 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC) 1280 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN; 1281 1282 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW) 1283 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN; 1284 1285 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 1286 ISPCTRL_CLKS_MASK, clk); 1287} 1288 1289void omap3isp_subclk_enable(struct isp_device *isp, 1290 enum isp_subclk_resource res) 1291{ 1292 isp->subclk_resources |= res; 1293 1294 __isp_subclk_update(isp); 1295} 1296 1297void omap3isp_subclk_disable(struct isp_device *isp, 1298 enum isp_subclk_resource res) 1299{ 1300 isp->subclk_resources &= ~res; 1301 1302 __isp_subclk_update(isp); 1303} 1304 1305/* 1306 * isp_enable_clocks - Enable ISP clocks 1307 * @isp: OMAP3 ISP device 1308 * 1309 * Return 0 if successful, or clk_prepare_enable return value if any of them 1310 * fails. 1311 */ 1312static int isp_enable_clocks(struct isp_device *isp) 1313{ 1314 int r; 1315 unsigned long rate; 1316 1317 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]); 1318 if (r) { 1319 dev_err(isp->dev, "failed to enable cam_ick clock\n"); 1320 goto out_clk_enable_ick; 1321 } 1322 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ); 1323 if (r) { 1324 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n"); 1325 goto out_clk_enable_mclk; 1326 } 1327 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]); 1328 if (r) { 1329 dev_err(isp->dev, "failed to enable cam_mclk clock\n"); 1330 goto out_clk_enable_mclk; 1331 } 1332 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]); 1333 if (rate != CM_CAM_MCLK_HZ) 1334 dev_warn(isp->dev, "unexpected cam_mclk rate:\n" 1335 " expected : %d\n" 1336 " actual : %ld\n", CM_CAM_MCLK_HZ, rate); 1337 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]); 1338 if (r) { 1339 dev_err(isp->dev, "failed to enable csi2_fck clock\n"); 1340 goto out_clk_enable_csi2_fclk; 1341 } 1342 return 0; 1343 1344out_clk_enable_csi2_fclk: 1345 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]); 1346out_clk_enable_mclk: 1347 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]); 1348out_clk_enable_ick: 1349 return r; 1350} 1351 1352/* 1353 * isp_disable_clocks - Disable ISP clocks 1354 * @isp: OMAP3 ISP device 1355 */ 1356static void isp_disable_clocks(struct isp_device *isp) 1357{ 1358 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]); 1359 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]); 1360 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]); 1361} 1362 1363static const char *isp_clocks[] = { 1364 "cam_ick", 1365 "cam_mclk", 1366 "csi2_96m_fck", 1367 "l3_ick", 1368}; 1369 1370static int isp_get_clocks(struct isp_device *isp) 1371{ 1372 struct clk *clk; 1373 unsigned int i; 1374 1375 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) { 1376 clk = devm_clk_get(isp->dev, isp_clocks[i]); 1377 if (IS_ERR(clk)) { 1378 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]); 1379 return PTR_ERR(clk); 1380 } 1381 1382 isp->clock[i] = clk; 1383 } 1384 1385 return 0; 1386} 1387 1388/* 1389 * omap3isp_get - Acquire the ISP resource. 1390 * 1391 * Initializes the clocks for the first acquire. 1392 * 1393 * Increment the reference count on the ISP. If the first reference is taken, 1394 * enable clocks and power-up all submodules. 1395 * 1396 * Return a pointer to the ISP device structure, or NULL if an error occurred. 1397 */ 1398static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq) 1399{ 1400 struct isp_device *__isp = isp; 1401 1402 if (isp == NULL) 1403 return NULL; 1404 1405 mutex_lock(&isp->isp_mutex); 1406 if (isp->ref_count > 0) 1407 goto out; 1408 1409 if (isp_enable_clocks(isp) < 0) { 1410 __isp = NULL; 1411 goto out; 1412 } 1413 1414 /* We don't want to restore context before saving it! */ 1415 if (isp->has_context) 1416 isp_restore_ctx(isp); 1417 1418 if (irq) 1419 isp_enable_interrupts(isp); 1420 1421out: 1422 if (__isp != NULL) 1423 isp->ref_count++; 1424 mutex_unlock(&isp->isp_mutex); 1425 1426 return __isp; 1427} 1428 1429struct isp_device *omap3isp_get(struct isp_device *isp) 1430{ 1431 return __omap3isp_get(isp, true); 1432} 1433 1434/* 1435 * omap3isp_put - Release the ISP 1436 * 1437 * Decrement the reference count on the ISP. If the last reference is released, 1438 * power-down all submodules, disable clocks and free temporary buffers. 1439 */ 1440static void __omap3isp_put(struct isp_device *isp, bool save_ctx) 1441{ 1442 if (isp == NULL) 1443 return; 1444 1445 mutex_lock(&isp->isp_mutex); 1446 BUG_ON(isp->ref_count == 0); 1447 if (--isp->ref_count == 0) { 1448 isp_disable_interrupts(isp); 1449 if (save_ctx) { 1450 isp_save_ctx(isp); 1451 isp->has_context = 1; 1452 } 1453 /* Reset the ISP if an entity has failed to stop. This is the 1454 * only way to recover from such conditions. 1455 */ 1456 if (!media_entity_enum_empty(&isp->crashed) || 1457 isp->stop_failure) 1458 isp_reset(isp); 1459 isp_disable_clocks(isp); 1460 } 1461 mutex_unlock(&isp->isp_mutex); 1462} 1463 1464void omap3isp_put(struct isp_device *isp) 1465{ 1466 __omap3isp_put(isp, true); 1467} 1468 1469/* -------------------------------------------------------------------------- 1470 * Platform device driver 1471 */ 1472 1473/* 1474 * omap3isp_print_status - Prints the values of the ISP Control Module registers 1475 * @isp: OMAP3 ISP device 1476 */ 1477#define ISP_PRINT_REGISTER(isp, name)\ 1478 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \ 1479 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name)) 1480#define SBL_PRINT_REGISTER(isp, name)\ 1481 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \ 1482 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name)) 1483 1484void omap3isp_print_status(struct isp_device *isp) 1485{ 1486 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n"); 1487 1488 ISP_PRINT_REGISTER(isp, SYSCONFIG); 1489 ISP_PRINT_REGISTER(isp, SYSSTATUS); 1490 ISP_PRINT_REGISTER(isp, IRQ0ENABLE); 1491 ISP_PRINT_REGISTER(isp, IRQ0STATUS); 1492 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH); 1493 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY); 1494 ISP_PRINT_REGISTER(isp, CTRL); 1495 ISP_PRINT_REGISTER(isp, TCTRL_CTRL); 1496 ISP_PRINT_REGISTER(isp, TCTRL_FRAME); 1497 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY); 1498 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY); 1499 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY); 1500 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH); 1501 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH); 1502 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH); 1503 1504 SBL_PRINT_REGISTER(isp, PCR); 1505 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP); 1506 1507 dev_dbg(isp->dev, "--------------------------------------------\n"); 1508} 1509 1510#ifdef CONFIG_PM 1511 1512/* 1513 * Power management support. 1514 * 1515 * As the ISP can't properly handle an input video stream interruption on a non 1516 * frame boundary, the ISP pipelines need to be stopped before sensors get 1517 * suspended. However, as suspending the sensors can require a running clock, 1518 * which can be provided by the ISP, the ISP can't be completely suspended 1519 * before the sensor. 1520 * 1521 * To solve this problem power management support is split into prepare/complete 1522 * and suspend/resume operations. The pipelines are stopped in prepare() and the 1523 * ISP clocks get disabled in suspend(). Similarly, the clocks are re-enabled in 1524 * resume(), and the the pipelines are restarted in complete(). 1525 * 1526 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly 1527 * yet. 1528 */ 1529static int isp_pm_prepare(struct device *dev) 1530{ 1531 struct isp_device *isp = dev_get_drvdata(dev); 1532 int reset; 1533 1534 WARN_ON(mutex_is_locked(&isp->isp_mutex)); 1535 1536 if (isp->ref_count == 0) 1537 return 0; 1538 1539 reset = isp_suspend_modules(isp); 1540 isp_disable_interrupts(isp); 1541 isp_save_ctx(isp); 1542 if (reset) 1543 isp_reset(isp); 1544 1545 return 0; 1546} 1547 1548static int isp_pm_suspend(struct device *dev) 1549{ 1550 struct isp_device *isp = dev_get_drvdata(dev); 1551 1552 WARN_ON(mutex_is_locked(&isp->isp_mutex)); 1553 1554 if (isp->ref_count) 1555 isp_disable_clocks(isp); 1556 1557 return 0; 1558} 1559 1560static int isp_pm_resume(struct device *dev) 1561{ 1562 struct isp_device *isp = dev_get_drvdata(dev); 1563 1564 if (isp->ref_count == 0) 1565 return 0; 1566 1567 return isp_enable_clocks(isp); 1568} 1569 1570static void isp_pm_complete(struct device *dev) 1571{ 1572 struct isp_device *isp = dev_get_drvdata(dev); 1573 1574 if (isp->ref_count == 0) 1575 return; 1576 1577 isp_restore_ctx(isp); 1578 isp_enable_interrupts(isp); 1579 isp_resume_modules(isp); 1580} 1581 1582#else 1583 1584#define isp_pm_prepare NULL 1585#define isp_pm_suspend NULL 1586#define isp_pm_resume NULL 1587#define isp_pm_complete NULL 1588 1589#endif /* CONFIG_PM */ 1590 1591static void isp_unregister_entities(struct isp_device *isp) 1592{ 1593 media_device_unregister(&isp->media_dev); 1594 1595 omap3isp_csi2_unregister_entities(&isp->isp_csi2a); 1596 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2); 1597 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc); 1598 omap3isp_preview_unregister_entities(&isp->isp_prev); 1599 omap3isp_resizer_unregister_entities(&isp->isp_res); 1600 omap3isp_stat_unregister_entities(&isp->isp_aewb); 1601 omap3isp_stat_unregister_entities(&isp->isp_af); 1602 omap3isp_stat_unregister_entities(&isp->isp_hist); 1603 1604 v4l2_device_unregister(&isp->v4l2_dev); 1605 media_device_cleanup(&isp->media_dev); 1606} 1607 1608static int isp_link_entity( 1609 struct isp_device *isp, struct media_entity *entity, 1610 enum isp_interface_type interface) 1611{ 1612 struct media_entity *input; 1613 unsigned int flags; 1614 unsigned int pad; 1615 unsigned int i; 1616 1617 /* Connect the sensor to the correct interface module. 1618 * Parallel sensors are connected directly to the CCDC, while 1619 * serial sensors are connected to the CSI2a, CCP2b or CSI2c 1620 * receiver through CSIPHY1 or CSIPHY2. 1621 */ 1622 switch (interface) { 1623 case ISP_INTERFACE_PARALLEL: 1624 input = &isp->isp_ccdc.subdev.entity; 1625 pad = CCDC_PAD_SINK; 1626 flags = 0; 1627 break; 1628 1629 case ISP_INTERFACE_CSI2A_PHY2: 1630 input = &isp->isp_csi2a.subdev.entity; 1631 pad = CSI2_PAD_SINK; 1632 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED; 1633 break; 1634 1635 case ISP_INTERFACE_CCP2B_PHY1: 1636 case ISP_INTERFACE_CCP2B_PHY2: 1637 input = &isp->isp_ccp2.subdev.entity; 1638 pad = CCP2_PAD_SINK; 1639 flags = 0; 1640 break; 1641 1642 case ISP_INTERFACE_CSI2C_PHY1: 1643 input = &isp->isp_csi2c.subdev.entity; 1644 pad = CSI2_PAD_SINK; 1645 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED; 1646 break; 1647 1648 default: 1649 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__, 1650 interface); 1651 return -EINVAL; 1652 } 1653 1654 /* 1655 * Not all interfaces are available on all revisions of the 1656 * ISP. The sub-devices of those interfaces aren't initialised 1657 * in such a case. Check this by ensuring the num_pads is 1658 * non-zero. 1659 */ 1660 if (!input->num_pads) { 1661 dev_err(isp->dev, "%s: invalid input %u\n", entity->name, 1662 interface); 1663 return -EINVAL; 1664 } 1665 1666 for (i = 0; i < entity->num_pads; i++) { 1667 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE) 1668 break; 1669 } 1670 if (i == entity->num_pads) { 1671 dev_err(isp->dev, "%s: no source pad in external entity %s\n", 1672 __func__, entity->name); 1673 return -EINVAL; 1674 } 1675 1676 return media_create_pad_link(entity, i, input, pad, flags); 1677} 1678 1679static int isp_register_entities(struct isp_device *isp) 1680{ 1681 int ret; 1682 1683 isp->media_dev.dev = isp->dev; 1684 strscpy(isp->media_dev.model, "TI OMAP3 ISP", 1685 sizeof(isp->media_dev.model)); 1686 isp->media_dev.hw_revision = isp->revision; 1687 isp->media_dev.ops = &isp_media_ops; 1688 media_device_init(&isp->media_dev); 1689 1690 isp->v4l2_dev.mdev = &isp->media_dev; 1691 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); 1692 if (ret < 0) { 1693 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", 1694 __func__, ret); 1695 goto done; 1696 } 1697 1698 /* Register internal entities */ 1699 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev); 1700 if (ret < 0) 1701 goto done; 1702 1703 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev); 1704 if (ret < 0) 1705 goto done; 1706 1707 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev); 1708 if (ret < 0) 1709 goto done; 1710 1711 ret = omap3isp_preview_register_entities(&isp->isp_prev, 1712 &isp->v4l2_dev); 1713 if (ret < 0) 1714 goto done; 1715 1716 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev); 1717 if (ret < 0) 1718 goto done; 1719 1720 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev); 1721 if (ret < 0) 1722 goto done; 1723 1724 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev); 1725 if (ret < 0) 1726 goto done; 1727 1728 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev); 1729 if (ret < 0) 1730 goto done; 1731 1732done: 1733 if (ret < 0) 1734 isp_unregister_entities(isp); 1735 1736 return ret; 1737} 1738 1739/* 1740 * isp_create_links() - Create links for internal and external ISP entities 1741 * @isp : Pointer to ISP device 1742 * 1743 * This function creates all links between ISP internal and external entities. 1744 * 1745 * Return: A negative error code on failure or zero on success. Possible error 1746 * codes are those returned by media_create_pad_link(). 1747 */ 1748static int isp_create_links(struct isp_device *isp) 1749{ 1750 int ret; 1751 1752 /* Create links between entities and video nodes. */ 1753 ret = media_create_pad_link( 1754 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE, 1755 &isp->isp_csi2a.video_out.video.entity, 0, 0); 1756 if (ret < 0) 1757 return ret; 1758 1759 ret = media_create_pad_link( 1760 &isp->isp_ccp2.video_in.video.entity, 0, 1761 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0); 1762 if (ret < 0) 1763 return ret; 1764 1765 ret = media_create_pad_link( 1766 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF, 1767 &isp->isp_ccdc.video_out.video.entity, 0, 0); 1768 if (ret < 0) 1769 return ret; 1770 1771 ret = media_create_pad_link( 1772 &isp->isp_prev.video_in.video.entity, 0, 1773 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0); 1774 if (ret < 0) 1775 return ret; 1776 1777 ret = media_create_pad_link( 1778 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE, 1779 &isp->isp_prev.video_out.video.entity, 0, 0); 1780 if (ret < 0) 1781 return ret; 1782 1783 ret = media_create_pad_link( 1784 &isp->isp_res.video_in.video.entity, 0, 1785 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0); 1786 if (ret < 0) 1787 return ret; 1788 1789 ret = media_create_pad_link( 1790 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE, 1791 &isp->isp_res.video_out.video.entity, 0, 0); 1792 1793 if (ret < 0) 1794 return ret; 1795 1796 /* Create links between entities. */ 1797 ret = media_create_pad_link( 1798 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE, 1799 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0); 1800 if (ret < 0) 1801 return ret; 1802 1803 ret = media_create_pad_link( 1804 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE, 1805 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0); 1806 if (ret < 0) 1807 return ret; 1808 1809 ret = media_create_pad_link( 1810 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP, 1811 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0); 1812 if (ret < 0) 1813 return ret; 1814 1815 ret = media_create_pad_link( 1816 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF, 1817 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0); 1818 if (ret < 0) 1819 return ret; 1820 1821 ret = media_create_pad_link( 1822 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE, 1823 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0); 1824 if (ret < 0) 1825 return ret; 1826 1827 ret = media_create_pad_link( 1828 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP, 1829 &isp->isp_aewb.subdev.entity, 0, 1830 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE); 1831 if (ret < 0) 1832 return ret; 1833 1834 ret = media_create_pad_link( 1835 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP, 1836 &isp->isp_af.subdev.entity, 0, 1837 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE); 1838 if (ret < 0) 1839 return ret; 1840 1841 ret = media_create_pad_link( 1842 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP, 1843 &isp->isp_hist.subdev.entity, 0, 1844 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE); 1845 if (ret < 0) 1846 return ret; 1847 1848 return 0; 1849} 1850 1851static void isp_cleanup_modules(struct isp_device *isp) 1852{ 1853 omap3isp_h3a_aewb_cleanup(isp); 1854 omap3isp_h3a_af_cleanup(isp); 1855 omap3isp_hist_cleanup(isp); 1856 omap3isp_resizer_cleanup(isp); 1857 omap3isp_preview_cleanup(isp); 1858 omap3isp_ccdc_cleanup(isp); 1859 omap3isp_ccp2_cleanup(isp); 1860 omap3isp_csi2_cleanup(isp); 1861 omap3isp_csiphy_cleanup(isp); 1862} 1863 1864static int isp_initialize_modules(struct isp_device *isp) 1865{ 1866 int ret; 1867 1868 ret = omap3isp_csiphy_init(isp); 1869 if (ret < 0) { 1870 dev_err(isp->dev, "CSI PHY initialization failed\n"); 1871 return ret; 1872 } 1873 1874 ret = omap3isp_csi2_init(isp); 1875 if (ret < 0) { 1876 dev_err(isp->dev, "CSI2 initialization failed\n"); 1877 goto error_csi2; 1878 } 1879 1880 ret = omap3isp_ccp2_init(isp); 1881 if (ret < 0) { 1882 if (ret != -EPROBE_DEFER) 1883 dev_err(isp->dev, "CCP2 initialization failed\n"); 1884 goto error_ccp2; 1885 } 1886 1887 ret = omap3isp_ccdc_init(isp); 1888 if (ret < 0) { 1889 dev_err(isp->dev, "CCDC initialization failed\n"); 1890 goto error_ccdc; 1891 } 1892 1893 ret = omap3isp_preview_init(isp); 1894 if (ret < 0) { 1895 dev_err(isp->dev, "Preview initialization failed\n"); 1896 goto error_preview; 1897 } 1898 1899 ret = omap3isp_resizer_init(isp); 1900 if (ret < 0) { 1901 dev_err(isp->dev, "Resizer initialization failed\n"); 1902 goto error_resizer; 1903 } 1904 1905 ret = omap3isp_hist_init(isp); 1906 if (ret < 0) { 1907 dev_err(isp->dev, "Histogram initialization failed\n"); 1908 goto error_hist; 1909 } 1910 1911 ret = omap3isp_h3a_aewb_init(isp); 1912 if (ret < 0) { 1913 dev_err(isp->dev, "H3A AEWB initialization failed\n"); 1914 goto error_h3a_aewb; 1915 } 1916 1917 ret = omap3isp_h3a_af_init(isp); 1918 if (ret < 0) { 1919 dev_err(isp->dev, "H3A AF initialization failed\n"); 1920 goto error_h3a_af; 1921 } 1922 1923 return 0; 1924 1925error_h3a_af: 1926 omap3isp_h3a_aewb_cleanup(isp); 1927error_h3a_aewb: 1928 omap3isp_hist_cleanup(isp); 1929error_hist: 1930 omap3isp_resizer_cleanup(isp); 1931error_resizer: 1932 omap3isp_preview_cleanup(isp); 1933error_preview: 1934 omap3isp_ccdc_cleanup(isp); 1935error_ccdc: 1936 omap3isp_ccp2_cleanup(isp); 1937error_ccp2: 1938 omap3isp_csi2_cleanup(isp); 1939error_csi2: 1940 omap3isp_csiphy_cleanup(isp); 1941 1942 return ret; 1943} 1944 1945static void isp_detach_iommu(struct isp_device *isp) 1946{ 1947#ifdef CONFIG_ARM_DMA_USE_IOMMU 1948 arm_iommu_detach_device(isp->dev); 1949 arm_iommu_release_mapping(isp->mapping); 1950 isp->mapping = NULL; 1951#endif 1952} 1953 1954static int isp_attach_iommu(struct isp_device *isp) 1955{ 1956#ifdef CONFIG_ARM_DMA_USE_IOMMU 1957 struct dma_iommu_mapping *mapping; 1958 int ret; 1959 1960 /* 1961 * Create the ARM mapping, used by the ARM DMA mapping core to allocate 1962 * VAs. This will allocate a corresponding IOMMU domain. 1963 */ 1964 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G); 1965 if (IS_ERR(mapping)) { 1966 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n"); 1967 return PTR_ERR(mapping); 1968 } 1969 1970 isp->mapping = mapping; 1971 1972 /* Attach the ARM VA mapping to the device. */ 1973 ret = arm_iommu_attach_device(isp->dev, mapping); 1974 if (ret < 0) { 1975 dev_err(isp->dev, "failed to attach device to VA mapping\n"); 1976 goto error; 1977 } 1978 1979 return 0; 1980 1981error: 1982 arm_iommu_release_mapping(isp->mapping); 1983 isp->mapping = NULL; 1984 return ret; 1985#else 1986 return -ENODEV; 1987#endif 1988} 1989 1990/* 1991 * isp_remove - Remove ISP platform device 1992 * @pdev: Pointer to ISP platform device 1993 * 1994 * Always returns 0. 1995 */ 1996static int isp_remove(struct platform_device *pdev) 1997{ 1998 struct isp_device *isp = platform_get_drvdata(pdev); 1999 2000 v4l2_async_notifier_unregister(&isp->notifier); 2001 isp_unregister_entities(isp); 2002 isp_cleanup_modules(isp); 2003 isp_xclk_cleanup(isp); 2004 2005 __omap3isp_get(isp, false); 2006 isp_detach_iommu(isp); 2007 __omap3isp_put(isp, false); 2008 2009 media_entity_enum_cleanup(&isp->crashed); 2010 v4l2_async_notifier_cleanup(&isp->notifier); 2011 2012 kfree(isp); 2013 2014 return 0; 2015} 2016 2017enum isp_of_phy { 2018 ISP_OF_PHY_PARALLEL = 0, 2019 ISP_OF_PHY_CSIPHY1, 2020 ISP_OF_PHY_CSIPHY2, 2021}; 2022 2023static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async) 2024{ 2025 struct isp_device *isp = container_of(async, struct isp_device, 2026 notifier); 2027 struct v4l2_device *v4l2_dev = &isp->v4l2_dev; 2028 struct v4l2_subdev *sd; 2029 int ret; 2030 2031 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev); 2032 if (ret) 2033 return ret; 2034 2035 list_for_each_entry(sd, &v4l2_dev->subdevs, list) { 2036 if (sd->notifier != &isp->notifier) 2037 continue; 2038 2039 ret = isp_link_entity(isp, &sd->entity, 2040 v4l2_subdev_to_bus_cfg(sd)->interface); 2041 if (ret < 0) 2042 return ret; 2043 } 2044 2045 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); 2046 if (ret < 0) 2047 return ret; 2048 2049 return media_device_register(&isp->media_dev); 2050} 2051 2052static void isp_parse_of_parallel_endpoint(struct device *dev, 2053 struct v4l2_fwnode_endpoint *vep, 2054 struct isp_bus_cfg *buscfg) 2055{ 2056 buscfg->interface = ISP_INTERFACE_PARALLEL; 2057 buscfg->bus.parallel.data_lane_shift = vep->bus.parallel.data_shift; 2058 buscfg->bus.parallel.clk_pol = 2059 !!(vep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING); 2060 buscfg->bus.parallel.hs_pol = 2061 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW); 2062 buscfg->bus.parallel.vs_pol = 2063 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW); 2064 buscfg->bus.parallel.fld_pol = 2065 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW); 2066 buscfg->bus.parallel.data_pol = 2067 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW); 2068 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656; 2069} 2070 2071static void isp_parse_of_csi2_endpoint(struct device *dev, 2072 struct v4l2_fwnode_endpoint *vep, 2073 struct isp_bus_cfg *buscfg) 2074{ 2075 unsigned int i; 2076 2077 buscfg->bus.csi2.lanecfg.clk.pos = vep->bus.mipi_csi2.clock_lane; 2078 buscfg->bus.csi2.lanecfg.clk.pol = 2079 vep->bus.mipi_csi2.lane_polarities[0]; 2080 dev_dbg(dev, "clock lane polarity %u, pos %u\n", 2081 buscfg->bus.csi2.lanecfg.clk.pol, 2082 buscfg->bus.csi2.lanecfg.clk.pos); 2083 2084 buscfg->bus.csi2.num_data_lanes = vep->bus.mipi_csi2.num_data_lanes; 2085 2086 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) { 2087 buscfg->bus.csi2.lanecfg.data[i].pos = 2088 vep->bus.mipi_csi2.data_lanes[i]; 2089 buscfg->bus.csi2.lanecfg.data[i].pol = 2090 vep->bus.mipi_csi2.lane_polarities[i + 1]; 2091 dev_dbg(dev, 2092 "data lane %u polarity %u, pos %u\n", i, 2093 buscfg->bus.csi2.lanecfg.data[i].pol, 2094 buscfg->bus.csi2.lanecfg.data[i].pos); 2095 } 2096 /* 2097 * FIXME: now we assume the CRC is always there. Implement a way to 2098 * obtain this information from the sensor. Frame descriptors, perhaps? 2099 */ 2100 buscfg->bus.csi2.crc = 1; 2101} 2102 2103static void isp_parse_of_csi1_endpoint(struct device *dev, 2104 struct v4l2_fwnode_endpoint *vep, 2105 struct isp_bus_cfg *buscfg) 2106{ 2107 buscfg->bus.ccp2.lanecfg.clk.pos = vep->bus.mipi_csi1.clock_lane; 2108 buscfg->bus.ccp2.lanecfg.clk.pol = vep->bus.mipi_csi1.lane_polarity[0]; 2109 dev_dbg(dev, "clock lane polarity %u, pos %u\n", 2110 buscfg->bus.ccp2.lanecfg.clk.pol, 2111 buscfg->bus.ccp2.lanecfg.clk.pos); 2112 2113 buscfg->bus.ccp2.lanecfg.data[0].pos = vep->bus.mipi_csi1.data_lane; 2114 buscfg->bus.ccp2.lanecfg.data[0].pol = 2115 vep->bus.mipi_csi1.lane_polarity[1]; 2116 2117 dev_dbg(dev, "data lane polarity %u, pos %u\n", 2118 buscfg->bus.ccp2.lanecfg.data[0].pol, 2119 buscfg->bus.ccp2.lanecfg.data[0].pos); 2120 2121 buscfg->bus.ccp2.strobe_clk_pol = vep->bus.mipi_csi1.clock_inv; 2122 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe; 2123 buscfg->bus.ccp2.ccp2_mode = vep->bus_type == V4L2_MBUS_CCP2; 2124 buscfg->bus.ccp2.vp_clk_pol = 1; 2125 2126 buscfg->bus.ccp2.crc = 1; 2127} 2128 2129static struct { 2130 u32 phy; 2131 u32 csi2_if; 2132 u32 csi1_if; 2133} isp_bus_interfaces[2] = { 2134 { ISP_OF_PHY_CSIPHY1, 2135 ISP_INTERFACE_CSI2C_PHY1, ISP_INTERFACE_CCP2B_PHY1 }, 2136 { ISP_OF_PHY_CSIPHY2, 2137 ISP_INTERFACE_CSI2A_PHY2, ISP_INTERFACE_CCP2B_PHY2 }, 2138}; 2139 2140static int isp_parse_of_endpoints(struct isp_device *isp) 2141{ 2142 struct fwnode_handle *ep; 2143 struct isp_async_subdev *isd = NULL; 2144 struct v4l2_async_subdev *asd; 2145 unsigned int i; 2146 2147 ep = fwnode_graph_get_endpoint_by_id( 2148 dev_fwnode(isp->dev), ISP_OF_PHY_PARALLEL, 0, 2149 FWNODE_GRAPH_ENDPOINT_NEXT); 2150 2151 if (ep) { 2152 struct v4l2_fwnode_endpoint vep = { 2153 .bus_type = V4L2_MBUS_PARALLEL 2154 }; 2155 int ret; 2156 2157 dev_dbg(isp->dev, "parsing parallel interface\n"); 2158 2159 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 2160 2161 if (!ret) { 2162 asd = v4l2_async_notifier_add_fwnode_remote_subdev( 2163 &isp->notifier, ep, sizeof(*isd)); 2164 if (!IS_ERR(asd)) { 2165 isd = container_of(asd, struct isp_async_subdev, asd); 2166 isp_parse_of_parallel_endpoint(isp->dev, &vep, &isd->bus); 2167 } 2168 } 2169 2170 fwnode_handle_put(ep); 2171 } 2172 2173 for (i = 0; i < ARRAY_SIZE(isp_bus_interfaces); i++) { 2174 struct v4l2_fwnode_endpoint vep = { 2175 .bus_type = V4L2_MBUS_CSI2_DPHY 2176 }; 2177 int ret; 2178 2179 ep = fwnode_graph_get_endpoint_by_id( 2180 dev_fwnode(isp->dev), isp_bus_interfaces[i].phy, 0, 2181 FWNODE_GRAPH_ENDPOINT_NEXT); 2182 2183 if (!ep) 2184 continue; 2185 2186 dev_dbg(isp->dev, "parsing serial interface %u, node %pOF\n", i, 2187 to_of_node(ep)); 2188 2189 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 2190 if (ret == -ENXIO) { 2191 vep = (struct v4l2_fwnode_endpoint) 2192 { .bus_type = V4L2_MBUS_CSI1 }; 2193 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 2194 2195 if (ret == -ENXIO) { 2196 vep = (struct v4l2_fwnode_endpoint) 2197 { .bus_type = V4L2_MBUS_CCP2 }; 2198 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 2199 } 2200 } 2201 2202 if (!ret) { 2203 asd = v4l2_async_notifier_add_fwnode_remote_subdev( 2204 &isp->notifier, ep, sizeof(*isd)); 2205 2206 if (!IS_ERR(asd)) { 2207 isd = container_of(asd, struct isp_async_subdev, asd); 2208 2209 switch (vep.bus_type) { 2210 case V4L2_MBUS_CSI2_DPHY: 2211 isd->bus.interface = 2212 isp_bus_interfaces[i].csi2_if; 2213 isp_parse_of_csi2_endpoint(isp->dev, &vep, &isd->bus); 2214 break; 2215 case V4L2_MBUS_CSI1: 2216 case V4L2_MBUS_CCP2: 2217 isd->bus.interface = 2218 isp_bus_interfaces[i].csi1_if; 2219 isp_parse_of_csi1_endpoint(isp->dev, &vep, 2220 &isd->bus); 2221 break; 2222 default: 2223 break; 2224 } 2225 } 2226 } 2227 2228 fwnode_handle_put(ep); 2229 } 2230 2231 return 0; 2232} 2233 2234static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = { 2235 .complete = isp_subdev_notifier_complete, 2236}; 2237 2238/* 2239 * isp_probe - Probe ISP platform device 2240 * @pdev: Pointer to ISP platform device 2241 * 2242 * Returns 0 if successful, 2243 * -ENOMEM if no memory available, 2244 * -ENODEV if no platform device resources found 2245 * or no space for remapping registers, 2246 * -EINVAL if couldn't install ISR, 2247 * or clk_get return error value. 2248 */ 2249static int isp_probe(struct platform_device *pdev) 2250{ 2251 struct isp_device *isp; 2252 struct resource *mem; 2253 int ret; 2254 int i, m; 2255 2256 isp = kzalloc(sizeof(*isp), GFP_KERNEL); 2257 if (!isp) { 2258 dev_err(&pdev->dev, "could not allocate memory\n"); 2259 return -ENOMEM; 2260 } 2261 2262 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node), 2263 "ti,phy-type", &isp->phy_type); 2264 if (ret) 2265 goto error_release_isp; 2266 2267 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2268 "syscon"); 2269 if (IS_ERR(isp->syscon)) { 2270 ret = PTR_ERR(isp->syscon); 2271 goto error_release_isp; 2272 } 2273 2274 ret = of_property_read_u32_index(pdev->dev.of_node, 2275 "syscon", 1, &isp->syscon_offset); 2276 if (ret) 2277 goto error_release_isp; 2278 2279 isp->autoidle = autoidle; 2280 2281 mutex_init(&isp->isp_mutex); 2282 spin_lock_init(&isp->stat_lock); 2283 v4l2_async_notifier_init(&isp->notifier); 2284 isp->dev = &pdev->dev; 2285 2286 ret = isp_parse_of_endpoints(isp); 2287 if (ret < 0) 2288 goto error; 2289 2290 isp->ref_count = 0; 2291 2292 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32)); 2293 if (ret) 2294 goto error; 2295 2296 platform_set_drvdata(pdev, isp); 2297 2298 /* Regulators */ 2299 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1"); 2300 if (IS_ERR(isp->isp_csiphy1.vdd)) { 2301 ret = PTR_ERR(isp->isp_csiphy1.vdd); 2302 goto error; 2303 } 2304 2305 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2"); 2306 if (IS_ERR(isp->isp_csiphy2.vdd)) { 2307 ret = PTR_ERR(isp->isp_csiphy2.vdd); 2308 goto error; 2309 } 2310 2311 /* Clocks 2312 * 2313 * The ISP clock tree is revision-dependent. We thus need to enable ICLK 2314 * manually to read the revision before calling __omap3isp_get(). 2315 * 2316 * Start by mapping the ISP MMIO area, which is in two pieces. 2317 * The ISP IOMMU is in between. Map both now, and fill in the 2318 * ISP revision specific portions a little later in the 2319 * function. 2320 */ 2321 for (i = 0; i < 2; i++) { 2322 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0; 2323 2324 mem = platform_get_resource(pdev, IORESOURCE_MEM, i); 2325 isp->mmio_base[map_idx] = 2326 devm_ioremap_resource(isp->dev, mem); 2327 if (IS_ERR(isp->mmio_base[map_idx])) { 2328 ret = PTR_ERR(isp->mmio_base[map_idx]); 2329 goto error; 2330 } 2331 } 2332 2333 ret = isp_get_clocks(isp); 2334 if (ret < 0) 2335 goto error; 2336 2337 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]); 2338 if (ret < 0) 2339 goto error; 2340 2341 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION); 2342 dev_info(isp->dev, "Revision %d.%d found\n", 2343 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f); 2344 2345 clk_disable(isp->clock[ISP_CLK_CAM_ICK]); 2346 2347 if (__omap3isp_get(isp, false) == NULL) { 2348 ret = -ENODEV; 2349 goto error; 2350 } 2351 2352 ret = isp_reset(isp); 2353 if (ret < 0) 2354 goto error_isp; 2355 2356 ret = isp_xclk_init(isp); 2357 if (ret < 0) 2358 goto error_isp; 2359 2360 /* Memory resources */ 2361 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++) 2362 if (isp->revision == isp_res_maps[m].isp_rev) 2363 break; 2364 2365 if (m == ARRAY_SIZE(isp_res_maps)) { 2366 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n", 2367 (isp->revision & 0xf0) >> 4, isp->revision & 0xf); 2368 ret = -ENODEV; 2369 goto error_isp; 2370 } 2371 2372 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++) 2373 isp->mmio_base[i] = 2374 isp->mmio_base[0] + isp_res_maps[m].offset[i]; 2375 2376 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++) 2377 isp->mmio_base[i] = 2378 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1] 2379 + isp_res_maps[m].offset[i]; 2380 2381 isp->mmio_hist_base_phys = 2382 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST]; 2383 2384 /* IOMMU */ 2385 ret = isp_attach_iommu(isp); 2386 if (ret < 0) { 2387 dev_err(&pdev->dev, "unable to attach to IOMMU\n"); 2388 goto error_isp; 2389 } 2390 2391 /* Interrupt */ 2392 ret = platform_get_irq(pdev, 0); 2393 if (ret <= 0) { 2394 ret = -ENODEV; 2395 goto error_iommu; 2396 } 2397 isp->irq_num = ret; 2398 2399 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED, 2400 "OMAP3 ISP", isp)) { 2401 dev_err(isp->dev, "Unable to request IRQ\n"); 2402 ret = -EINVAL; 2403 goto error_iommu; 2404 } 2405 2406 /* Entities */ 2407 ret = isp_initialize_modules(isp); 2408 if (ret < 0) 2409 goto error_iommu; 2410 2411 ret = isp_register_entities(isp); 2412 if (ret < 0) 2413 goto error_modules; 2414 2415 ret = isp_create_links(isp); 2416 if (ret < 0) 2417 goto error_register_entities; 2418 2419 isp->notifier.ops = &isp_subdev_notifier_ops; 2420 2421 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier); 2422 if (ret) 2423 goto error_register_entities; 2424 2425 isp_core_init(isp, 1); 2426 omap3isp_put(isp); 2427 2428 return 0; 2429 2430error_register_entities: 2431 isp_unregister_entities(isp); 2432error_modules: 2433 isp_cleanup_modules(isp); 2434error_iommu: 2435 isp_detach_iommu(isp); 2436error_isp: 2437 isp_xclk_cleanup(isp); 2438 __omap3isp_put(isp, false); 2439error: 2440 v4l2_async_notifier_cleanup(&isp->notifier); 2441 mutex_destroy(&isp->isp_mutex); 2442error_release_isp: 2443 kfree(isp); 2444 2445 return ret; 2446} 2447 2448static const struct dev_pm_ops omap3isp_pm_ops = { 2449 .prepare = isp_pm_prepare, 2450 .suspend = isp_pm_suspend, 2451 .resume = isp_pm_resume, 2452 .complete = isp_pm_complete, 2453}; 2454 2455static const struct platform_device_id omap3isp_id_table[] = { 2456 { "omap3isp", 0 }, 2457 { }, 2458}; 2459MODULE_DEVICE_TABLE(platform, omap3isp_id_table); 2460 2461static const struct of_device_id omap3isp_of_table[] = { 2462 { .compatible = "ti,omap3-isp" }, 2463 { }, 2464}; 2465MODULE_DEVICE_TABLE(of, omap3isp_of_table); 2466 2467static struct platform_driver omap3isp_driver = { 2468 .probe = isp_probe, 2469 .remove = isp_remove, 2470 .id_table = omap3isp_id_table, 2471 .driver = { 2472 .name = "omap3isp", 2473 .pm = &omap3isp_pm_ops, 2474 .of_match_table = omap3isp_of_table, 2475 }, 2476}; 2477 2478module_platform_driver(omap3isp_driver); 2479 2480MODULE_AUTHOR("Nokia Corporation"); 2481MODULE_DESCRIPTION("TI OMAP3 ISP driver"); 2482MODULE_LICENSE("GPL"); 2483MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION); 2484