18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com> 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Original author: 68c2ecf20Sopenharmony_ci * Ben Collins <bcollins@ubuntu.com> 78c2ecf20Sopenharmony_ci * 88c2ecf20Sopenharmony_ci * Additional work by: 98c2ecf20Sopenharmony_ci * John Brooks <john.brooks@bluecherry.net> 108c2ecf20Sopenharmony_ci */ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/kernel.h> 138c2ecf20Sopenharmony_ci#include <linux/fs.h> 148c2ecf20Sopenharmony_ci#include <linux/delay.h> 158c2ecf20Sopenharmony_ci#include <linux/uaccess.h> 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci#include "solo6x10.h" 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_cistatic void solo_gpio_mode(struct solo_dev *solo_dev, 208c2ecf20Sopenharmony_ci unsigned int port_mask, unsigned int mode) 218c2ecf20Sopenharmony_ci{ 228c2ecf20Sopenharmony_ci int port; 238c2ecf20Sopenharmony_ci unsigned int ret; 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_0); 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci /* To set gpio */ 288c2ecf20Sopenharmony_ci for (port = 0; port < 16; port++) { 298c2ecf20Sopenharmony_ci if (!((1 << port) & port_mask)) 308c2ecf20Sopenharmony_ci continue; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci ret &= (~(3 << (port << 1))); 338c2ecf20Sopenharmony_ci ret |= ((mode & 3) << (port << 1)); 348c2ecf20Sopenharmony_ci } 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci solo_reg_write(solo_dev, SOLO_GPIO_CONFIG_0, ret); 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci /* To set extended gpio - sensor */ 398c2ecf20Sopenharmony_ci ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_1); 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci for (port = 0; port < 16; port++) { 428c2ecf20Sopenharmony_ci if (!((1UL << (port + 16)) & port_mask)) 438c2ecf20Sopenharmony_ci continue; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci if (!mode) 468c2ecf20Sopenharmony_ci ret &= ~(1UL << port); 478c2ecf20Sopenharmony_ci else 488c2ecf20Sopenharmony_ci ret |= 1UL << port; 498c2ecf20Sopenharmony_ci } 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci /* Enable GPIO[31:16] */ 528c2ecf20Sopenharmony_ci ret |= 0xffff0000; 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci solo_reg_write(solo_dev, SOLO_GPIO_CONFIG_1, ret); 558c2ecf20Sopenharmony_ci} 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_cistatic void solo_gpio_set(struct solo_dev *solo_dev, unsigned int value) 588c2ecf20Sopenharmony_ci{ 598c2ecf20Sopenharmony_ci solo_reg_write(solo_dev, SOLO_GPIO_DATA_OUT, 608c2ecf20Sopenharmony_ci solo_reg_read(solo_dev, SOLO_GPIO_DATA_OUT) | value); 618c2ecf20Sopenharmony_ci} 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_cistatic void solo_gpio_clear(struct solo_dev *solo_dev, unsigned int value) 648c2ecf20Sopenharmony_ci{ 658c2ecf20Sopenharmony_ci solo_reg_write(solo_dev, SOLO_GPIO_DATA_OUT, 668c2ecf20Sopenharmony_ci solo_reg_read(solo_dev, SOLO_GPIO_DATA_OUT) & ~value); 678c2ecf20Sopenharmony_ci} 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_cistatic void solo_gpio_config(struct solo_dev *solo_dev) 708c2ecf20Sopenharmony_ci{ 718c2ecf20Sopenharmony_ci /* Video reset */ 728c2ecf20Sopenharmony_ci solo_gpio_mode(solo_dev, 0x30, 1); 738c2ecf20Sopenharmony_ci solo_gpio_clear(solo_dev, 0x30); 748c2ecf20Sopenharmony_ci udelay(100); 758c2ecf20Sopenharmony_ci solo_gpio_set(solo_dev, 0x30); 768c2ecf20Sopenharmony_ci udelay(100); 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci /* Warning: Don't touch the next line unless you're sure of what 798c2ecf20Sopenharmony_ci * you're doing: first four gpio [0-3] are used for video. */ 808c2ecf20Sopenharmony_ci solo_gpio_mode(solo_dev, 0x0f, 2); 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci /* We use bit 8-15 of SOLO_GPIO_CONFIG_0 for relay purposes */ 838c2ecf20Sopenharmony_ci solo_gpio_mode(solo_dev, 0xff00, 1); 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci /* Initially set relay status to 0 */ 868c2ecf20Sopenharmony_ci solo_gpio_clear(solo_dev, 0xff00); 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ci /* Set input pins direction */ 898c2ecf20Sopenharmony_ci solo_gpio_mode(solo_dev, 0xffff0000, 0); 908c2ecf20Sopenharmony_ci} 918c2ecf20Sopenharmony_ci 928c2ecf20Sopenharmony_ci#ifdef CONFIG_GPIOLIB 938c2ecf20Sopenharmony_ci/* Pins 0-7 are not exported, because it seems from code above they are 948c2ecf20Sopenharmony_ci * used for internal purposes. So offset 0 corresponds to pin 8, therefore 958c2ecf20Sopenharmony_ci * offsets 0-7 are relay GPIOs, 8-23 - input GPIOs. 968c2ecf20Sopenharmony_ci */ 978c2ecf20Sopenharmony_cistatic int solo_gpiochip_get_direction(struct gpio_chip *chip, 988c2ecf20Sopenharmony_ci unsigned int offset) 998c2ecf20Sopenharmony_ci{ 1008c2ecf20Sopenharmony_ci int ret, mode; 1018c2ecf20Sopenharmony_ci struct solo_dev *solo_dev = gpiochip_get_data(chip); 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci if (offset < 8) { 1048c2ecf20Sopenharmony_ci ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_0); 1058c2ecf20Sopenharmony_ci mode = 3 & (ret >> ((offset + 8) * 2)); 1068c2ecf20Sopenharmony_ci } else { 1078c2ecf20Sopenharmony_ci ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_1); 1088c2ecf20Sopenharmony_ci mode = 1 & (ret >> (offset - 8)); 1098c2ecf20Sopenharmony_ci } 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci if (!mode) 1128c2ecf20Sopenharmony_ci return 1; 1138c2ecf20Sopenharmony_ci else if (mode == 1) 1148c2ecf20Sopenharmony_ci return 0; 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_ci return -1; 1178c2ecf20Sopenharmony_ci} 1188c2ecf20Sopenharmony_ci 1198c2ecf20Sopenharmony_cistatic int solo_gpiochip_direction_input(struct gpio_chip *chip, 1208c2ecf20Sopenharmony_ci unsigned int offset) 1218c2ecf20Sopenharmony_ci{ 1228c2ecf20Sopenharmony_ci return -1; 1238c2ecf20Sopenharmony_ci} 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_cistatic int solo_gpiochip_direction_output(struct gpio_chip *chip, 1268c2ecf20Sopenharmony_ci unsigned int offset, int value) 1278c2ecf20Sopenharmony_ci{ 1288c2ecf20Sopenharmony_ci return -1; 1298c2ecf20Sopenharmony_ci} 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_cistatic int solo_gpiochip_get(struct gpio_chip *chip, 1328c2ecf20Sopenharmony_ci unsigned int offset) 1338c2ecf20Sopenharmony_ci{ 1348c2ecf20Sopenharmony_ci int ret; 1358c2ecf20Sopenharmony_ci struct solo_dev *solo_dev = gpiochip_get_data(chip); 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_ci ret = solo_reg_read(solo_dev, SOLO_GPIO_DATA_IN); 1388c2ecf20Sopenharmony_ci 1398c2ecf20Sopenharmony_ci return 1 & (ret >> (offset + 8)); 1408c2ecf20Sopenharmony_ci} 1418c2ecf20Sopenharmony_ci 1428c2ecf20Sopenharmony_cistatic void solo_gpiochip_set(struct gpio_chip *chip, 1438c2ecf20Sopenharmony_ci unsigned int offset, int value) 1448c2ecf20Sopenharmony_ci{ 1458c2ecf20Sopenharmony_ci struct solo_dev *solo_dev = gpiochip_get_data(chip); 1468c2ecf20Sopenharmony_ci 1478c2ecf20Sopenharmony_ci if (value) 1488c2ecf20Sopenharmony_ci solo_gpio_set(solo_dev, 1 << (offset + 8)); 1498c2ecf20Sopenharmony_ci else 1508c2ecf20Sopenharmony_ci solo_gpio_clear(solo_dev, 1 << (offset + 8)); 1518c2ecf20Sopenharmony_ci} 1528c2ecf20Sopenharmony_ci#endif 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_ciint solo_gpio_init(struct solo_dev *solo_dev) 1558c2ecf20Sopenharmony_ci{ 1568c2ecf20Sopenharmony_ci#ifdef CONFIG_GPIOLIB 1578c2ecf20Sopenharmony_ci int ret; 1588c2ecf20Sopenharmony_ci#endif 1598c2ecf20Sopenharmony_ci 1608c2ecf20Sopenharmony_ci solo_gpio_config(solo_dev); 1618c2ecf20Sopenharmony_ci#ifdef CONFIG_GPIOLIB 1628c2ecf20Sopenharmony_ci solo_dev->gpio_dev.label = SOLO6X10_NAME"_gpio"; 1638c2ecf20Sopenharmony_ci solo_dev->gpio_dev.parent = &solo_dev->pdev->dev; 1648c2ecf20Sopenharmony_ci solo_dev->gpio_dev.owner = THIS_MODULE; 1658c2ecf20Sopenharmony_ci solo_dev->gpio_dev.base = -1; 1668c2ecf20Sopenharmony_ci solo_dev->gpio_dev.ngpio = 24; 1678c2ecf20Sopenharmony_ci solo_dev->gpio_dev.can_sleep = 0; 1688c2ecf20Sopenharmony_ci 1698c2ecf20Sopenharmony_ci solo_dev->gpio_dev.get_direction = solo_gpiochip_get_direction; 1708c2ecf20Sopenharmony_ci solo_dev->gpio_dev.direction_input = solo_gpiochip_direction_input; 1718c2ecf20Sopenharmony_ci solo_dev->gpio_dev.direction_output = solo_gpiochip_direction_output; 1728c2ecf20Sopenharmony_ci solo_dev->gpio_dev.get = solo_gpiochip_get; 1738c2ecf20Sopenharmony_ci solo_dev->gpio_dev.set = solo_gpiochip_set; 1748c2ecf20Sopenharmony_ci 1758c2ecf20Sopenharmony_ci ret = gpiochip_add_data(&solo_dev->gpio_dev, solo_dev); 1768c2ecf20Sopenharmony_ci 1778c2ecf20Sopenharmony_ci if (ret) { 1788c2ecf20Sopenharmony_ci solo_dev->gpio_dev.label = NULL; 1798c2ecf20Sopenharmony_ci return -1; 1808c2ecf20Sopenharmony_ci } 1818c2ecf20Sopenharmony_ci#endif 1828c2ecf20Sopenharmony_ci return 0; 1838c2ecf20Sopenharmony_ci} 1848c2ecf20Sopenharmony_ci 1858c2ecf20Sopenharmony_civoid solo_gpio_exit(struct solo_dev *solo_dev) 1868c2ecf20Sopenharmony_ci{ 1878c2ecf20Sopenharmony_ci#ifdef CONFIG_GPIOLIB 1888c2ecf20Sopenharmony_ci if (solo_dev->gpio_dev.label) { 1898c2ecf20Sopenharmony_ci gpiochip_remove(&solo_dev->gpio_dev); 1908c2ecf20Sopenharmony_ci solo_dev->gpio_dev.label = NULL; 1918c2ecf20Sopenharmony_ci } 1928c2ecf20Sopenharmony_ci#endif 1938c2ecf20Sopenharmony_ci solo_gpio_clear(solo_dev, 0x30); 1948c2ecf20Sopenharmony_ci solo_gpio_config(solo_dev); 1958c2ecf20Sopenharmony_ci} 196