18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * drivers/media/i2c/smiapp-pll.h 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Generic driver for SMIA/SMIA++ compliant camera modules 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Copyright (C) 2012 Nokia Corporation 88c2ecf20Sopenharmony_ci * Contact: Sakari Ailus <sakari.ailus@iki.fi> 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#ifndef SMIAPP_PLL_H 128c2ecf20Sopenharmony_ci#define SMIAPP_PLL_H 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci/* CSI-2 or CCP-2 */ 158c2ecf20Sopenharmony_ci#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00 168c2ecf20Sopenharmony_ci#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci/* op pix clock is for all lanes in total normally */ 198c2ecf20Sopenharmony_ci#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) 208c2ecf20Sopenharmony_ci#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1) 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_cistruct smiapp_pll_branch { 238c2ecf20Sopenharmony_ci uint16_t sys_clk_div; 248c2ecf20Sopenharmony_ci uint16_t pix_clk_div; 258c2ecf20Sopenharmony_ci uint32_t sys_clk_freq_hz; 268c2ecf20Sopenharmony_ci uint32_t pix_clk_freq_hz; 278c2ecf20Sopenharmony_ci}; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_cistruct smiapp_pll { 308c2ecf20Sopenharmony_ci /* input values */ 318c2ecf20Sopenharmony_ci uint8_t bus_type; 328c2ecf20Sopenharmony_ci union { 338c2ecf20Sopenharmony_ci struct { 348c2ecf20Sopenharmony_ci uint8_t lanes; 358c2ecf20Sopenharmony_ci } csi2; 368c2ecf20Sopenharmony_ci struct { 378c2ecf20Sopenharmony_ci uint8_t bus_width; 388c2ecf20Sopenharmony_ci } parallel; 398c2ecf20Sopenharmony_ci }; 408c2ecf20Sopenharmony_ci unsigned long flags; 418c2ecf20Sopenharmony_ci uint8_t binning_horizontal; 428c2ecf20Sopenharmony_ci uint8_t binning_vertical; 438c2ecf20Sopenharmony_ci uint8_t scale_m; 448c2ecf20Sopenharmony_ci uint8_t scale_n; 458c2ecf20Sopenharmony_ci uint8_t bits_per_pixel; 468c2ecf20Sopenharmony_ci uint32_t link_freq; 478c2ecf20Sopenharmony_ci uint32_t ext_clk_freq_hz; 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci /* output values */ 508c2ecf20Sopenharmony_ci uint16_t pre_pll_clk_div; 518c2ecf20Sopenharmony_ci uint16_t pll_multiplier; 528c2ecf20Sopenharmony_ci uint32_t pll_ip_clk_freq_hz; 538c2ecf20Sopenharmony_ci uint32_t pll_op_clk_freq_hz; 548c2ecf20Sopenharmony_ci struct smiapp_pll_branch vt; 558c2ecf20Sopenharmony_ci struct smiapp_pll_branch op; 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci uint32_t pixel_rate_csi; 588c2ecf20Sopenharmony_ci uint32_t pixel_rate_pixel_array; 598c2ecf20Sopenharmony_ci}; 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_cistruct smiapp_pll_branch_limits { 628c2ecf20Sopenharmony_ci uint16_t min_sys_clk_div; 638c2ecf20Sopenharmony_ci uint16_t max_sys_clk_div; 648c2ecf20Sopenharmony_ci uint32_t min_sys_clk_freq_hz; 658c2ecf20Sopenharmony_ci uint32_t max_sys_clk_freq_hz; 668c2ecf20Sopenharmony_ci uint16_t min_pix_clk_div; 678c2ecf20Sopenharmony_ci uint16_t max_pix_clk_div; 688c2ecf20Sopenharmony_ci uint32_t min_pix_clk_freq_hz; 698c2ecf20Sopenharmony_ci uint32_t max_pix_clk_freq_hz; 708c2ecf20Sopenharmony_ci}; 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_cistruct smiapp_pll_limits { 738c2ecf20Sopenharmony_ci /* Strict PLL limits */ 748c2ecf20Sopenharmony_ci uint32_t min_ext_clk_freq_hz; 758c2ecf20Sopenharmony_ci uint32_t max_ext_clk_freq_hz; 768c2ecf20Sopenharmony_ci uint16_t min_pre_pll_clk_div; 778c2ecf20Sopenharmony_ci uint16_t max_pre_pll_clk_div; 788c2ecf20Sopenharmony_ci uint32_t min_pll_ip_freq_hz; 798c2ecf20Sopenharmony_ci uint32_t max_pll_ip_freq_hz; 808c2ecf20Sopenharmony_ci uint16_t min_pll_multiplier; 818c2ecf20Sopenharmony_ci uint16_t max_pll_multiplier; 828c2ecf20Sopenharmony_ci uint32_t min_pll_op_freq_hz; 838c2ecf20Sopenharmony_ci uint32_t max_pll_op_freq_hz; 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci struct smiapp_pll_branch_limits vt; 868c2ecf20Sopenharmony_ci struct smiapp_pll_branch_limits op; 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ci /* Other relevant limits */ 898c2ecf20Sopenharmony_ci uint32_t min_line_length_pck_bin; 908c2ecf20Sopenharmony_ci uint32_t min_line_length_pck; 918c2ecf20Sopenharmony_ci}; 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_cistruct device; 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ciint smiapp_pll_calculate(struct device *dev, 968c2ecf20Sopenharmony_ci const struct smiapp_pll_limits *limits, 978c2ecf20Sopenharmony_ci struct smiapp_pll *pll); 988c2ecf20Sopenharmony_ci 998c2ecf20Sopenharmony_ci#endif /* SMIAPP_PLL_H */ 100