1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the OV7251 camera sensor.
4 *
5 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2017-2018, Linaro Ltd.
7 */
8
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/gpio/consumer.h>
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/regulator/consumer.h>
18#include <linux/slab.h>
19#include <linux/types.h>
20#include <media/v4l2-ctrls.h>
21#include <media/v4l2-fwnode.h>
22#include <media/v4l2-subdev.h>
23
24#define OV7251_SC_MODE_SELECT		0x0100
25#define OV7251_SC_MODE_SELECT_SW_STANDBY	0x0
26#define OV7251_SC_MODE_SELECT_STREAMING		0x1
27
28#define OV7251_CHIP_ID_HIGH		0x300a
29#define OV7251_CHIP_ID_HIGH_BYTE	0x77
30#define OV7251_CHIP_ID_LOW		0x300b
31#define OV7251_CHIP_ID_LOW_BYTE		0x50
32#define OV7251_SC_GP_IO_IN1		0x3029
33#define OV7251_AEC_EXPO_0		0x3500
34#define OV7251_AEC_EXPO_1		0x3501
35#define OV7251_AEC_EXPO_2		0x3502
36#define OV7251_AEC_AGC_ADJ_0		0x350a
37#define OV7251_AEC_AGC_ADJ_1		0x350b
38#define OV7251_TIMING_FORMAT1		0x3820
39#define OV7251_TIMING_FORMAT1_VFLIP	BIT(2)
40#define OV7251_TIMING_FORMAT2		0x3821
41#define OV7251_TIMING_FORMAT2_MIRROR	BIT(2)
42#define OV7251_PRE_ISP_00		0x5e00
43#define OV7251_PRE_ISP_00_TEST_PATTERN	BIT(7)
44
45struct reg_value {
46	u16 reg;
47	u8 val;
48};
49
50struct ov7251_mode_info {
51	u32 width;
52	u32 height;
53	const struct reg_value *data;
54	u32 data_size;
55	u32 pixel_clock;
56	u32 link_freq;
57	u16 exposure_max;
58	u16 exposure_def;
59	struct v4l2_fract timeperframe;
60};
61
62struct ov7251 {
63	struct i2c_client *i2c_client;
64	struct device *dev;
65	struct v4l2_subdev sd;
66	struct media_pad pad;
67	struct v4l2_fwnode_endpoint ep;
68	struct v4l2_mbus_framefmt fmt;
69	struct v4l2_rect crop;
70	struct clk *xclk;
71	u32 xclk_freq;
72
73	struct regulator *io_regulator;
74	struct regulator *core_regulator;
75	struct regulator *analog_regulator;
76
77	const struct ov7251_mode_info *current_mode;
78
79	struct v4l2_ctrl_handler ctrls;
80	struct v4l2_ctrl *pixel_clock;
81	struct v4l2_ctrl *link_freq;
82	struct v4l2_ctrl *exposure;
83	struct v4l2_ctrl *gain;
84
85	/* Cached register values */
86	u8 aec_pk_manual;
87	u8 pre_isp_00;
88	u8 timing_format1;
89	u8 timing_format2;
90
91	struct mutex lock; /* lock to protect power state, ctrls and mode */
92	bool power_on;
93
94	struct gpio_desc *enable_gpio;
95};
96
97static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd)
98{
99	return container_of(sd, struct ov7251, sd);
100}
101
102static const struct reg_value ov7251_global_init_setting[] = {
103	{ 0x0103, 0x01 },
104	{ 0x303b, 0x02 },
105};
106
107static const struct reg_value ov7251_setting_vga_30fps[] = {
108	{ 0x3005, 0x00 },
109	{ 0x3012, 0xc0 },
110	{ 0x3013, 0xd2 },
111	{ 0x3014, 0x04 },
112	{ 0x3016, 0xf0 },
113	{ 0x3017, 0xf0 },
114	{ 0x3018, 0xf0 },
115	{ 0x301a, 0xf0 },
116	{ 0x301b, 0xf0 },
117	{ 0x301c, 0xf0 },
118	{ 0x3023, 0x05 },
119	{ 0x3037, 0xf0 },
120	{ 0x3098, 0x04 }, /* pll2 pre divider */
121	{ 0x3099, 0x28 }, /* pll2 multiplier */
122	{ 0x309a, 0x05 }, /* pll2 sys divider */
123	{ 0x309b, 0x04 }, /* pll2 adc divider */
124	{ 0x309d, 0x00 }, /* pll2 divider */
125	{ 0x30b0, 0x0a }, /* pll1 pix divider */
126	{ 0x30b1, 0x01 }, /* pll1 divider */
127	{ 0x30b3, 0x64 }, /* pll1 multiplier */
128	{ 0x30b4, 0x03 }, /* pll1 pre divider */
129	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
130	{ 0x3106, 0xda },
131	{ 0x3503, 0x07 },
132	{ 0x3509, 0x10 },
133	{ 0x3600, 0x1c },
134	{ 0x3602, 0x62 },
135	{ 0x3620, 0xb7 },
136	{ 0x3622, 0x04 },
137	{ 0x3626, 0x21 },
138	{ 0x3627, 0x30 },
139	{ 0x3630, 0x44 },
140	{ 0x3631, 0x35 },
141	{ 0x3634, 0x60 },
142	{ 0x3636, 0x00 },
143	{ 0x3662, 0x01 },
144	{ 0x3663, 0x70 },
145	{ 0x3664, 0x50 },
146	{ 0x3666, 0x0a },
147	{ 0x3669, 0x1a },
148	{ 0x366a, 0x00 },
149	{ 0x366b, 0x50 },
150	{ 0x3673, 0x01 },
151	{ 0x3674, 0xff },
152	{ 0x3675, 0x03 },
153	{ 0x3705, 0xc1 },
154	{ 0x3709, 0x40 },
155	{ 0x373c, 0x08 },
156	{ 0x3742, 0x00 },
157	{ 0x3757, 0xb3 },
158	{ 0x3788, 0x00 },
159	{ 0x37a8, 0x01 },
160	{ 0x37a9, 0xc0 },
161	{ 0x3800, 0x00 },
162	{ 0x3801, 0x04 },
163	{ 0x3802, 0x00 },
164	{ 0x3803, 0x04 },
165	{ 0x3804, 0x02 },
166	{ 0x3805, 0x8b },
167	{ 0x3806, 0x01 },
168	{ 0x3807, 0xeb },
169	{ 0x3808, 0x02 }, /* width high */
170	{ 0x3809, 0x80 }, /* width low */
171	{ 0x380a, 0x01 }, /* height high */
172	{ 0x380b, 0xe0 }, /* height low */
173	{ 0x380c, 0x03 }, /* total horiz timing high */
174	{ 0x380d, 0xa0 }, /* total horiz timing low */
175	{ 0x380e, 0x06 }, /* total vertical timing high */
176	{ 0x380f, 0xbc }, /* total vertical timing low */
177	{ 0x3810, 0x00 },
178	{ 0x3811, 0x04 },
179	{ 0x3812, 0x00 },
180	{ 0x3813, 0x05 },
181	{ 0x3814, 0x11 },
182	{ 0x3815, 0x11 },
183	{ 0x3820, 0x40 },
184	{ 0x3821, 0x00 },
185	{ 0x382f, 0x0e },
186	{ 0x3832, 0x00 },
187	{ 0x3833, 0x05 },
188	{ 0x3834, 0x00 },
189	{ 0x3835, 0x0c },
190	{ 0x3837, 0x00 },
191	{ 0x3b80, 0x00 },
192	{ 0x3b81, 0xa5 },
193	{ 0x3b82, 0x10 },
194	{ 0x3b83, 0x00 },
195	{ 0x3b84, 0x08 },
196	{ 0x3b85, 0x00 },
197	{ 0x3b86, 0x01 },
198	{ 0x3b87, 0x00 },
199	{ 0x3b88, 0x00 },
200	{ 0x3b89, 0x00 },
201	{ 0x3b8a, 0x00 },
202	{ 0x3b8b, 0x05 },
203	{ 0x3b8c, 0x00 },
204	{ 0x3b8d, 0x00 },
205	{ 0x3b8e, 0x00 },
206	{ 0x3b8f, 0x1a },
207	{ 0x3b94, 0x05 },
208	{ 0x3b95, 0xf2 },
209	{ 0x3b96, 0x40 },
210	{ 0x3c00, 0x89 },
211	{ 0x3c01, 0x63 },
212	{ 0x3c02, 0x01 },
213	{ 0x3c03, 0x00 },
214	{ 0x3c04, 0x00 },
215	{ 0x3c05, 0x03 },
216	{ 0x3c06, 0x00 },
217	{ 0x3c07, 0x06 },
218	{ 0x3c0c, 0x01 },
219	{ 0x3c0d, 0xd0 },
220	{ 0x3c0e, 0x02 },
221	{ 0x3c0f, 0x0a },
222	{ 0x4001, 0x42 },
223	{ 0x4004, 0x04 },
224	{ 0x4005, 0x00 },
225	{ 0x404e, 0x01 },
226	{ 0x4300, 0xff },
227	{ 0x4301, 0x00 },
228	{ 0x4315, 0x00 },
229	{ 0x4501, 0x48 },
230	{ 0x4600, 0x00 },
231	{ 0x4601, 0x4e },
232	{ 0x4801, 0x0f },
233	{ 0x4806, 0x0f },
234	{ 0x4819, 0xaa },
235	{ 0x4823, 0x3e },
236	{ 0x4837, 0x19 },
237	{ 0x4a0d, 0x00 },
238	{ 0x4a47, 0x7f },
239	{ 0x4a49, 0xf0 },
240	{ 0x4a4b, 0x30 },
241	{ 0x5000, 0x85 },
242	{ 0x5001, 0x80 },
243};
244
245static const struct reg_value ov7251_setting_vga_60fps[] = {
246	{ 0x3005, 0x00 },
247	{ 0x3012, 0xc0 },
248	{ 0x3013, 0xd2 },
249	{ 0x3014, 0x04 },
250	{ 0x3016, 0x10 },
251	{ 0x3017, 0x00 },
252	{ 0x3018, 0x00 },
253	{ 0x301a, 0x00 },
254	{ 0x301b, 0x00 },
255	{ 0x301c, 0x00 },
256	{ 0x3023, 0x05 },
257	{ 0x3037, 0xf0 },
258	{ 0x3098, 0x04 }, /* pll2 pre divider */
259	{ 0x3099, 0x28 }, /* pll2 multiplier */
260	{ 0x309a, 0x05 }, /* pll2 sys divider */
261	{ 0x309b, 0x04 }, /* pll2 adc divider */
262	{ 0x309d, 0x00 }, /* pll2 divider */
263	{ 0x30b0, 0x0a }, /* pll1 pix divider */
264	{ 0x30b1, 0x01 }, /* pll1 divider */
265	{ 0x30b3, 0x64 }, /* pll1 multiplier */
266	{ 0x30b4, 0x03 }, /* pll1 pre divider */
267	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
268	{ 0x3106, 0xda },
269	{ 0x3503, 0x07 },
270	{ 0x3509, 0x10 },
271	{ 0x3600, 0x1c },
272	{ 0x3602, 0x62 },
273	{ 0x3620, 0xb7 },
274	{ 0x3622, 0x04 },
275	{ 0x3626, 0x21 },
276	{ 0x3627, 0x30 },
277	{ 0x3630, 0x44 },
278	{ 0x3631, 0x35 },
279	{ 0x3634, 0x60 },
280	{ 0x3636, 0x00 },
281	{ 0x3662, 0x01 },
282	{ 0x3663, 0x70 },
283	{ 0x3664, 0x50 },
284	{ 0x3666, 0x0a },
285	{ 0x3669, 0x1a },
286	{ 0x366a, 0x00 },
287	{ 0x366b, 0x50 },
288	{ 0x3673, 0x01 },
289	{ 0x3674, 0xff },
290	{ 0x3675, 0x03 },
291	{ 0x3705, 0xc1 },
292	{ 0x3709, 0x40 },
293	{ 0x373c, 0x08 },
294	{ 0x3742, 0x00 },
295	{ 0x3757, 0xb3 },
296	{ 0x3788, 0x00 },
297	{ 0x37a8, 0x01 },
298	{ 0x37a9, 0xc0 },
299	{ 0x3800, 0x00 },
300	{ 0x3801, 0x04 },
301	{ 0x3802, 0x00 },
302	{ 0x3803, 0x04 },
303	{ 0x3804, 0x02 },
304	{ 0x3805, 0x8b },
305	{ 0x3806, 0x01 },
306	{ 0x3807, 0xeb },
307	{ 0x3808, 0x02 }, /* width high */
308	{ 0x3809, 0x80 }, /* width low */
309	{ 0x380a, 0x01 }, /* height high */
310	{ 0x380b, 0xe0 }, /* height low */
311	{ 0x380c, 0x03 }, /* total horiz timing high */
312	{ 0x380d, 0xa0 }, /* total horiz timing low */
313	{ 0x380e, 0x03 }, /* total vertical timing high */
314	{ 0x380f, 0x5c }, /* total vertical timing low */
315	{ 0x3810, 0x00 },
316	{ 0x3811, 0x04 },
317	{ 0x3812, 0x00 },
318	{ 0x3813, 0x05 },
319	{ 0x3814, 0x11 },
320	{ 0x3815, 0x11 },
321	{ 0x3820, 0x40 },
322	{ 0x3821, 0x00 },
323	{ 0x382f, 0x0e },
324	{ 0x3832, 0x00 },
325	{ 0x3833, 0x05 },
326	{ 0x3834, 0x00 },
327	{ 0x3835, 0x0c },
328	{ 0x3837, 0x00 },
329	{ 0x3b80, 0x00 },
330	{ 0x3b81, 0xa5 },
331	{ 0x3b82, 0x10 },
332	{ 0x3b83, 0x00 },
333	{ 0x3b84, 0x08 },
334	{ 0x3b85, 0x00 },
335	{ 0x3b86, 0x01 },
336	{ 0x3b87, 0x00 },
337	{ 0x3b88, 0x00 },
338	{ 0x3b89, 0x00 },
339	{ 0x3b8a, 0x00 },
340	{ 0x3b8b, 0x05 },
341	{ 0x3b8c, 0x00 },
342	{ 0x3b8d, 0x00 },
343	{ 0x3b8e, 0x00 },
344	{ 0x3b8f, 0x1a },
345	{ 0x3b94, 0x05 },
346	{ 0x3b95, 0xf2 },
347	{ 0x3b96, 0x40 },
348	{ 0x3c00, 0x89 },
349	{ 0x3c01, 0x63 },
350	{ 0x3c02, 0x01 },
351	{ 0x3c03, 0x00 },
352	{ 0x3c04, 0x00 },
353	{ 0x3c05, 0x03 },
354	{ 0x3c06, 0x00 },
355	{ 0x3c07, 0x06 },
356	{ 0x3c0c, 0x01 },
357	{ 0x3c0d, 0xd0 },
358	{ 0x3c0e, 0x02 },
359	{ 0x3c0f, 0x0a },
360	{ 0x4001, 0x42 },
361	{ 0x4004, 0x04 },
362	{ 0x4005, 0x00 },
363	{ 0x404e, 0x01 },
364	{ 0x4300, 0xff },
365	{ 0x4301, 0x00 },
366	{ 0x4315, 0x00 },
367	{ 0x4501, 0x48 },
368	{ 0x4600, 0x00 },
369	{ 0x4601, 0x4e },
370	{ 0x4801, 0x0f },
371	{ 0x4806, 0x0f },
372	{ 0x4819, 0xaa },
373	{ 0x4823, 0x3e },
374	{ 0x4837, 0x19 },
375	{ 0x4a0d, 0x00 },
376	{ 0x4a47, 0x7f },
377	{ 0x4a49, 0xf0 },
378	{ 0x4a4b, 0x30 },
379	{ 0x5000, 0x85 },
380	{ 0x5001, 0x80 },
381};
382
383static const struct reg_value ov7251_setting_vga_90fps[] = {
384	{ 0x3005, 0x00 },
385	{ 0x3012, 0xc0 },
386	{ 0x3013, 0xd2 },
387	{ 0x3014, 0x04 },
388	{ 0x3016, 0x10 },
389	{ 0x3017, 0x00 },
390	{ 0x3018, 0x00 },
391	{ 0x301a, 0x00 },
392	{ 0x301b, 0x00 },
393	{ 0x301c, 0x00 },
394	{ 0x3023, 0x05 },
395	{ 0x3037, 0xf0 },
396	{ 0x3098, 0x04 }, /* pll2 pre divider */
397	{ 0x3099, 0x28 }, /* pll2 multiplier */
398	{ 0x309a, 0x05 }, /* pll2 sys divider */
399	{ 0x309b, 0x04 }, /* pll2 adc divider */
400	{ 0x309d, 0x00 }, /* pll2 divider */
401	{ 0x30b0, 0x0a }, /* pll1 pix divider */
402	{ 0x30b1, 0x01 }, /* pll1 divider */
403	{ 0x30b3, 0x64 }, /* pll1 multiplier */
404	{ 0x30b4, 0x03 }, /* pll1 pre divider */
405	{ 0x30b5, 0x05 }, /* pll1 mipi divider */
406	{ 0x3106, 0xda },
407	{ 0x3503, 0x07 },
408	{ 0x3509, 0x10 },
409	{ 0x3600, 0x1c },
410	{ 0x3602, 0x62 },
411	{ 0x3620, 0xb7 },
412	{ 0x3622, 0x04 },
413	{ 0x3626, 0x21 },
414	{ 0x3627, 0x30 },
415	{ 0x3630, 0x44 },
416	{ 0x3631, 0x35 },
417	{ 0x3634, 0x60 },
418	{ 0x3636, 0x00 },
419	{ 0x3662, 0x01 },
420	{ 0x3663, 0x70 },
421	{ 0x3664, 0x50 },
422	{ 0x3666, 0x0a },
423	{ 0x3669, 0x1a },
424	{ 0x366a, 0x00 },
425	{ 0x366b, 0x50 },
426	{ 0x3673, 0x01 },
427	{ 0x3674, 0xff },
428	{ 0x3675, 0x03 },
429	{ 0x3705, 0xc1 },
430	{ 0x3709, 0x40 },
431	{ 0x373c, 0x08 },
432	{ 0x3742, 0x00 },
433	{ 0x3757, 0xb3 },
434	{ 0x3788, 0x00 },
435	{ 0x37a8, 0x01 },
436	{ 0x37a9, 0xc0 },
437	{ 0x3800, 0x00 },
438	{ 0x3801, 0x04 },
439	{ 0x3802, 0x00 },
440	{ 0x3803, 0x04 },
441	{ 0x3804, 0x02 },
442	{ 0x3805, 0x8b },
443	{ 0x3806, 0x01 },
444	{ 0x3807, 0xeb },
445	{ 0x3808, 0x02 }, /* width high */
446	{ 0x3809, 0x80 }, /* width low */
447	{ 0x380a, 0x01 }, /* height high */
448	{ 0x380b, 0xe0 }, /* height low */
449	{ 0x380c, 0x03 }, /* total horiz timing high */
450	{ 0x380d, 0xa0 }, /* total horiz timing low */
451	{ 0x380e, 0x02 }, /* total vertical timing high */
452	{ 0x380f, 0x3c }, /* total vertical timing low */
453	{ 0x3810, 0x00 },
454	{ 0x3811, 0x04 },
455	{ 0x3812, 0x00 },
456	{ 0x3813, 0x05 },
457	{ 0x3814, 0x11 },
458	{ 0x3815, 0x11 },
459	{ 0x3820, 0x40 },
460	{ 0x3821, 0x00 },
461	{ 0x382f, 0x0e },
462	{ 0x3832, 0x00 },
463	{ 0x3833, 0x05 },
464	{ 0x3834, 0x00 },
465	{ 0x3835, 0x0c },
466	{ 0x3837, 0x00 },
467	{ 0x3b80, 0x00 },
468	{ 0x3b81, 0xa5 },
469	{ 0x3b82, 0x10 },
470	{ 0x3b83, 0x00 },
471	{ 0x3b84, 0x08 },
472	{ 0x3b85, 0x00 },
473	{ 0x3b86, 0x01 },
474	{ 0x3b87, 0x00 },
475	{ 0x3b88, 0x00 },
476	{ 0x3b89, 0x00 },
477	{ 0x3b8a, 0x00 },
478	{ 0x3b8b, 0x05 },
479	{ 0x3b8c, 0x00 },
480	{ 0x3b8d, 0x00 },
481	{ 0x3b8e, 0x00 },
482	{ 0x3b8f, 0x1a },
483	{ 0x3b94, 0x05 },
484	{ 0x3b95, 0xf2 },
485	{ 0x3b96, 0x40 },
486	{ 0x3c00, 0x89 },
487	{ 0x3c01, 0x63 },
488	{ 0x3c02, 0x01 },
489	{ 0x3c03, 0x00 },
490	{ 0x3c04, 0x00 },
491	{ 0x3c05, 0x03 },
492	{ 0x3c06, 0x00 },
493	{ 0x3c07, 0x06 },
494	{ 0x3c0c, 0x01 },
495	{ 0x3c0d, 0xd0 },
496	{ 0x3c0e, 0x02 },
497	{ 0x3c0f, 0x0a },
498	{ 0x4001, 0x42 },
499	{ 0x4004, 0x04 },
500	{ 0x4005, 0x00 },
501	{ 0x404e, 0x01 },
502	{ 0x4300, 0xff },
503	{ 0x4301, 0x00 },
504	{ 0x4315, 0x00 },
505	{ 0x4501, 0x48 },
506	{ 0x4600, 0x00 },
507	{ 0x4601, 0x4e },
508	{ 0x4801, 0x0f },
509	{ 0x4806, 0x0f },
510	{ 0x4819, 0xaa },
511	{ 0x4823, 0x3e },
512	{ 0x4837, 0x19 },
513	{ 0x4a0d, 0x00 },
514	{ 0x4a47, 0x7f },
515	{ 0x4a49, 0xf0 },
516	{ 0x4a4b, 0x30 },
517	{ 0x5000, 0x85 },
518	{ 0x5001, 0x80 },
519};
520
521static const s64 link_freq[] = {
522	240000000,
523};
524
525static const struct ov7251_mode_info ov7251_mode_info_data[] = {
526	{
527		.width = 640,
528		.height = 480,
529		.data = ov7251_setting_vga_30fps,
530		.data_size = ARRAY_SIZE(ov7251_setting_vga_30fps),
531		.pixel_clock = 48000000,
532		.link_freq = 0, /* an index in link_freq[] */
533		.exposure_max = 1704,
534		.exposure_def = 504,
535		.timeperframe = {
536			.numerator = 100,
537			.denominator = 3000
538		}
539	},
540	{
541		.width = 640,
542		.height = 480,
543		.data = ov7251_setting_vga_60fps,
544		.data_size = ARRAY_SIZE(ov7251_setting_vga_60fps),
545		.pixel_clock = 48000000,
546		.link_freq = 0, /* an index in link_freq[] */
547		.exposure_max = 840,
548		.exposure_def = 504,
549		.timeperframe = {
550			.numerator = 100,
551			.denominator = 6014
552		}
553	},
554	{
555		.width = 640,
556		.height = 480,
557		.data = ov7251_setting_vga_90fps,
558		.data_size = ARRAY_SIZE(ov7251_setting_vga_90fps),
559		.pixel_clock = 48000000,
560		.link_freq = 0, /* an index in link_freq[] */
561		.exposure_max = 552,
562		.exposure_def = 504,
563		.timeperframe = {
564			.numerator = 100,
565			.denominator = 9043
566		}
567	},
568};
569
570static int ov7251_regulators_enable(struct ov7251 *ov7251)
571{
572	int ret;
573
574	/* OV7251 power up sequence requires core regulator
575	 * to be enabled not earlier than io regulator
576	 */
577
578	ret = regulator_enable(ov7251->io_regulator);
579	if (ret < 0) {
580		dev_err(ov7251->dev, "set io voltage failed\n");
581		return ret;
582	}
583
584	ret = regulator_enable(ov7251->analog_regulator);
585	if (ret) {
586		dev_err(ov7251->dev, "set analog voltage failed\n");
587		goto err_disable_io;
588	}
589
590	ret = regulator_enable(ov7251->core_regulator);
591	if (ret) {
592		dev_err(ov7251->dev, "set core voltage failed\n");
593		goto err_disable_analog;
594	}
595
596	return 0;
597
598err_disable_analog:
599	regulator_disable(ov7251->analog_regulator);
600
601err_disable_io:
602	regulator_disable(ov7251->io_regulator);
603
604	return ret;
605}
606
607static void ov7251_regulators_disable(struct ov7251 *ov7251)
608{
609	int ret;
610
611	ret = regulator_disable(ov7251->core_regulator);
612	if (ret < 0)
613		dev_err(ov7251->dev, "core regulator disable failed\n");
614
615	ret = regulator_disable(ov7251->analog_regulator);
616	if (ret < 0)
617		dev_err(ov7251->dev, "analog regulator disable failed\n");
618
619	ret = regulator_disable(ov7251->io_regulator);
620	if (ret < 0)
621		dev_err(ov7251->dev, "io regulator disable failed\n");
622}
623
624static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val)
625{
626	u8 regbuf[3];
627	int ret;
628
629	regbuf[0] = reg >> 8;
630	regbuf[1] = reg & 0xff;
631	regbuf[2] = val;
632
633	ret = i2c_master_send(ov7251->i2c_client, regbuf, 3);
634	if (ret < 0) {
635		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n",
636			__func__, ret, reg, val);
637		return ret;
638	}
639
640	return 0;
641}
642
643static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val,
644				 u8 num)
645{
646	u8 regbuf[5];
647	u8 nregbuf = sizeof(reg) + num * sizeof(*val);
648	int ret = 0;
649
650	if (nregbuf > sizeof(regbuf))
651		return -EINVAL;
652
653	regbuf[0] = reg >> 8;
654	regbuf[1] = reg & 0xff;
655
656	memcpy(regbuf + 2, val, num);
657
658	ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf);
659	if (ret < 0) {
660		dev_err(ov7251->dev,
661			"%s: write seq regs error %d: first reg=%x\n",
662			__func__, ret, reg);
663		return ret;
664	}
665
666	return 0;
667}
668
669static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val)
670{
671	u8 regbuf[2];
672	int ret;
673
674	regbuf[0] = reg >> 8;
675	regbuf[1] = reg & 0xff;
676
677	ret = i2c_master_send(ov7251->i2c_client, regbuf, 2);
678	if (ret < 0) {
679		dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n",
680			__func__, ret, reg);
681		return ret;
682	}
683
684	ret = i2c_master_recv(ov7251->i2c_client, val, 1);
685	if (ret < 0) {
686		dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n",
687			__func__, ret, reg);
688		return ret;
689	}
690
691	return 0;
692}
693
694static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure)
695{
696	u16 reg;
697	u8 val[3];
698
699	reg = OV7251_AEC_EXPO_0;
700	val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */
701	val[1] = (exposure & 0x0ff0) >> 4;  /* goes to OV7251_AEC_EXPO_1 */
702	val[2] = (exposure & 0x000f) << 4;  /* goes to OV7251_AEC_EXPO_2 */
703
704	return ov7251_write_seq_regs(ov7251, reg, val, 3);
705}
706
707static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain)
708{
709	u16 reg;
710	u8 val[2];
711
712	reg = OV7251_AEC_AGC_ADJ_0;
713	val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */
714	val[1] = gain & 0xff;          /* goes to OV7251_AEC_AGC_ADJ_1 */
715
716	return ov7251_write_seq_regs(ov7251, reg, val, 2);
717}
718
719static int ov7251_set_register_array(struct ov7251 *ov7251,
720				     const struct reg_value *settings,
721				     unsigned int num_settings)
722{
723	unsigned int i;
724	int ret;
725
726	for (i = 0; i < num_settings; ++i, ++settings) {
727		ret = ov7251_write_reg(ov7251, settings->reg, settings->val);
728		if (ret < 0)
729			return ret;
730	}
731
732	return 0;
733}
734
735static int ov7251_set_power_on(struct ov7251 *ov7251)
736{
737	int ret;
738	u32 wait_us;
739
740	ret = ov7251_regulators_enable(ov7251);
741	if (ret < 0)
742		return ret;
743
744	ret = clk_prepare_enable(ov7251->xclk);
745	if (ret < 0) {
746		dev_err(ov7251->dev, "clk prepare enable failed\n");
747		ov7251_regulators_disable(ov7251);
748		return ret;
749	}
750
751	gpiod_set_value_cansleep(ov7251->enable_gpio, 1);
752
753	/* wait at least 65536 external clock cycles */
754	wait_us = DIV_ROUND_UP(65536 * 1000,
755			       DIV_ROUND_UP(ov7251->xclk_freq, 1000));
756	usleep_range(wait_us, wait_us + 1000);
757
758	return 0;
759}
760
761static void ov7251_set_power_off(struct ov7251 *ov7251)
762{
763	clk_disable_unprepare(ov7251->xclk);
764	gpiod_set_value_cansleep(ov7251->enable_gpio, 0);
765	ov7251_regulators_disable(ov7251);
766}
767
768static int ov7251_s_power(struct v4l2_subdev *sd, int on)
769{
770	struct ov7251 *ov7251 = to_ov7251(sd);
771	int ret = 0;
772
773	mutex_lock(&ov7251->lock);
774
775	/* If the power state is not modified - no work to do. */
776	if (ov7251->power_on == !!on)
777		goto exit;
778
779	if (on) {
780		ret = ov7251_set_power_on(ov7251);
781		if (ret < 0)
782			goto exit;
783
784		ret = ov7251_set_register_array(ov7251,
785					ov7251_global_init_setting,
786					ARRAY_SIZE(ov7251_global_init_setting));
787		if (ret < 0) {
788			dev_err(ov7251->dev, "could not set init registers\n");
789			ov7251_set_power_off(ov7251);
790			goto exit;
791		}
792
793		ov7251->power_on = true;
794	} else {
795		ov7251_set_power_off(ov7251);
796		ov7251->power_on = false;
797	}
798
799exit:
800	mutex_unlock(&ov7251->lock);
801
802	return ret;
803}
804
805static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value)
806{
807	u8 val = ov7251->timing_format2;
808	int ret;
809
810	if (value)
811		val |= OV7251_TIMING_FORMAT2_MIRROR;
812	else
813		val &= ~OV7251_TIMING_FORMAT2_MIRROR;
814
815	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val);
816	if (!ret)
817		ov7251->timing_format2 = val;
818
819	return ret;
820}
821
822static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value)
823{
824	u8 val = ov7251->timing_format1;
825	int ret;
826
827	if (value)
828		val |= OV7251_TIMING_FORMAT1_VFLIP;
829	else
830		val &= ~OV7251_TIMING_FORMAT1_VFLIP;
831
832	ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val);
833	if (!ret)
834		ov7251->timing_format1 = val;
835
836	return ret;
837}
838
839static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value)
840{
841	u8 val = ov7251->pre_isp_00;
842	int ret;
843
844	if (value)
845		val |= OV7251_PRE_ISP_00_TEST_PATTERN;
846	else
847		val &= ~OV7251_PRE_ISP_00_TEST_PATTERN;
848
849	ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val);
850	if (!ret)
851		ov7251->pre_isp_00 = val;
852
853	return ret;
854}
855
856static const char * const ov7251_test_pattern_menu[] = {
857	"Disabled",
858	"Vertical Pattern Bars",
859};
860
861static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl)
862{
863	struct ov7251 *ov7251 = container_of(ctrl->handler,
864					     struct ov7251, ctrls);
865	int ret;
866
867	/* v4l2_ctrl_lock() locks our mutex */
868
869	if (!ov7251->power_on)
870		return 0;
871
872	switch (ctrl->id) {
873	case V4L2_CID_EXPOSURE:
874		ret = ov7251_set_exposure(ov7251, ctrl->val);
875		break;
876	case V4L2_CID_GAIN:
877		ret = ov7251_set_gain(ov7251, ctrl->val);
878		break;
879	case V4L2_CID_TEST_PATTERN:
880		ret = ov7251_set_test_pattern(ov7251, ctrl->val);
881		break;
882	case V4L2_CID_HFLIP:
883		ret = ov7251_set_hflip(ov7251, ctrl->val);
884		break;
885	case V4L2_CID_VFLIP:
886		ret = ov7251_set_vflip(ov7251, ctrl->val);
887		break;
888	default:
889		ret = -EINVAL;
890		break;
891	}
892
893	return ret;
894}
895
896static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
897	.s_ctrl = ov7251_s_ctrl,
898};
899
900static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
901				 struct v4l2_subdev_pad_config *cfg,
902				 struct v4l2_subdev_mbus_code_enum *code)
903{
904	if (code->index > 0)
905		return -EINVAL;
906
907	code->code = MEDIA_BUS_FMT_Y10_1X10;
908
909	return 0;
910}
911
912static int ov7251_enum_frame_size(struct v4l2_subdev *subdev,
913				  struct v4l2_subdev_pad_config *cfg,
914				  struct v4l2_subdev_frame_size_enum *fse)
915{
916	if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
917		return -EINVAL;
918
919	if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data))
920		return -EINVAL;
921
922	fse->min_width = ov7251_mode_info_data[fse->index].width;
923	fse->max_width = ov7251_mode_info_data[fse->index].width;
924	fse->min_height = ov7251_mode_info_data[fse->index].height;
925	fse->max_height = ov7251_mode_info_data[fse->index].height;
926
927	return 0;
928}
929
930static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev,
931				  struct v4l2_subdev_pad_config *cfg,
932				  struct v4l2_subdev_frame_interval_enum *fie)
933{
934	unsigned int index = fie->index;
935	unsigned int i;
936
937	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
938		if (fie->width != ov7251_mode_info_data[i].width ||
939		    fie->height != ov7251_mode_info_data[i].height)
940			continue;
941
942		if (index-- == 0) {
943			fie->interval = ov7251_mode_info_data[i].timeperframe;
944			return 0;
945		}
946	}
947
948	return -EINVAL;
949}
950
951static struct v4l2_mbus_framefmt *
952__ov7251_get_pad_format(struct ov7251 *ov7251,
953			struct v4l2_subdev_pad_config *cfg,
954			unsigned int pad,
955			enum v4l2_subdev_format_whence which)
956{
957	switch (which) {
958	case V4L2_SUBDEV_FORMAT_TRY:
959		return v4l2_subdev_get_try_format(&ov7251->sd, cfg, pad);
960	case V4L2_SUBDEV_FORMAT_ACTIVE:
961		return &ov7251->fmt;
962	default:
963		return NULL;
964	}
965}
966
967static int ov7251_get_format(struct v4l2_subdev *sd,
968			     struct v4l2_subdev_pad_config *cfg,
969			     struct v4l2_subdev_format *format)
970{
971	struct ov7251 *ov7251 = to_ov7251(sd);
972
973	mutex_lock(&ov7251->lock);
974	format->format = *__ov7251_get_pad_format(ov7251, cfg, format->pad,
975						  format->which);
976	mutex_unlock(&ov7251->lock);
977
978	return 0;
979}
980
981static struct v4l2_rect *
982__ov7251_get_pad_crop(struct ov7251 *ov7251, struct v4l2_subdev_pad_config *cfg,
983		      unsigned int pad, enum v4l2_subdev_format_whence which)
984{
985	switch (which) {
986	case V4L2_SUBDEV_FORMAT_TRY:
987		return v4l2_subdev_get_try_crop(&ov7251->sd, cfg, pad);
988	case V4L2_SUBDEV_FORMAT_ACTIVE:
989		return &ov7251->crop;
990	default:
991		return NULL;
992	}
993}
994
995static inline u32 avg_fps(const struct v4l2_fract *t)
996{
997	return (t->denominator + (t->numerator >> 1)) / t->numerator;
998}
999
1000static const struct ov7251_mode_info *
1001ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe)
1002{
1003	const struct ov7251_mode_info *mode = ov7251->current_mode;
1004	unsigned int fps_req = avg_fps(timeperframe);
1005	unsigned int max_dist_match = (unsigned int) -1;
1006	unsigned int i, n = 0;
1007
1008	for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) {
1009		unsigned int dist;
1010		unsigned int fps_tmp;
1011
1012		if (mode->width != ov7251_mode_info_data[i].width ||
1013		    mode->height != ov7251_mode_info_data[i].height)
1014			continue;
1015
1016		fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe);
1017
1018		dist = abs(fps_req - fps_tmp);
1019
1020		if (dist < max_dist_match) {
1021			n = i;
1022			max_dist_match = dist;
1023		}
1024	}
1025
1026	return &ov7251_mode_info_data[n];
1027}
1028
1029static int ov7251_set_format(struct v4l2_subdev *sd,
1030			     struct v4l2_subdev_pad_config *cfg,
1031			     struct v4l2_subdev_format *format)
1032{
1033	struct ov7251 *ov7251 = to_ov7251(sd);
1034	struct v4l2_mbus_framefmt *__format;
1035	struct v4l2_rect *__crop;
1036	const struct ov7251_mode_info *new_mode;
1037	int ret = 0;
1038
1039	mutex_lock(&ov7251->lock);
1040
1041	__crop = __ov7251_get_pad_crop(ov7251, cfg, format->pad, format->which);
1042
1043	new_mode = v4l2_find_nearest_size(ov7251_mode_info_data,
1044				ARRAY_SIZE(ov7251_mode_info_data),
1045				width, height,
1046				format->format.width, format->format.height);
1047
1048	__crop->width = new_mode->width;
1049	__crop->height = new_mode->height;
1050
1051	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1052		ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock,
1053					       new_mode->pixel_clock);
1054		if (ret < 0)
1055			goto exit;
1056
1057		ret = __v4l2_ctrl_s_ctrl(ov7251->link_freq,
1058					 new_mode->link_freq);
1059		if (ret < 0)
1060			goto exit;
1061
1062		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1063					       1, new_mode->exposure_max,
1064					       1, new_mode->exposure_def);
1065		if (ret < 0)
1066			goto exit;
1067
1068		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1069					 new_mode->exposure_def);
1070		if (ret < 0)
1071			goto exit;
1072
1073		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1074		if (ret < 0)
1075			goto exit;
1076
1077		ov7251->current_mode = new_mode;
1078	}
1079
1080	__format = __ov7251_get_pad_format(ov7251, cfg, format->pad,
1081					   format->which);
1082	__format->width = __crop->width;
1083	__format->height = __crop->height;
1084	__format->code = MEDIA_BUS_FMT_Y10_1X10;
1085	__format->field = V4L2_FIELD_NONE;
1086	__format->colorspace = V4L2_COLORSPACE_SRGB;
1087	__format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace);
1088	__format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
1089				__format->colorspace, __format->ycbcr_enc);
1090	__format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace);
1091
1092	format->format = *__format;
1093
1094exit:
1095	mutex_unlock(&ov7251->lock);
1096
1097	return ret;
1098}
1099
1100static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev,
1101				  struct v4l2_subdev_pad_config *cfg)
1102{
1103	struct v4l2_subdev_format fmt = {
1104		.which = cfg ? V4L2_SUBDEV_FORMAT_TRY
1105			     : V4L2_SUBDEV_FORMAT_ACTIVE,
1106		.format = {
1107			.width = 640,
1108			.height = 480
1109		}
1110	};
1111
1112	ov7251_set_format(subdev, cfg, &fmt);
1113
1114	return 0;
1115}
1116
1117static int ov7251_get_selection(struct v4l2_subdev *sd,
1118				struct v4l2_subdev_pad_config *cfg,
1119				struct v4l2_subdev_selection *sel)
1120{
1121	struct ov7251 *ov7251 = to_ov7251(sd);
1122
1123	if (sel->target != V4L2_SEL_TGT_CROP)
1124		return -EINVAL;
1125
1126	mutex_lock(&ov7251->lock);
1127	sel->r = *__ov7251_get_pad_crop(ov7251, cfg, sel->pad,
1128					sel->which);
1129	mutex_unlock(&ov7251->lock);
1130
1131	return 0;
1132}
1133
1134static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable)
1135{
1136	struct ov7251 *ov7251 = to_ov7251(subdev);
1137	int ret;
1138
1139	mutex_lock(&ov7251->lock);
1140
1141	if (enable) {
1142		ret = ov7251_set_register_array(ov7251,
1143					ov7251->current_mode->data,
1144					ov7251->current_mode->data_size);
1145		if (ret < 0) {
1146			dev_err(ov7251->dev, "could not set mode %dx%d\n",
1147				ov7251->current_mode->width,
1148				ov7251->current_mode->height);
1149			goto exit;
1150		}
1151		ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls);
1152		if (ret < 0) {
1153			dev_err(ov7251->dev, "could not sync v4l2 controls\n");
1154			goto exit;
1155		}
1156		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1157				       OV7251_SC_MODE_SELECT_STREAMING);
1158	} else {
1159		ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT,
1160				       OV7251_SC_MODE_SELECT_SW_STANDBY);
1161	}
1162
1163exit:
1164	mutex_unlock(&ov7251->lock);
1165
1166	return ret;
1167}
1168
1169static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,
1170				     struct v4l2_subdev_frame_interval *fi)
1171{
1172	struct ov7251 *ov7251 = to_ov7251(subdev);
1173
1174	mutex_lock(&ov7251->lock);
1175	fi->interval = ov7251->current_mode->timeperframe;
1176	mutex_unlock(&ov7251->lock);
1177
1178	return 0;
1179}
1180
1181static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,
1182				     struct v4l2_subdev_frame_interval *fi)
1183{
1184	struct ov7251 *ov7251 = to_ov7251(subdev);
1185	const struct ov7251_mode_info *new_mode;
1186	int ret = 0;
1187
1188	mutex_lock(&ov7251->lock);
1189	new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval);
1190
1191	if (new_mode != ov7251->current_mode) {
1192		ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock,
1193					       new_mode->pixel_clock);
1194		if (ret < 0)
1195			goto exit;
1196
1197		ret = __v4l2_ctrl_s_ctrl(ov7251->link_freq,
1198					 new_mode->link_freq);
1199		if (ret < 0)
1200			goto exit;
1201
1202		ret = __v4l2_ctrl_modify_range(ov7251->exposure,
1203					       1, new_mode->exposure_max,
1204					       1, new_mode->exposure_def);
1205		if (ret < 0)
1206			goto exit;
1207
1208		ret = __v4l2_ctrl_s_ctrl(ov7251->exposure,
1209					 new_mode->exposure_def);
1210		if (ret < 0)
1211			goto exit;
1212
1213		ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16);
1214		if (ret < 0)
1215			goto exit;
1216
1217		ov7251->current_mode = new_mode;
1218	}
1219
1220	fi->interval = ov7251->current_mode->timeperframe;
1221
1222exit:
1223	mutex_unlock(&ov7251->lock);
1224
1225	return ret;
1226}
1227
1228static const struct v4l2_subdev_core_ops ov7251_core_ops = {
1229	.s_power = ov7251_s_power,
1230};
1231
1232static const struct v4l2_subdev_video_ops ov7251_video_ops = {
1233	.s_stream = ov7251_s_stream,
1234	.g_frame_interval = ov7251_get_frame_interval,
1235	.s_frame_interval = ov7251_set_frame_interval,
1236};
1237
1238static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {
1239	.init_cfg = ov7251_entity_init_cfg,
1240	.enum_mbus_code = ov7251_enum_mbus_code,
1241	.enum_frame_size = ov7251_enum_frame_size,
1242	.enum_frame_interval = ov7251_enum_frame_ival,
1243	.get_fmt = ov7251_get_format,
1244	.set_fmt = ov7251_set_format,
1245	.get_selection = ov7251_get_selection,
1246};
1247
1248static const struct v4l2_subdev_ops ov7251_subdev_ops = {
1249	.core = &ov7251_core_ops,
1250	.video = &ov7251_video_ops,
1251	.pad = &ov7251_subdev_pad_ops,
1252};
1253
1254static int ov7251_probe(struct i2c_client *client)
1255{
1256	struct device *dev = &client->dev;
1257	struct fwnode_handle *endpoint;
1258	struct ov7251 *ov7251;
1259	u8 chip_id_high, chip_id_low, chip_rev;
1260	int ret;
1261
1262	ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL);
1263	if (!ov7251)
1264		return -ENOMEM;
1265
1266	ov7251->i2c_client = client;
1267	ov7251->dev = dev;
1268
1269	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1270	if (!endpoint) {
1271		dev_err(dev, "endpoint node not found\n");
1272		return -EINVAL;
1273	}
1274
1275	ret = v4l2_fwnode_endpoint_parse(endpoint, &ov7251->ep);
1276	fwnode_handle_put(endpoint);
1277	if (ret < 0) {
1278		dev_err(dev, "parsing endpoint node failed\n");
1279		return ret;
1280	}
1281
1282	if (ov7251->ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1283		dev_err(dev, "invalid bus type (%u), must be CSI2 (%u)\n",
1284			ov7251->ep.bus_type, V4L2_MBUS_CSI2_DPHY);
1285		return -EINVAL;
1286	}
1287
1288	/* get system clock (xclk) */
1289	ov7251->xclk = devm_clk_get(dev, "xclk");
1290	if (IS_ERR(ov7251->xclk)) {
1291		dev_err(dev, "could not get xclk");
1292		return PTR_ERR(ov7251->xclk);
1293	}
1294
1295	ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1296				       &ov7251->xclk_freq);
1297	if (ret) {
1298		dev_err(dev, "could not get xclk frequency\n");
1299		return ret;
1300	}
1301
1302	/* external clock must be 24MHz, allow 1% tolerance */
1303	if (ov7251->xclk_freq < 23760000 || ov7251->xclk_freq > 24240000) {
1304		dev_err(dev, "external clock frequency %u is not supported\n",
1305			ov7251->xclk_freq);
1306		return -EINVAL;
1307	}
1308
1309	ret = clk_set_rate(ov7251->xclk, ov7251->xclk_freq);
1310	if (ret) {
1311		dev_err(dev, "could not set xclk frequency\n");
1312		return ret;
1313	}
1314
1315	ov7251->io_regulator = devm_regulator_get(dev, "vdddo");
1316	if (IS_ERR(ov7251->io_regulator)) {
1317		dev_err(dev, "cannot get io regulator\n");
1318		return PTR_ERR(ov7251->io_regulator);
1319	}
1320
1321	ov7251->core_regulator = devm_regulator_get(dev, "vddd");
1322	if (IS_ERR(ov7251->core_regulator)) {
1323		dev_err(dev, "cannot get core regulator\n");
1324		return PTR_ERR(ov7251->core_regulator);
1325	}
1326
1327	ov7251->analog_regulator = devm_regulator_get(dev, "vdda");
1328	if (IS_ERR(ov7251->analog_regulator)) {
1329		dev_err(dev, "cannot get analog regulator\n");
1330		return PTR_ERR(ov7251->analog_regulator);
1331	}
1332
1333	ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1334	if (IS_ERR(ov7251->enable_gpio)) {
1335		dev_err(dev, "cannot get enable gpio\n");
1336		return PTR_ERR(ov7251->enable_gpio);
1337	}
1338
1339	mutex_init(&ov7251->lock);
1340
1341	v4l2_ctrl_handler_init(&ov7251->ctrls, 7);
1342	ov7251->ctrls.lock = &ov7251->lock;
1343
1344	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1345			  V4L2_CID_HFLIP, 0, 1, 1, 0);
1346	v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1347			  V4L2_CID_VFLIP, 0, 1, 1, 0);
1348	ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1349					     V4L2_CID_EXPOSURE, 1, 32, 1, 32);
1350	ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,
1351					 V4L2_CID_GAIN, 16, 1023, 1, 16);
1352	v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops,
1353				     V4L2_CID_TEST_PATTERN,
1354				     ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
1355				     0, 0, ov7251_test_pattern_menu);
1356	ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls,
1357						&ov7251_ctrl_ops,
1358						V4L2_CID_PIXEL_RATE,
1359						1, INT_MAX, 1, 1);
1360	ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls,
1361						   &ov7251_ctrl_ops,
1362						   V4L2_CID_LINK_FREQ,
1363						   ARRAY_SIZE(link_freq) - 1,
1364						   0, link_freq);
1365	if (ov7251->link_freq)
1366		ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1367
1368	ov7251->sd.ctrl_handler = &ov7251->ctrls;
1369
1370	if (ov7251->ctrls.error) {
1371		dev_err(dev, "%s: control initialization error %d\n",
1372			__func__, ov7251->ctrls.error);
1373		ret = ov7251->ctrls.error;
1374		goto free_ctrl;
1375	}
1376
1377	v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);
1378	ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1379	ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
1380	ov7251->sd.dev = &client->dev;
1381	ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1382
1383	ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad);
1384	if (ret < 0) {
1385		dev_err(dev, "could not register media entity\n");
1386		goto free_ctrl;
1387	}
1388
1389	ret = ov7251_s_power(&ov7251->sd, true);
1390	if (ret < 0) {
1391		dev_err(dev, "could not power up OV7251\n");
1392		goto free_entity;
1393	}
1394
1395	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high);
1396	if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) {
1397		dev_err(dev, "could not read ID high\n");
1398		ret = -ENODEV;
1399		goto power_down;
1400	}
1401	ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low);
1402	if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) {
1403		dev_err(dev, "could not read ID low\n");
1404		ret = -ENODEV;
1405		goto power_down;
1406	}
1407
1408	ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev);
1409	if (ret < 0) {
1410		dev_err(dev, "could not read revision\n");
1411		ret = -ENODEV;
1412		goto power_down;
1413	}
1414	chip_rev >>= 4;
1415
1416	dev_info(dev, "OV7251 revision %x (%s) detected at address 0x%02x\n",
1417		 chip_rev,
1418		 chip_rev == 0x4 ? "1A / 1B" :
1419		 chip_rev == 0x5 ? "1C / 1D" :
1420		 chip_rev == 0x6 ? "1E" :
1421		 chip_rev == 0x7 ? "1F" : "unknown",
1422		 client->addr);
1423
1424	ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00,
1425			      &ov7251->pre_isp_00);
1426	if (ret < 0) {
1427		dev_err(dev, "could not read test pattern value\n");
1428		ret = -ENODEV;
1429		goto power_down;
1430	}
1431
1432	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1,
1433			      &ov7251->timing_format1);
1434	if (ret < 0) {
1435		dev_err(dev, "could not read vflip value\n");
1436		ret = -ENODEV;
1437		goto power_down;
1438	}
1439
1440	ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2,
1441			      &ov7251->timing_format2);
1442	if (ret < 0) {
1443		dev_err(dev, "could not read hflip value\n");
1444		ret = -ENODEV;
1445		goto power_down;
1446	}
1447
1448	ov7251_s_power(&ov7251->sd, false);
1449
1450	ret = v4l2_async_register_subdev(&ov7251->sd);
1451	if (ret < 0) {
1452		dev_err(dev, "could not register v4l2 device\n");
1453		goto free_entity;
1454	}
1455
1456	ov7251_entity_init_cfg(&ov7251->sd, NULL);
1457
1458	return 0;
1459
1460power_down:
1461	ov7251_s_power(&ov7251->sd, false);
1462free_entity:
1463	media_entity_cleanup(&ov7251->sd.entity);
1464free_ctrl:
1465	v4l2_ctrl_handler_free(&ov7251->ctrls);
1466	mutex_destroy(&ov7251->lock);
1467
1468	return ret;
1469}
1470
1471static int ov7251_remove(struct i2c_client *client)
1472{
1473	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1474	struct ov7251 *ov7251 = to_ov7251(sd);
1475
1476	v4l2_async_unregister_subdev(&ov7251->sd);
1477	media_entity_cleanup(&ov7251->sd.entity);
1478	v4l2_ctrl_handler_free(&ov7251->ctrls);
1479	mutex_destroy(&ov7251->lock);
1480
1481	return 0;
1482}
1483
1484static const struct of_device_id ov7251_of_match[] = {
1485	{ .compatible = "ovti,ov7251" },
1486	{ /* sentinel */ }
1487};
1488MODULE_DEVICE_TABLE(of, ov7251_of_match);
1489
1490static struct i2c_driver ov7251_i2c_driver = {
1491	.driver = {
1492		.of_match_table = ov7251_of_match,
1493		.name  = "ov7251",
1494	},
1495	.probe_new  = ov7251_probe,
1496	.remove = ov7251_remove,
1497};
1498
1499module_i2c_driver(ov7251_i2c_driver);
1500
1501MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver");
1502MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1503MODULE_LICENSE("GPL v2");
1504