1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Aptina Sensor PLL Configuration
4 *
5 * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 */
7
8#include <linux/device.h>
9#include <linux/gcd.h>
10#include <linux/kernel.h>
11#include <linux/lcm.h>
12#include <linux/module.h>
13
14#include "aptina-pll.h"
15
16int aptina_pll_calculate(struct device *dev,
17			 const struct aptina_pll_limits *limits,
18			 struct aptina_pll *pll)
19{
20	unsigned int mf_min;
21	unsigned int mf_max;
22	unsigned int p1_min;
23	unsigned int p1_max;
24	unsigned int p1;
25	unsigned int div;
26
27	dev_dbg(dev, "PLL: ext clock %u pix clock %u\n",
28		pll->ext_clock, pll->pix_clock);
29
30	if (pll->ext_clock < limits->ext_clock_min ||
31	    pll->ext_clock > limits->ext_clock_max) {
32		dev_err(dev, "pll: invalid external clock frequency.\n");
33		return -EINVAL;
34	}
35
36	if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) {
37		dev_err(dev, "pll: invalid pixel clock frequency.\n");
38		return -EINVAL;
39	}
40
41	/* Compute the multiplier M and combined N*P1 divisor. */
42	div = gcd(pll->pix_clock, pll->ext_clock);
43	pll->m = pll->pix_clock / div;
44	div = pll->ext_clock / div;
45
46	/* We now have the smallest M and N*P1 values that will result in the
47	 * desired pixel clock frequency, but they might be out of the valid
48	 * range. Compute the factor by which we should multiply them given the
49	 * following constraints:
50	 *
51	 * - minimum/maximum multiplier
52	 * - minimum/maximum multiplier output clock frequency assuming the
53	 *   minimum/maximum N value
54	 * - minimum/maximum combined N*P1 divisor
55	 */
56	mf_min = DIV_ROUND_UP(limits->m_min, pll->m);
57	mf_min = max(mf_min, limits->out_clock_min /
58		     (pll->ext_clock / limits->n_min * pll->m));
59	mf_min = max(mf_min, limits->n_min * limits->p1_min / div);
60	mf_max = limits->m_max / pll->m;
61	mf_max = min(mf_max, limits->out_clock_max /
62		    (pll->ext_clock / limits->n_max * pll->m));
63	mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div));
64
65	dev_dbg(dev, "pll: mf min %u max %u\n", mf_min, mf_max);
66	if (mf_min > mf_max) {
67		dev_err(dev, "pll: no valid combined N*P1 divisor.\n");
68		return -EINVAL;
69	}
70
71	/*
72	 * We're looking for the highest acceptable P1 value for which a
73	 * multiplier factor MF exists that fulfills the following conditions:
74	 *
75	 * 1. p1 is in the [p1_min, p1_max] range given by the limits and is
76	 *    even
77	 * 2. mf is in the [mf_min, mf_max] range computed above
78	 * 3. div * mf is a multiple of p1, in order to compute
79	 *	n = div * mf / p1
80	 *	m = pll->m * mf
81	 * 4. the internal clock frequency, given by ext_clock / n, is in the
82	 *    [int_clock_min, int_clock_max] range given by the limits
83	 * 5. the output clock frequency, given by ext_clock / n * m, is in the
84	 *    [out_clock_min, out_clock_max] range given by the limits
85	 *
86	 * The first naive approach is to iterate over all p1 values acceptable
87	 * according to (1) and all mf values acceptable according to (2), and
88	 * stop at the first combination that fulfills (3), (4) and (5). This
89	 * has a O(n^2) complexity.
90	 *
91	 * Instead of iterating over all mf values in the [mf_min, mf_max] range
92	 * we can compute the mf increment between two acceptable values
93	 * according to (3) with
94	 *
95	 *	mf_inc = p1 / gcd(div, p1)			(6)
96	 *
97	 * and round the minimum up to the nearest multiple of mf_inc. This will
98	 * restrict the number of mf values to be checked.
99	 *
100	 * Furthermore, conditions (4) and (5) only restrict the range of
101	 * acceptable p1 and mf values by modifying the minimum and maximum
102	 * limits. (5) can be expressed as
103	 *
104	 *	ext_clock / (div * mf / p1) * m * mf >= out_clock_min
105	 *	ext_clock / (div * mf / p1) * m * mf <= out_clock_max
106	 *
107	 * or
108	 *
109	 *	p1 >= out_clock_min * div / (ext_clock * m)	(7)
110	 *	p1 <= out_clock_max * div / (ext_clock * m)
111	 *
112	 * Similarly, (4) can be expressed as
113	 *
114	 *	mf >= ext_clock * p1 / (int_clock_max * div)	(8)
115	 *	mf <= ext_clock * p1 / (int_clock_min * div)
116	 *
117	 * We can thus iterate over the restricted p1 range defined by the
118	 * combination of (1) and (7), and then compute the restricted mf range
119	 * defined by the combination of (2), (6) and (8). If the resulting mf
120	 * range is not empty, any value in the mf range is acceptable. We thus
121	 * select the mf lwoer bound and the corresponding p1 value.
122	 */
123	if (limits->p1_min == 0) {
124		dev_err(dev, "pll: P1 minimum value must be >0.\n");
125		return -EINVAL;
126	}
127
128	p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div,
129		     pll->ext_clock * pll->m));
130	p1_max = min(limits->p1_max, limits->out_clock_max * div /
131		     (pll->ext_clock * pll->m));
132
133	for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) {
134		unsigned int mf_inc = p1 / gcd(div, p1);
135		unsigned int mf_high;
136		unsigned int mf_low;
137
138		mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1,
139					limits->int_clock_max * div)), mf_inc);
140		mf_high = min(mf_max, pll->ext_clock * p1 /
141			      (limits->int_clock_min * div));
142
143		if (mf_low > mf_high)
144			continue;
145
146		pll->n = div * mf_low / p1;
147		pll->m *= mf_low;
148		pll->p1 = p1;
149		dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1);
150		return 0;
151	}
152
153	dev_err(dev, "pll: no valid N and P1 divisors found.\n");
154	return -EINVAL;
155}
156EXPORT_SYMBOL_GPL(aptina_pll_calculate);
157
158MODULE_DESCRIPTION("Aptina PLL Helpers");
159MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
160MODULE_LICENSE("GPL v2");
161