1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 NXP TDA10048HN DVB OFDM demodulator driver 4 5 Copyright (C) 2009 Steven Toth <stoth@kernellabs.com> 6 7 8*/ 9 10#include <linux/kernel.h> 11#include <linux/init.h> 12#include <linux/module.h> 13#include <linux/string.h> 14#include <linux/slab.h> 15#include <linux/delay.h> 16#include <linux/math64.h> 17#include <asm/div64.h> 18#include <media/dvb_frontend.h> 19#include <media/dvb_math.h> 20#include "tda10048.h" 21 22#define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw" 23#define TDA10048_DEFAULT_FIRMWARE_SIZE 24878 24 25/* Register name definitions */ 26#define TDA10048_IDENTITY 0x00 27#define TDA10048_VERSION 0x01 28#define TDA10048_DSP_CODE_CPT 0x0C 29#define TDA10048_DSP_CODE_IN 0x0E 30#define TDA10048_IN_CONF1 0x10 31#define TDA10048_IN_CONF2 0x11 32#define TDA10048_IN_CONF3 0x12 33#define TDA10048_OUT_CONF1 0x14 34#define TDA10048_OUT_CONF2 0x15 35#define TDA10048_OUT_CONF3 0x16 36#define TDA10048_AUTO 0x18 37#define TDA10048_SYNC_STATUS 0x1A 38#define TDA10048_CONF_C4_1 0x1E 39#define TDA10048_CONF_C4_2 0x1F 40#define TDA10048_CODE_IN_RAM 0x20 41#define TDA10048_CHANNEL_INFO1_R 0x22 42#define TDA10048_CHANNEL_INFO2_R 0x23 43#define TDA10048_CHANNEL_INFO1 0x24 44#define TDA10048_CHANNEL_INFO2 0x25 45#define TDA10048_TIME_ERROR_R 0x26 46#define TDA10048_TIME_ERROR 0x27 47#define TDA10048_FREQ_ERROR_LSB_R 0x28 48#define TDA10048_FREQ_ERROR_MSB_R 0x29 49#define TDA10048_FREQ_ERROR_LSB 0x2A 50#define TDA10048_FREQ_ERROR_MSB 0x2B 51#define TDA10048_IT_SEL 0x30 52#define TDA10048_IT_STAT 0x32 53#define TDA10048_DSP_AD_LSB 0x3C 54#define TDA10048_DSP_AD_MSB 0x3D 55#define TDA10048_DSP_REG_LSB 0x3E 56#define TDA10048_DSP_REG_MSB 0x3F 57#define TDA10048_CONF_TRISTATE1 0x44 58#define TDA10048_CONF_TRISTATE2 0x45 59#define TDA10048_CONF_POLARITY 0x46 60#define TDA10048_GPIO_SP_DS0 0x48 61#define TDA10048_GPIO_SP_DS1 0x49 62#define TDA10048_GPIO_SP_DS2 0x4A 63#define TDA10048_GPIO_SP_DS3 0x4B 64#define TDA10048_GPIO_OUT_SEL 0x4C 65#define TDA10048_GPIO_SELECT 0x4D 66#define TDA10048_IC_MODE 0x4E 67#define TDA10048_CONF_XO 0x50 68#define TDA10048_CONF_PLL1 0x51 69#define TDA10048_CONF_PLL2 0x52 70#define TDA10048_CONF_PLL3 0x53 71#define TDA10048_CONF_ADC 0x54 72#define TDA10048_CONF_ADC_2 0x55 73#define TDA10048_CONF_C1_1 0x60 74#define TDA10048_CONF_C1_3 0x62 75#define TDA10048_AGC_CONF 0x70 76#define TDA10048_AGC_THRESHOLD_LSB 0x72 77#define TDA10048_AGC_THRESHOLD_MSB 0x73 78#define TDA10048_AGC_RENORM 0x74 79#define TDA10048_AGC_GAINS 0x76 80#define TDA10048_AGC_TUN_MIN 0x78 81#define TDA10048_AGC_TUN_MAX 0x79 82#define TDA10048_AGC_IF_MIN 0x7A 83#define TDA10048_AGC_IF_MAX 0x7B 84#define TDA10048_AGC_TUN_LEVEL 0x7E 85#define TDA10048_AGC_IF_LEVEL 0x7F 86#define TDA10048_DIG_AGC_LEVEL 0x81 87#define TDA10048_FREQ_PHY2_LSB 0x86 88#define TDA10048_FREQ_PHY2_MSB 0x87 89#define TDA10048_TIME_INVWREF_LSB 0x88 90#define TDA10048_TIME_INVWREF_MSB 0x89 91#define TDA10048_TIME_WREF_LSB 0x8A 92#define TDA10048_TIME_WREF_MID1 0x8B 93#define TDA10048_TIME_WREF_MID2 0x8C 94#define TDA10048_TIME_WREF_MSB 0x8D 95#define TDA10048_NP_OUT 0xA2 96#define TDA10048_CELL_ID_LSB 0xA4 97#define TDA10048_CELL_ID_MSB 0xA5 98#define TDA10048_EXTTPS_ODD 0xAA 99#define TDA10048_EXTTPS_EVEN 0xAB 100#define TDA10048_TPS_LENGTH 0xAC 101#define TDA10048_FREE_REG_1 0xB2 102#define TDA10048_FREE_REG_2 0xB3 103#define TDA10048_CONF_C3_1 0xC0 104#define TDA10048_CVBER_CTRL 0xC2 105#define TDA10048_CBER_NMAX_LSB 0xC4 106#define TDA10048_CBER_NMAX_MSB 0xC5 107#define TDA10048_CBER_LSB 0xC6 108#define TDA10048_CBER_MSB 0xC7 109#define TDA10048_VBER_LSB 0xC8 110#define TDA10048_VBER_MID 0xC9 111#define TDA10048_VBER_MSB 0xCA 112#define TDA10048_CVBER_LUT 0xCC 113#define TDA10048_UNCOR_CTRL 0xCD 114#define TDA10048_UNCOR_CPT_LSB 0xCE 115#define TDA10048_UNCOR_CPT_MSB 0xCF 116#define TDA10048_SOFT_IT_C3 0xD6 117#define TDA10048_CONF_TS2 0xE0 118#define TDA10048_CONF_TS1 0xE1 119 120static unsigned int debug; 121 122#define dprintk(level, fmt, arg...)\ 123 do { if (debug >= level)\ 124 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\ 125 } while (0) 126 127struct tda10048_state { 128 129 struct i2c_adapter *i2c; 130 131 /* We'll cache and update the attach config settings */ 132 struct tda10048_config config; 133 struct dvb_frontend frontend; 134 135 int fwloaded; 136 137 u32 freq_if_hz; 138 u32 xtal_hz; 139 u32 pll_mfactor; 140 u32 pll_nfactor; 141 u32 pll_pfactor; 142 u32 sample_freq; 143 144 u32 bandwidth; 145}; 146 147static struct init_tab { 148 u8 reg; 149 u16 data; 150} init_tab[] = { 151 { TDA10048_CONF_PLL1, 0x08 }, 152 { TDA10048_CONF_ADC_2, 0x00 }, 153 { TDA10048_CONF_C4_1, 0x00 }, 154 { TDA10048_CONF_PLL1, 0x0f }, 155 { TDA10048_CONF_PLL2, 0x0a }, 156 { TDA10048_CONF_PLL3, 0x43 }, 157 { TDA10048_FREQ_PHY2_LSB, 0x02 }, 158 { TDA10048_FREQ_PHY2_MSB, 0x0a }, 159 { TDA10048_TIME_WREF_LSB, 0xbd }, 160 { TDA10048_TIME_WREF_MID1, 0xe4 }, 161 { TDA10048_TIME_WREF_MID2, 0xa8 }, 162 { TDA10048_TIME_WREF_MSB, 0x02 }, 163 { TDA10048_TIME_INVWREF_LSB, 0x04 }, 164 { TDA10048_TIME_INVWREF_MSB, 0x06 }, 165 { TDA10048_CONF_C4_1, 0x00 }, 166 { TDA10048_CONF_C1_1, 0xa8 }, 167 { TDA10048_AGC_CONF, 0x16 }, 168 { TDA10048_CONF_C1_3, 0x0b }, 169 { TDA10048_AGC_TUN_MIN, 0x00 }, 170 { TDA10048_AGC_TUN_MAX, 0xff }, 171 { TDA10048_AGC_IF_MIN, 0x00 }, 172 { TDA10048_AGC_IF_MAX, 0xff }, 173 { TDA10048_AGC_THRESHOLD_MSB, 0x00 }, 174 { TDA10048_AGC_THRESHOLD_LSB, 0x70 }, 175 { TDA10048_CVBER_CTRL, 0x38 }, 176 { TDA10048_AGC_GAINS, 0x12 }, 177 { TDA10048_CONF_XO, 0x00 }, 178 { TDA10048_CONF_TS1, 0x07 }, 179 { TDA10048_IC_MODE, 0x00 }, 180 { TDA10048_CONF_TS2, 0xc0 }, 181 { TDA10048_CONF_TRISTATE1, 0x21 }, 182 { TDA10048_CONF_TRISTATE2, 0x00 }, 183 { TDA10048_CONF_POLARITY, 0x00 }, 184 { TDA10048_CONF_C4_2, 0x04 }, 185 { TDA10048_CONF_ADC, 0x60 }, 186 { TDA10048_CONF_ADC_2, 0x10 }, 187 { TDA10048_CONF_ADC, 0x60 }, 188 { TDA10048_CONF_ADC_2, 0x00 }, 189 { TDA10048_CONF_C1_1, 0xa8 }, 190 { TDA10048_UNCOR_CTRL, 0x00 }, 191 { TDA10048_CONF_C4_2, 0x04 }, 192}; 193 194static struct pll_tab { 195 u32 clk_freq_khz; 196 u32 if_freq_khz; 197} pll_tab[] = { 198 { TDA10048_CLK_4000, TDA10048_IF_36130 }, 199 { TDA10048_CLK_16000, TDA10048_IF_3300 }, 200 { TDA10048_CLK_16000, TDA10048_IF_3500 }, 201 { TDA10048_CLK_16000, TDA10048_IF_3800 }, 202 { TDA10048_CLK_16000, TDA10048_IF_4000 }, 203 { TDA10048_CLK_16000, TDA10048_IF_4300 }, 204 { TDA10048_CLK_16000, TDA10048_IF_4500 }, 205 { TDA10048_CLK_16000, TDA10048_IF_5000 }, 206 { TDA10048_CLK_16000, TDA10048_IF_36130 }, 207}; 208 209static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) 210{ 211 struct tda10048_config *config = &state->config; 212 int ret; 213 u8 buf[] = { reg, data }; 214 struct i2c_msg msg = { 215 .addr = config->demod_address, 216 .flags = 0, .buf = buf, .len = 2 }; 217 218 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data); 219 220 ret = i2c_transfer(state->i2c, &msg, 1); 221 222 if (ret != 1) 223 printk("%s: writereg error (ret == %i)\n", __func__, ret); 224 225 return (ret != 1) ? -1 : 0; 226} 227 228static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) 229{ 230 struct tda10048_config *config = &state->config; 231 int ret; 232 u8 b0[] = { reg }; 233 u8 b1[] = { 0 }; 234 struct i2c_msg msg[] = { 235 { .addr = config->demod_address, 236 .flags = 0, .buf = b0, .len = 1 }, 237 { .addr = config->demod_address, 238 .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 239 240 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg); 241 242 ret = i2c_transfer(state->i2c, msg, 2); 243 244 if (ret != 2) 245 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 246 __func__, ret); 247 248 return b1[0]; 249} 250 251static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, 252 const u8 *data, u16 len) 253{ 254 struct tda10048_config *config = &state->config; 255 int ret = -EREMOTEIO; 256 struct i2c_msg msg; 257 u8 *buf; 258 259 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len); 260 261 buf = kmalloc(len + 1, GFP_KERNEL); 262 if (buf == NULL) { 263 ret = -ENOMEM; 264 goto error; 265 } 266 267 *buf = reg; 268 memcpy(buf + 1, data, len); 269 270 msg.addr = config->demod_address; 271 msg.flags = 0; 272 msg.buf = buf; 273 msg.len = len + 1; 274 275 dprintk(2, "%s(): write len = %d\n", 276 __func__, msg.len); 277 278 ret = i2c_transfer(state->i2c, &msg, 1); 279 if (ret != 1) { 280 printk(KERN_ERR "%s(): writereg error err %i\n", 281 __func__, ret); 282 ret = -EREMOTEIO; 283 } 284 285error: 286 kfree(buf); 287 288 return ret; 289} 290 291static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz, 292 u32 if_hz) 293{ 294 struct tda10048_state *state = fe->demodulator_priv; 295 u64 t; 296 297 dprintk(1, "%s()\n", __func__); 298 299 if (sample_freq_hz == 0) 300 return -EINVAL; 301 302 if (if_hz < (sample_freq_hz / 2)) { 303 /* PHY2 = (if2/fs) * 2^15 */ 304 t = if_hz; 305 t *= 10; 306 t *= 32768; 307 do_div(t, sample_freq_hz); 308 t += 5; 309 do_div(t, 10); 310 } else { 311 /* PHY2 = ((IF1-fs)/fs) * 2^15 */ 312 t = sample_freq_hz - if_hz; 313 t *= 10; 314 t *= 32768; 315 do_div(t, sample_freq_hz); 316 t += 5; 317 do_div(t, 10); 318 t = ~t + 1; 319 } 320 321 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t); 322 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8)); 323 324 return 0; 325} 326 327static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz, 328 u32 bw) 329{ 330 struct tda10048_state *state = fe->demodulator_priv; 331 u64 t, z; 332 333 dprintk(1, "%s()\n", __func__); 334 335 if (sample_freq_hz == 0) 336 return -EINVAL; 337 338 /* WREF = (B / (7 * fs)) * 2^31 */ 339 t = bw * 10; 340 /* avoid warning: this decimal constant is unsigned only in ISO C90 */ 341 /* t *= 2147483648 on 32bit platforms */ 342 t *= (2048 * 1024); 343 t *= 1024; 344 z = 7 * sample_freq_hz; 345 do_div(t, z); 346 t += 5; 347 do_div(t, 10); 348 349 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t); 350 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8)); 351 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16)); 352 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24)); 353 354 return 0; 355} 356 357static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz, 358 u32 bw) 359{ 360 struct tda10048_state *state = fe->demodulator_priv; 361 u64 t; 362 363 dprintk(1, "%s()\n", __func__); 364 365 if (sample_freq_hz == 0) 366 return -EINVAL; 367 368 /* INVWREF = ((7 * fs) / B) * 2^5 */ 369 t = sample_freq_hz; 370 t *= 7; 371 t *= 32; 372 t *= 10; 373 do_div(t, bw); 374 t += 5; 375 do_div(t, 10); 376 377 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t); 378 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8)); 379 380 return 0; 381} 382 383static int tda10048_set_bandwidth(struct dvb_frontend *fe, 384 u32 bw) 385{ 386 struct tda10048_state *state = fe->demodulator_priv; 387 dprintk(1, "%s(bw=%d)\n", __func__, bw); 388 389 /* Bandwidth setting may need to be adjusted */ 390 switch (bw) { 391 case 6000000: 392 case 7000000: 393 case 8000000: 394 tda10048_set_wref(fe, state->sample_freq, bw); 395 tda10048_set_invwref(fe, state->sample_freq, bw); 396 break; 397 default: 398 printk(KERN_ERR "%s() invalid bandwidth\n", __func__); 399 return -EINVAL; 400 } 401 402 state->bandwidth = bw; 403 404 return 0; 405} 406 407static int tda10048_set_if(struct dvb_frontend *fe, u32 bw) 408{ 409 struct tda10048_state *state = fe->demodulator_priv; 410 struct tda10048_config *config = &state->config; 411 int i; 412 u32 if_freq_khz; 413 414 dprintk(1, "%s(bw = %d)\n", __func__, bw); 415 416 /* based on target bandwidth and clk we calculate pll factors */ 417 switch (bw) { 418 case 6000000: 419 if_freq_khz = config->dtv6_if_freq_khz; 420 break; 421 case 7000000: 422 if_freq_khz = config->dtv7_if_freq_khz; 423 break; 424 case 8000000: 425 if_freq_khz = config->dtv8_if_freq_khz; 426 break; 427 default: 428 printk(KERN_ERR "%s() no default\n", __func__); 429 return -EINVAL; 430 } 431 432 for (i = 0; i < ARRAY_SIZE(pll_tab); i++) { 433 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) && 434 (pll_tab[i].if_freq_khz == if_freq_khz)) { 435 436 state->freq_if_hz = pll_tab[i].if_freq_khz * 1000; 437 state->xtal_hz = pll_tab[i].clk_freq_khz * 1000; 438 break; 439 } 440 } 441 if (i == ARRAY_SIZE(pll_tab)) { 442 printk(KERN_ERR "%s() Incorrect attach settings\n", 443 __func__); 444 return -EINVAL; 445 } 446 447 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz); 448 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz); 449 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor); 450 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor); 451 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor); 452 453 /* Calculate the sample frequency */ 454 state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45); 455 state->sample_freq /= (state->pll_nfactor + 1); 456 state->sample_freq /= (state->pll_pfactor + 4); 457 dprintk(1, "- sample_freq = %d\n", state->sample_freq); 458 459 /* Update the I/F */ 460 tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz); 461 462 return 0; 463} 464 465static int tda10048_firmware_upload(struct dvb_frontend *fe) 466{ 467 struct tda10048_state *state = fe->demodulator_priv; 468 struct tda10048_config *config = &state->config; 469 const struct firmware *fw; 470 int ret; 471 int pos = 0; 472 int cnt; 473 u8 wlen = config->fwbulkwritelen; 474 475 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50)) 476 wlen = TDA10048_BULKWRITE_200; 477 478 /* request the firmware, this will block and timeout */ 479 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n", 480 __func__, 481 TDA10048_DEFAULT_FIRMWARE); 482 483 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE, 484 state->i2c->dev.parent); 485 if (ret) { 486 printk(KERN_ERR "%s: Upload failed. (file not found?)\n", 487 __func__); 488 return -EIO; 489 } else { 490 printk(KERN_INFO "%s: firmware read %zu bytes.\n", 491 __func__, 492 fw->size); 493 ret = 0; 494 } 495 496 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) { 497 printk(KERN_ERR "%s: firmware incorrect size\n", __func__); 498 ret = -EIO; 499 } else { 500 printk(KERN_INFO "%s: firmware uploading\n", __func__); 501 502 /* Soft reset */ 503 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 504 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 505 & 0xfe); 506 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 507 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 508 | 0x01); 509 510 /* Put the demod into host download mode */ 511 tda10048_writereg(state, TDA10048_CONF_C4_1, 512 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9); 513 514 /* Boot the DSP */ 515 tda10048_writereg(state, TDA10048_CONF_C4_1, 516 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08); 517 518 /* Prepare for download */ 519 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0); 520 521 /* Download the firmware payload */ 522 while (pos < fw->size) { 523 524 if ((fw->size - pos) > wlen) 525 cnt = wlen; 526 else 527 cnt = fw->size - pos; 528 529 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN, 530 &fw->data[pos], cnt); 531 532 pos += cnt; 533 } 534 535 ret = -EIO; 536 /* Wait up to 250ms for the DSP to boot */ 537 for (cnt = 0; cnt < 250 ; cnt += 10) { 538 539 msleep(10); 540 541 if (tda10048_readreg(state, TDA10048_SYNC_STATUS) 542 & 0x40) { 543 ret = 0; 544 break; 545 } 546 } 547 } 548 549 release_firmware(fw); 550 551 if (ret == 0) { 552 printk(KERN_INFO "%s: firmware uploaded\n", __func__); 553 state->fwloaded = 1; 554 } else 555 printk(KERN_ERR "%s: firmware upload failed\n", __func__); 556 557 return ret; 558} 559 560static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion) 561{ 562 struct tda10048_state *state = fe->demodulator_priv; 563 564 dprintk(1, "%s(%d)\n", __func__, inversion); 565 566 if (inversion == TDA10048_INVERSION_ON) 567 tda10048_writereg(state, TDA10048_CONF_C1_1, 568 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20); 569 else 570 tda10048_writereg(state, TDA10048_CONF_C1_1, 571 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf); 572 573 return 0; 574} 575 576/* Retrieve the demod settings */ 577static int tda10048_get_tps(struct tda10048_state *state, 578 struct dtv_frontend_properties *p) 579{ 580 u8 val; 581 582 /* Make sure the TPS regs are valid */ 583 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01)) 584 return -EAGAIN; 585 586 val = tda10048_readreg(state, TDA10048_OUT_CONF2); 587 switch ((val & 0x60) >> 5) { 588 case 0: 589 p->modulation = QPSK; 590 break; 591 case 1: 592 p->modulation = QAM_16; 593 break; 594 case 2: 595 p->modulation = QAM_64; 596 break; 597 } 598 switch ((val & 0x18) >> 3) { 599 case 0: 600 p->hierarchy = HIERARCHY_NONE; 601 break; 602 case 1: 603 p->hierarchy = HIERARCHY_1; 604 break; 605 case 2: 606 p->hierarchy = HIERARCHY_2; 607 break; 608 case 3: 609 p->hierarchy = HIERARCHY_4; 610 break; 611 } 612 switch (val & 0x07) { 613 case 0: 614 p->code_rate_HP = FEC_1_2; 615 break; 616 case 1: 617 p->code_rate_HP = FEC_2_3; 618 break; 619 case 2: 620 p->code_rate_HP = FEC_3_4; 621 break; 622 case 3: 623 p->code_rate_HP = FEC_5_6; 624 break; 625 case 4: 626 p->code_rate_HP = FEC_7_8; 627 break; 628 } 629 630 val = tda10048_readreg(state, TDA10048_OUT_CONF3); 631 switch (val & 0x07) { 632 case 0: 633 p->code_rate_LP = FEC_1_2; 634 break; 635 case 1: 636 p->code_rate_LP = FEC_2_3; 637 break; 638 case 2: 639 p->code_rate_LP = FEC_3_4; 640 break; 641 case 3: 642 p->code_rate_LP = FEC_5_6; 643 break; 644 case 4: 645 p->code_rate_LP = FEC_7_8; 646 break; 647 } 648 649 val = tda10048_readreg(state, TDA10048_OUT_CONF1); 650 switch ((val & 0x0c) >> 2) { 651 case 0: 652 p->guard_interval = GUARD_INTERVAL_1_32; 653 break; 654 case 1: 655 p->guard_interval = GUARD_INTERVAL_1_16; 656 break; 657 case 2: 658 p->guard_interval = GUARD_INTERVAL_1_8; 659 break; 660 case 3: 661 p->guard_interval = GUARD_INTERVAL_1_4; 662 break; 663 } 664 switch (val & 0x03) { 665 case 0: 666 p->transmission_mode = TRANSMISSION_MODE_2K; 667 break; 668 case 1: 669 p->transmission_mode = TRANSMISSION_MODE_8K; 670 break; 671 } 672 673 return 0; 674} 675 676static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 677{ 678 struct tda10048_state *state = fe->demodulator_priv; 679 struct tda10048_config *config = &state->config; 680 dprintk(1, "%s(%d)\n", __func__, enable); 681 682 if (config->disable_gate_access) 683 return 0; 684 685 if (enable) 686 return tda10048_writereg(state, TDA10048_CONF_C4_1, 687 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02); 688 else 689 return tda10048_writereg(state, TDA10048_CONF_C4_1, 690 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd); 691} 692 693static int tda10048_output_mode(struct dvb_frontend *fe, int serial) 694{ 695 struct tda10048_state *state = fe->demodulator_priv; 696 dprintk(1, "%s(%d)\n", __func__, serial); 697 698 /* Ensure pins are out of tri-state */ 699 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21); 700 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00); 701 702 if (serial) { 703 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20); 704 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0); 705 } else { 706 tda10048_writereg(state, TDA10048_IC_MODE, 0x00); 707 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01); 708 } 709 710 return 0; 711} 712 713/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 714/* TODO: Support manual tuning with specific params */ 715static int tda10048_set_frontend(struct dvb_frontend *fe) 716{ 717 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 718 struct tda10048_state *state = fe->demodulator_priv; 719 720 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency); 721 722 /* Update the I/F pll's if the bandwidth changes */ 723 if (p->bandwidth_hz != state->bandwidth) { 724 tda10048_set_if(fe, p->bandwidth_hz); 725 tda10048_set_bandwidth(fe, p->bandwidth_hz); 726 } 727 728 if (fe->ops.tuner_ops.set_params) { 729 730 if (fe->ops.i2c_gate_ctrl) 731 fe->ops.i2c_gate_ctrl(fe, 1); 732 733 fe->ops.tuner_ops.set_params(fe); 734 735 if (fe->ops.i2c_gate_ctrl) 736 fe->ops.i2c_gate_ctrl(fe, 0); 737 } 738 739 /* Enable demod TPS auto detection and begin acquisition */ 740 tda10048_writereg(state, TDA10048_AUTO, 0x57); 741 /* trigger cber and vber acquisition */ 742 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B); 743 744 return 0; 745} 746 747/* Establish sane defaults and load firmware. */ 748static int tda10048_init(struct dvb_frontend *fe) 749{ 750 struct tda10048_state *state = fe->demodulator_priv; 751 struct tda10048_config *config = &state->config; 752 int ret = 0, i; 753 754 dprintk(1, "%s()\n", __func__); 755 756 /* PLL */ 757 init_tab[4].data = (u8)(state->pll_mfactor); 758 init_tab[5].data = (u8)(state->pll_nfactor) | 0x40; 759 760 /* Apply register defaults */ 761 for (i = 0; i < ARRAY_SIZE(init_tab); i++) 762 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); 763 764 if (state->fwloaded == 0) 765 ret = tda10048_firmware_upload(fe); 766 767 /* Set either serial or parallel */ 768 tda10048_output_mode(fe, config->output_mode); 769 770 /* Set inversion */ 771 tda10048_set_inversion(fe, config->inversion); 772 773 /* Establish default RF values */ 774 tda10048_set_if(fe, 8000000); 775 tda10048_set_bandwidth(fe, 8000000); 776 777 /* Ensure we leave the gate closed */ 778 tda10048_i2c_gate_ctrl(fe, 0); 779 780 return ret; 781} 782 783static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status) 784{ 785 struct tda10048_state *state = fe->demodulator_priv; 786 u8 reg; 787 788 *status = 0; 789 790 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); 791 792 dprintk(1, "%s() status =0x%02x\n", __func__, reg); 793 794 if (reg & 0x02) 795 *status |= FE_HAS_CARRIER; 796 797 if (reg & 0x04) 798 *status |= FE_HAS_SIGNAL; 799 800 if (reg & 0x08) { 801 *status |= FE_HAS_LOCK; 802 *status |= FE_HAS_VITERBI; 803 *status |= FE_HAS_SYNC; 804 } 805 806 return 0; 807} 808 809static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber) 810{ 811 struct tda10048_state *state = fe->demodulator_priv; 812 static u32 cber_current; 813 u32 cber_nmax; 814 u64 cber_tmp; 815 816 dprintk(1, "%s()\n", __func__); 817 818 /* update cber on interrupt */ 819 if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) { 820 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 | 821 tda10048_readreg(state, TDA10048_CBER_LSB); 822 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 | 823 tda10048_readreg(state, TDA10048_CBER_NMAX_LSB); 824 cber_tmp *= 100000000; 825 cber_tmp *= 2; 826 cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1); 827 cber_current = (u32)cber_tmp; 828 /* retrigger cber acquisition */ 829 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39); 830 } 831 /* actual cber is (*ber)/1e8 */ 832 *ber = cber_current; 833 834 return 0; 835} 836 837static int tda10048_read_signal_strength(struct dvb_frontend *fe, 838 u16 *signal_strength) 839{ 840 struct tda10048_state *state = fe->demodulator_priv; 841 u8 v; 842 843 dprintk(1, "%s()\n", __func__); 844 845 *signal_strength = 65535; 846 847 v = tda10048_readreg(state, TDA10048_NP_OUT); 848 if (v > 0) 849 *signal_strength -= (v << 8) | v; 850 851 return 0; 852} 853 854/* SNR lookup table */ 855static struct snr_tab { 856 u8 val; 857 u8 data; 858} snr_tab[] = { 859 { 0, 0 }, 860 { 1, 246 }, 861 { 2, 215 }, 862 { 3, 198 }, 863 { 4, 185 }, 864 { 5, 176 }, 865 { 6, 168 }, 866 { 7, 161 }, 867 { 8, 155 }, 868 { 9, 150 }, 869 { 10, 146 }, 870 { 11, 141 }, 871 { 12, 138 }, 872 { 13, 134 }, 873 { 14, 131 }, 874 { 15, 128 }, 875 { 16, 125 }, 876 { 17, 122 }, 877 { 18, 120 }, 878 { 19, 118 }, 879 { 20, 115 }, 880 { 21, 113 }, 881 { 22, 111 }, 882 { 23, 109 }, 883 { 24, 107 }, 884 { 25, 106 }, 885 { 26, 104 }, 886 { 27, 102 }, 887 { 28, 101 }, 888 { 29, 99 }, 889 { 30, 98 }, 890 { 31, 96 }, 891 { 32, 95 }, 892 { 33, 94 }, 893 { 34, 92 }, 894 { 35, 91 }, 895 { 36, 90 }, 896 { 37, 89 }, 897 { 38, 88 }, 898 { 39, 86 }, 899 { 40, 85 }, 900 { 41, 84 }, 901 { 42, 83 }, 902 { 43, 82 }, 903 { 44, 81 }, 904 { 45, 80 }, 905 { 46, 79 }, 906 { 47, 78 }, 907 { 48, 77 }, 908 { 49, 76 }, 909 { 50, 76 }, 910 { 51, 75 }, 911 { 52, 74 }, 912 { 53, 73 }, 913 { 54, 72 }, 914 { 56, 71 }, 915 { 57, 70 }, 916 { 58, 69 }, 917 { 60, 68 }, 918 { 61, 67 }, 919 { 63, 66 }, 920 { 64, 65 }, 921 { 66, 64 }, 922 { 67, 63 }, 923 { 68, 62 }, 924 { 69, 62 }, 925 { 70, 61 }, 926 { 72, 60 }, 927 { 74, 59 }, 928 { 75, 58 }, 929 { 77, 57 }, 930 { 79, 56 }, 931 { 81, 55 }, 932 { 83, 54 }, 933 { 85, 53 }, 934 { 87, 52 }, 935 { 89, 51 }, 936 { 91, 50 }, 937 { 93, 49 }, 938 { 95, 48 }, 939 { 97, 47 }, 940 { 100, 46 }, 941 { 102, 45 }, 942 { 104, 44 }, 943 { 107, 43 }, 944 { 109, 42 }, 945 { 112, 41 }, 946 { 114, 40 }, 947 { 117, 39 }, 948 { 120, 38 }, 949 { 123, 37 }, 950 { 125, 36 }, 951 { 128, 35 }, 952 { 131, 34 }, 953 { 134, 33 }, 954 { 138, 32 }, 955 { 141, 31 }, 956 { 144, 30 }, 957 { 147, 29 }, 958 { 151, 28 }, 959 { 154, 27 }, 960 { 158, 26 }, 961 { 162, 25 }, 962 { 165, 24 }, 963 { 169, 23 }, 964 { 173, 22 }, 965 { 177, 21 }, 966 { 181, 20 }, 967 { 186, 19 }, 968 { 190, 18 }, 969 { 194, 17 }, 970 { 199, 16 }, 971 { 204, 15 }, 972 { 208, 14 }, 973 { 213, 13 }, 974 { 218, 12 }, 975 { 223, 11 }, 976 { 229, 10 }, 977 { 234, 9 }, 978 { 239, 8 }, 979 { 245, 7 }, 980 { 251, 6 }, 981 { 255, 5 }, 982}; 983 984static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr) 985{ 986 struct tda10048_state *state = fe->demodulator_priv; 987 u8 v; 988 int i, ret = -EINVAL; 989 990 dprintk(1, "%s()\n", __func__); 991 992 v = tda10048_readreg(state, TDA10048_NP_OUT); 993 for (i = 0; i < ARRAY_SIZE(snr_tab); i++) { 994 if (v <= snr_tab[i].val) { 995 *snr = snr_tab[i].data; 996 ret = 0; 997 break; 998 } 999 } 1000 1001 return ret; 1002} 1003 1004static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1005{ 1006 struct tda10048_state *state = fe->demodulator_priv; 1007 1008 dprintk(1, "%s()\n", __func__); 1009 1010 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | 1011 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); 1012 /* clear the uncorrected TS packets counter when saturated */ 1013 if (*ucblocks == 0xFFFF) 1014 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); 1015 1016 return 0; 1017} 1018 1019static int tda10048_get_frontend(struct dvb_frontend *fe, 1020 struct dtv_frontend_properties *p) 1021{ 1022 struct tda10048_state *state = fe->demodulator_priv; 1023 1024 dprintk(1, "%s()\n", __func__); 1025 1026 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) 1027 & 0x20 ? INVERSION_ON : INVERSION_OFF; 1028 1029 return tda10048_get_tps(state, p); 1030} 1031 1032static int tda10048_get_tune_settings(struct dvb_frontend *fe, 1033 struct dvb_frontend_tune_settings *tune) 1034{ 1035 tune->min_delay_ms = 1000; 1036 return 0; 1037} 1038 1039static void tda10048_release(struct dvb_frontend *fe) 1040{ 1041 struct tda10048_state *state = fe->demodulator_priv; 1042 dprintk(1, "%s()\n", __func__); 1043 kfree(state); 1044} 1045 1046static void tda10048_establish_defaults(struct dvb_frontend *fe) 1047{ 1048 struct tda10048_state *state = fe->demodulator_priv; 1049 struct tda10048_config *config = &state->config; 1050 1051 /* Validate/default the config */ 1052 if (config->dtv6_if_freq_khz == 0) { 1053 config->dtv6_if_freq_khz = TDA10048_IF_4300; 1054 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n", 1055 __func__, 1056 config->dtv6_if_freq_khz); 1057 } 1058 1059 if (config->dtv7_if_freq_khz == 0) { 1060 config->dtv7_if_freq_khz = TDA10048_IF_4300; 1061 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n", 1062 __func__, 1063 config->dtv7_if_freq_khz); 1064 } 1065 1066 if (config->dtv8_if_freq_khz == 0) { 1067 config->dtv8_if_freq_khz = TDA10048_IF_4300; 1068 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n", 1069 __func__, 1070 config->dtv8_if_freq_khz); 1071 } 1072 1073 if (config->clk_freq_khz == 0) { 1074 config->clk_freq_khz = TDA10048_CLK_16000; 1075 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n", 1076 __func__, 1077 config->clk_freq_khz); 1078 } 1079} 1080 1081static const struct dvb_frontend_ops tda10048_ops; 1082 1083struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, 1084 struct i2c_adapter *i2c) 1085{ 1086 struct tda10048_state *state = NULL; 1087 1088 dprintk(1, "%s()\n", __func__); 1089 1090 /* allocate memory for the internal state */ 1091 state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL); 1092 if (state == NULL) 1093 goto error; 1094 1095 /* setup the state and clone the config */ 1096 memcpy(&state->config, config, sizeof(*config)); 1097 state->i2c = i2c; 1098 state->fwloaded = config->no_firmware; 1099 state->bandwidth = 8000000; 1100 1101 /* check if the demod is present */ 1102 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) 1103 goto error; 1104 1105 /* create dvb_frontend */ 1106 memcpy(&state->frontend.ops, &tda10048_ops, 1107 sizeof(struct dvb_frontend_ops)); 1108 state->frontend.demodulator_priv = state; 1109 1110 /* set pll */ 1111 if (config->set_pll) { 1112 state->pll_mfactor = config->pll_m; 1113 state->pll_nfactor = config->pll_n; 1114 state->pll_pfactor = config->pll_p; 1115 } else { 1116 state->pll_mfactor = 10; 1117 state->pll_nfactor = 3; 1118 state->pll_pfactor = 0; 1119 } 1120 1121 /* Establish any defaults the the user didn't pass */ 1122 tda10048_establish_defaults(&state->frontend); 1123 1124 /* Set the xtal and freq defaults */ 1125 if (tda10048_set_if(&state->frontend, 8000000) != 0) 1126 goto error; 1127 1128 /* Default bandwidth */ 1129 if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0) 1130 goto error; 1131 1132 /* Leave the gate closed */ 1133 tda10048_i2c_gate_ctrl(&state->frontend, 0); 1134 1135 return &state->frontend; 1136 1137error: 1138 kfree(state); 1139 return NULL; 1140} 1141EXPORT_SYMBOL_GPL(tda10048_attach); 1142 1143static const struct dvb_frontend_ops tda10048_ops = { 1144 .delsys = { SYS_DVBT }, 1145 .info = { 1146 .name = "NXP TDA10048HN DVB-T", 1147 .frequency_min_hz = 177 * MHz, 1148 .frequency_max_hz = 858 * MHz, 1149 .frequency_stepsize_hz = 166666, 1150 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1151 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1152 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1153 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 1154 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER 1155 }, 1156 1157 .release = tda10048_release, 1158 .init = tda10048_init, 1159 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl, 1160 .set_frontend = tda10048_set_frontend, 1161 .get_frontend = tda10048_get_frontend, 1162 .get_tune_settings = tda10048_get_tune_settings, 1163 .read_status = tda10048_read_status, 1164 .read_ber = tda10048_read_ber, 1165 .read_signal_strength = tda10048_read_signal_strength, 1166 .read_snr = tda10048_read_snr, 1167 .read_ucblocks = tda10048_read_ucblocks, 1168}; 1169 1170module_param(debug, int, 0644); 1171MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 1172 1173MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver"); 1174MODULE_AUTHOR("Steven Toth"); 1175MODULE_LICENSE("GPL"); 1176