1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/delay.h> 7#include <linux/interrupt.h> 8#include <linux/io.h> 9#include <linux/mailbox_controller.h> 10#include <linux/of.h> 11#include <linux/of_device.h> 12#include <linux/platform_device.h> 13#include <linux/pm.h> 14#include <linux/slab.h> 15 16#include <soc/tegra/fuse.h> 17 18#include <dt-bindings/mailbox/tegra186-hsp.h> 19 20#include "mailbox.h" 21 22#define HSP_INT_IE(x) (0x100 + ((x) * 4)) 23#define HSP_INT_IV 0x300 24#define HSP_INT_IR 0x304 25 26#define HSP_INT_EMPTY_SHIFT 0 27#define HSP_INT_EMPTY_MASK 0xff 28#define HSP_INT_FULL_SHIFT 8 29#define HSP_INT_FULL_MASK 0xff 30 31#define HSP_INT_DIMENSIONING 0x380 32#define HSP_nSM_SHIFT 0 33#define HSP_nSS_SHIFT 4 34#define HSP_nAS_SHIFT 8 35#define HSP_nDB_SHIFT 12 36#define HSP_nSI_SHIFT 16 37#define HSP_nINT_MASK 0xf 38 39#define HSP_DB_TRIGGER 0x0 40#define HSP_DB_ENABLE 0x4 41#define HSP_DB_RAW 0x8 42#define HSP_DB_PENDING 0xc 43 44#define HSP_SM_SHRD_MBOX 0x0 45#define HSP_SM_SHRD_MBOX_FULL BIT(31) 46#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 47#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 48 49#define HSP_DB_CCPLEX 1 50#define HSP_DB_BPMP 3 51#define HSP_DB_MAX 7 52 53struct tegra_hsp_channel; 54struct tegra_hsp; 55 56struct tegra_hsp_channel { 57 struct tegra_hsp *hsp; 58 struct mbox_chan *chan; 59 void __iomem *regs; 60}; 61 62struct tegra_hsp_doorbell { 63 struct tegra_hsp_channel channel; 64 struct list_head list; 65 const char *name; 66 unsigned int master; 67 unsigned int index; 68}; 69 70struct tegra_hsp_mailbox { 71 struct tegra_hsp_channel channel; 72 unsigned int index; 73 bool producer; 74}; 75 76struct tegra_hsp_db_map { 77 const char *name; 78 unsigned int master; 79 unsigned int index; 80}; 81 82struct tegra_hsp_soc { 83 const struct tegra_hsp_db_map *map; 84 bool has_per_mb_ie; 85}; 86 87struct tegra_hsp { 88 struct device *dev; 89 const struct tegra_hsp_soc *soc; 90 struct mbox_controller mbox_db; 91 struct mbox_controller mbox_sm; 92 void __iomem *regs; 93 unsigned int doorbell_irq; 94 unsigned int *shared_irqs; 95 unsigned int shared_irq; 96 unsigned int num_sm; 97 unsigned int num_as; 98 unsigned int num_ss; 99 unsigned int num_db; 100 unsigned int num_si; 101 spinlock_t lock; 102 103 struct list_head doorbells; 104 struct tegra_hsp_mailbox *mailboxes; 105 106 unsigned long mask; 107}; 108 109static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) 110{ 111 return readl(hsp->regs + offset); 112} 113 114static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value, 115 unsigned int offset) 116{ 117 writel(value, hsp->regs + offset); 118} 119 120static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel, 121 unsigned int offset) 122{ 123 return readl(channel->regs + offset); 124} 125 126static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel, 127 u32 value, unsigned int offset) 128{ 129 writel(value, channel->regs + offset); 130} 131 132static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db) 133{ 134 u32 value; 135 136 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE); 137 138 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0; 139} 140 141static struct tegra_hsp_doorbell * 142__tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) 143{ 144 struct tegra_hsp_doorbell *entry; 145 146 list_for_each_entry(entry, &hsp->doorbells, list) 147 if (entry->master == master) 148 return entry; 149 150 return NULL; 151} 152 153static struct tegra_hsp_doorbell * 154tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) 155{ 156 struct tegra_hsp_doorbell *db; 157 unsigned long flags; 158 159 spin_lock_irqsave(&hsp->lock, flags); 160 db = __tegra_hsp_doorbell_get(hsp, master); 161 spin_unlock_irqrestore(&hsp->lock, flags); 162 163 return db; 164} 165 166static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data) 167{ 168 struct tegra_hsp *hsp = data; 169 struct tegra_hsp_doorbell *db; 170 unsigned long master, value; 171 172 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 173 if (!db) 174 return IRQ_NONE; 175 176 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING); 177 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING); 178 179 spin_lock(&hsp->lock); 180 181 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) { 182 struct tegra_hsp_doorbell *db; 183 184 db = __tegra_hsp_doorbell_get(hsp, master); 185 /* 186 * Depending on the bootloader chain, the CCPLEX doorbell will 187 * have some doorbells enabled, which means that requesting an 188 * interrupt will immediately fire. 189 * 190 * In that case, db->channel.chan will still be NULL here and 191 * cause a crash if not properly guarded. 192 * 193 * It remains to be seen if ignoring the doorbell in that case 194 * is the correct solution. 195 */ 196 if (db && db->channel.chan) 197 mbox_chan_received_data(db->channel.chan, NULL); 198 } 199 200 spin_unlock(&hsp->lock); 201 202 return IRQ_HANDLED; 203} 204 205static irqreturn_t tegra_hsp_shared_irq(int irq, void *data) 206{ 207 struct tegra_hsp *hsp = data; 208 unsigned long bit, mask; 209 u32 status, value; 210 void *msg; 211 212 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask; 213 214 /* process EMPTY interrupts first */ 215 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; 216 217 for_each_set_bit(bit, &mask, hsp->num_sm) { 218 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; 219 220 if (mb->producer) { 221 /* 222 * Disable EMPTY interrupts until data is sent with 223 * the next message. These interrupts are level- 224 * triggered, so if we kept them enabled they would 225 * constantly trigger until we next write data into 226 * the message. 227 */ 228 spin_lock(&hsp->lock); 229 230 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 231 tegra_hsp_writel(hsp, hsp->mask, 232 HSP_INT_IE(hsp->shared_irq)); 233 234 spin_unlock(&hsp->lock); 235 236 mbox_chan_txdone(mb->channel.chan, 0); 237 } 238 } 239 240 /* process FULL interrupts */ 241 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; 242 243 for_each_set_bit(bit, &mask, hsp->num_sm) { 244 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit]; 245 246 if (!mb->producer) { 247 value = tegra_hsp_channel_readl(&mb->channel, 248 HSP_SM_SHRD_MBOX); 249 value &= ~HSP_SM_SHRD_MBOX_FULL; 250 msg = (void *)(unsigned long)value; 251 mbox_chan_received_data(mb->channel.chan, msg); 252 253 /* 254 * Need to clear all bits here since some producers, 255 * such as TCU, depend on fields in the register 256 * getting cleared by the consumer. 257 * 258 * The mailbox API doesn't give the consumers a way 259 * of doing that explicitly, so we have to make sure 260 * we cover all possible cases. 261 */ 262 tegra_hsp_channel_writel(&mb->channel, 0x0, 263 HSP_SM_SHRD_MBOX); 264 } 265 } 266 267 return IRQ_HANDLED; 268} 269 270static struct tegra_hsp_channel * 271tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, 272 unsigned int master, unsigned int index) 273{ 274 struct tegra_hsp_doorbell *db; 275 unsigned int offset; 276 unsigned long flags; 277 278 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL); 279 if (!db) 280 return ERR_PTR(-ENOMEM); 281 282 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; 283 offset += index * 0x100; 284 285 db->channel.regs = hsp->regs + offset; 286 db->channel.hsp = hsp; 287 288 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL); 289 db->master = master; 290 db->index = index; 291 292 spin_lock_irqsave(&hsp->lock, flags); 293 list_add_tail(&db->list, &hsp->doorbells); 294 spin_unlock_irqrestore(&hsp->lock, flags); 295 296 return &db->channel; 297} 298 299static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data) 300{ 301 struct tegra_hsp_doorbell *db = chan->con_priv; 302 303 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER); 304 305 return 0; 306} 307 308static int tegra_hsp_doorbell_startup(struct mbox_chan *chan) 309{ 310 struct tegra_hsp_doorbell *db = chan->con_priv; 311 struct tegra_hsp *hsp = db->channel.hsp; 312 struct tegra_hsp_doorbell *ccplex; 313 unsigned long flags; 314 u32 value; 315 316 if (db->master >= chan->mbox->num_chans) { 317 dev_err(chan->mbox->dev, 318 "invalid master ID %u for HSP channel\n", 319 db->master); 320 return -EINVAL; 321 } 322 323 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 324 if (!ccplex) 325 return -ENODEV; 326 327 /* 328 * On simulation platforms the BPMP hasn't had a chance yet to mark 329 * the doorbell as ringable by the CCPLEX, so we want to skip extra 330 * checks here. 331 */ 332 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db)) 333 return -ENODEV; 334 335 spin_lock_irqsave(&hsp->lock, flags); 336 337 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE); 338 value |= BIT(db->master); 339 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE); 340 341 spin_unlock_irqrestore(&hsp->lock, flags); 342 343 return 0; 344} 345 346static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan) 347{ 348 struct tegra_hsp_doorbell *db = chan->con_priv; 349 struct tegra_hsp *hsp = db->channel.hsp; 350 struct tegra_hsp_doorbell *ccplex; 351 unsigned long flags; 352 u32 value; 353 354 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX); 355 if (!ccplex) 356 return; 357 358 spin_lock_irqsave(&hsp->lock, flags); 359 360 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE); 361 value &= ~BIT(db->master); 362 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE); 363 364 spin_unlock_irqrestore(&hsp->lock, flags); 365} 366 367static const struct mbox_chan_ops tegra_hsp_db_ops = { 368 .send_data = tegra_hsp_doorbell_send_data, 369 .startup = tegra_hsp_doorbell_startup, 370 .shutdown = tegra_hsp_doorbell_shutdown, 371}; 372 373static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) 374{ 375 struct tegra_hsp_mailbox *mb = chan->con_priv; 376 struct tegra_hsp *hsp = mb->channel.hsp; 377 unsigned long flags; 378 u32 value; 379 380 if (WARN_ON(!mb->producer)) 381 return -EPERM; 382 383 /* copy data and mark mailbox full */ 384 value = (u32)(unsigned long)data; 385 value |= HSP_SM_SHRD_MBOX_FULL; 386 387 tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX); 388 389 /* enable EMPTY interrupt for the shared mailbox */ 390 spin_lock_irqsave(&hsp->lock, flags); 391 392 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); 393 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 394 395 spin_unlock_irqrestore(&hsp->lock, flags); 396 397 return 0; 398} 399 400static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, 401 unsigned long timeout) 402{ 403 struct tegra_hsp_mailbox *mb = chan->con_priv; 404 struct tegra_hsp_channel *ch = &mb->channel; 405 u32 value; 406 407 timeout = jiffies + msecs_to_jiffies(timeout); 408 409 while (time_before(jiffies, timeout)) { 410 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); 411 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { 412 mbox_chan_txdone(chan, 0); 413 414 /* Wait until channel is empty */ 415 if (chan->active_req != NULL) 416 continue; 417 418 return 0; 419 } 420 421 udelay(1); 422 } 423 424 return -ETIME; 425} 426 427static int tegra_hsp_mailbox_startup(struct mbox_chan *chan) 428{ 429 struct tegra_hsp_mailbox *mb = chan->con_priv; 430 struct tegra_hsp_channel *ch = &mb->channel; 431 struct tegra_hsp *hsp = mb->channel.hsp; 432 unsigned long flags; 433 434 chan->txdone_method = TXDONE_BY_IRQ; 435 436 /* 437 * Shared mailboxes start out as consumers by default. FULL and EMPTY 438 * interrupts are coalesced at the same shared interrupt. 439 * 440 * Keep EMPTY interrupts disabled at startup and only enable them when 441 * the mailbox is actually full. This is required because the FULL and 442 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts 443 * enabled all the time would cause an interrupt storm while mailboxes 444 * are idle. 445 */ 446 447 spin_lock_irqsave(&hsp->lock, flags); 448 449 if (mb->producer) 450 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 451 else 452 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index); 453 454 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 455 456 spin_unlock_irqrestore(&hsp->lock, flags); 457 458 if (hsp->soc->has_per_mb_ie) { 459 if (mb->producer) 460 tegra_hsp_channel_writel(ch, 0x0, 461 HSP_SM_SHRD_MBOX_EMPTY_INT_IE); 462 else 463 tegra_hsp_channel_writel(ch, 0x1, 464 HSP_SM_SHRD_MBOX_FULL_INT_IE); 465 } 466 467 return 0; 468} 469 470static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan) 471{ 472 struct tegra_hsp_mailbox *mb = chan->con_priv; 473 struct tegra_hsp_channel *ch = &mb->channel; 474 struct tegra_hsp *hsp = mb->channel.hsp; 475 unsigned long flags; 476 477 if (hsp->soc->has_per_mb_ie) { 478 if (mb->producer) 479 tegra_hsp_channel_writel(ch, 0x0, 480 HSP_SM_SHRD_MBOX_EMPTY_INT_IE); 481 else 482 tegra_hsp_channel_writel(ch, 0x0, 483 HSP_SM_SHRD_MBOX_FULL_INT_IE); 484 } 485 486 spin_lock_irqsave(&hsp->lock, flags); 487 488 if (mb->producer) 489 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); 490 else 491 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); 492 493 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); 494 495 spin_unlock_irqrestore(&hsp->lock, flags); 496} 497 498static const struct mbox_chan_ops tegra_hsp_sm_ops = { 499 .send_data = tegra_hsp_mailbox_send_data, 500 .flush = tegra_hsp_mailbox_flush, 501 .startup = tegra_hsp_mailbox_startup, 502 .shutdown = tegra_hsp_mailbox_shutdown, 503}; 504 505static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox, 506 const struct of_phandle_args *args) 507{ 508 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db); 509 unsigned int type = args->args[0], master = args->args[1]; 510 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV); 511 struct tegra_hsp_doorbell *db; 512 struct mbox_chan *chan; 513 unsigned long flags; 514 unsigned int i; 515 516 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq) 517 return ERR_PTR(-ENODEV); 518 519 db = tegra_hsp_doorbell_get(hsp, master); 520 if (db) 521 channel = &db->channel; 522 523 if (IS_ERR(channel)) 524 return ERR_CAST(channel); 525 526 spin_lock_irqsave(&hsp->lock, flags); 527 528 for (i = 0; i < mbox->num_chans; i++) { 529 chan = &mbox->chans[i]; 530 if (!chan->con_priv) { 531 channel->chan = chan; 532 chan->con_priv = db; 533 break; 534 } 535 536 chan = NULL; 537 } 538 539 spin_unlock_irqrestore(&hsp->lock, flags); 540 541 return chan ?: ERR_PTR(-EBUSY); 542} 543 544static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox, 545 const struct of_phandle_args *args) 546{ 547 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm); 548 unsigned int type = args->args[0], index; 549 struct tegra_hsp_mailbox *mb; 550 551 index = args->args[1] & TEGRA_HSP_SM_MASK; 552 553 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs || 554 index >= hsp->num_sm) 555 return ERR_PTR(-ENODEV); 556 557 mb = &hsp->mailboxes[index]; 558 559 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0) 560 mb->producer = false; 561 else 562 mb->producer = true; 563 564 return mb->channel.chan; 565} 566 567static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp) 568{ 569 const struct tegra_hsp_db_map *map = hsp->soc->map; 570 struct tegra_hsp_channel *channel; 571 572 while (map->name) { 573 channel = tegra_hsp_doorbell_create(hsp, map->name, 574 map->master, map->index); 575 if (IS_ERR(channel)) 576 return PTR_ERR(channel); 577 578 map++; 579 } 580 581 return 0; 582} 583 584static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev) 585{ 586 int i; 587 588 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes), 589 GFP_KERNEL); 590 if (!hsp->mailboxes) 591 return -ENOMEM; 592 593 for (i = 0; i < hsp->num_sm; i++) { 594 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; 595 596 mb->index = i; 597 598 mb->channel.hsp = hsp; 599 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K; 600 mb->channel.chan = &hsp->mbox_sm.chans[i]; 601 mb->channel.chan->con_priv = mb; 602 } 603 604 return 0; 605} 606 607static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp) 608{ 609 unsigned int i, irq = 0; 610 int err; 611 612 for (i = 0; i < hsp->num_si; i++) { 613 irq = hsp->shared_irqs[i]; 614 if (irq <= 0) 615 continue; 616 617 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0, 618 dev_name(hsp->dev), hsp); 619 if (err < 0) { 620 dev_err(hsp->dev, "failed to request interrupt: %d\n", 621 err); 622 continue; 623 } 624 625 hsp->shared_irq = i; 626 627 /* disable all interrupts */ 628 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq)); 629 630 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq); 631 632 break; 633 } 634 635 if (i == hsp->num_si) { 636 dev_err(hsp->dev, "failed to find available interrupt\n"); 637 return -ENOENT; 638 } 639 640 return 0; 641} 642 643static int tegra_hsp_probe(struct platform_device *pdev) 644{ 645 struct tegra_hsp *hsp; 646 struct resource *res; 647 unsigned int i; 648 u32 value; 649 int err; 650 651 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL); 652 if (!hsp) 653 return -ENOMEM; 654 655 hsp->dev = &pdev->dev; 656 hsp->soc = of_device_get_match_data(&pdev->dev); 657 INIT_LIST_HEAD(&hsp->doorbells); 658 spin_lock_init(&hsp->lock); 659 660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 661 hsp->regs = devm_ioremap_resource(&pdev->dev, res); 662 if (IS_ERR(hsp->regs)) 663 return PTR_ERR(hsp->regs); 664 665 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING); 666 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK; 667 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK; 668 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK; 669 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK; 670 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK; 671 672 err = platform_get_irq_byname_optional(pdev, "doorbell"); 673 if (err >= 0) 674 hsp->doorbell_irq = err; 675 676 if (hsp->num_si > 0) { 677 unsigned int count = 0; 678 679 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si, 680 sizeof(*hsp->shared_irqs), 681 GFP_KERNEL); 682 if (!hsp->shared_irqs) 683 return -ENOMEM; 684 685 for (i = 0; i < hsp->num_si; i++) { 686 char *name; 687 688 name = kasprintf(GFP_KERNEL, "shared%u", i); 689 if (!name) 690 return -ENOMEM; 691 692 err = platform_get_irq_byname_optional(pdev, name); 693 if (err >= 0) { 694 hsp->shared_irqs[i] = err; 695 count++; 696 } 697 698 kfree(name); 699 } 700 701 if (count == 0) { 702 devm_kfree(&pdev->dev, hsp->shared_irqs); 703 hsp->shared_irqs = NULL; 704 } 705 } 706 707 /* setup the doorbell controller */ 708 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate; 709 hsp->mbox_db.num_chans = 32; 710 hsp->mbox_db.dev = &pdev->dev; 711 hsp->mbox_db.ops = &tegra_hsp_db_ops; 712 713 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans, 714 sizeof(*hsp->mbox_db.chans), 715 GFP_KERNEL); 716 if (!hsp->mbox_db.chans) 717 return -ENOMEM; 718 719 if (hsp->doorbell_irq) { 720 err = tegra_hsp_add_doorbells(hsp); 721 if (err < 0) { 722 dev_err(&pdev->dev, "failed to add doorbells: %d\n", 723 err); 724 return err; 725 } 726 } 727 728 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db); 729 if (err < 0) { 730 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n", 731 err); 732 return err; 733 } 734 735 /* setup the shared mailbox controller */ 736 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate; 737 hsp->mbox_sm.num_chans = hsp->num_sm; 738 hsp->mbox_sm.dev = &pdev->dev; 739 hsp->mbox_sm.ops = &tegra_hsp_sm_ops; 740 741 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans, 742 sizeof(*hsp->mbox_sm.chans), 743 GFP_KERNEL); 744 if (!hsp->mbox_sm.chans) 745 return -ENOMEM; 746 747 if (hsp->shared_irqs) { 748 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev); 749 if (err < 0) { 750 dev_err(&pdev->dev, "failed to add mailboxes: %d\n", 751 err); 752 return err; 753 } 754 } 755 756 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm); 757 if (err < 0) { 758 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n", 759 err); 760 return err; 761 } 762 763 platform_set_drvdata(pdev, hsp); 764 765 if (hsp->doorbell_irq) { 766 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq, 767 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND, 768 dev_name(&pdev->dev), hsp); 769 if (err < 0) { 770 dev_err(&pdev->dev, 771 "failed to request doorbell IRQ#%u: %d\n", 772 hsp->doorbell_irq, err); 773 return err; 774 } 775 } 776 777 if (hsp->shared_irqs) { 778 err = tegra_hsp_request_shared_irq(hsp); 779 if (err < 0) 780 return err; 781 } 782 783 return 0; 784} 785 786static int __maybe_unused tegra_hsp_resume(struct device *dev) 787{ 788 struct tegra_hsp *hsp = dev_get_drvdata(dev); 789 unsigned int i; 790 struct tegra_hsp_doorbell *db; 791 792 list_for_each_entry(db, &hsp->doorbells, list) { 793 if (db && db->channel.chan) 794 tegra_hsp_doorbell_startup(db->channel.chan); 795 } 796 797 if (hsp->mailboxes) { 798 for (i = 0; i < hsp->num_sm; i++) { 799 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i]; 800 801 if (mb->channel.chan->cl) 802 tegra_hsp_mailbox_startup(mb->channel.chan); 803 } 804 } 805 806 return 0; 807} 808 809static const struct dev_pm_ops tegra_hsp_pm_ops = { 810 .resume_noirq = tegra_hsp_resume, 811}; 812 813static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { 814 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, }, 815 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, }, 816 { /* sentinel */ } 817}; 818 819static const struct tegra_hsp_soc tegra186_hsp_soc = { 820 .map = tegra186_hsp_db_map, 821 .has_per_mb_ie = false, 822}; 823 824static const struct tegra_hsp_soc tegra194_hsp_soc = { 825 .map = tegra186_hsp_db_map, 826 .has_per_mb_ie = true, 827}; 828 829static const struct of_device_id tegra_hsp_match[] = { 830 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc }, 831 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc }, 832 { } 833}; 834 835static struct platform_driver tegra_hsp_driver = { 836 .driver = { 837 .name = "tegra-hsp", 838 .of_match_table = tegra_hsp_match, 839 .pm = &tegra_hsp_pm_ops, 840 }, 841 .probe = tegra_hsp_probe, 842}; 843 844static int __init tegra_hsp_init(void) 845{ 846 return platform_driver_register(&tegra_hsp_driver); 847} 848core_initcall(tegra_hsp_init); 849