1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (c) 2018 MediaTek Inc. 4 5#include <linux/bitops.h> 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/dma-mapping.h> 9#include <linux/errno.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/iopoll.h> 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/mailbox_controller.h> 17#include <linux/mailbox/mtk-cmdq-mailbox.h> 18#include <linux/of_device.h> 19 20#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) 21#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) 22 23#define CMDQ_CURR_IRQ_STATUS 0x10 24#define CMDQ_SYNC_TOKEN_UPDATE 0x68 25#define CMDQ_THR_SLOT_CYCLES 0x30 26#define CMDQ_THR_BASE 0x100 27#define CMDQ_THR_SIZE 0x80 28#define CMDQ_THR_WARM_RESET 0x00 29#define CMDQ_THR_ENABLE_TASK 0x04 30#define CMDQ_THR_SUSPEND_TASK 0x08 31#define CMDQ_THR_CURR_STATUS 0x0c 32#define CMDQ_THR_IRQ_STATUS 0x10 33#define CMDQ_THR_IRQ_ENABLE 0x14 34#define CMDQ_THR_CURR_ADDR 0x20 35#define CMDQ_THR_END_ADDR 0x24 36#define CMDQ_THR_WAIT_TOKEN 0x30 37#define CMDQ_THR_PRIORITY 0x40 38 39#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 40#define CMDQ_THR_ENABLED 0x1 41#define CMDQ_THR_DISABLED 0x0 42#define CMDQ_THR_SUSPEND 0x1 43#define CMDQ_THR_RESUME 0x0 44#define CMDQ_THR_STATUS_SUSPENDED BIT(1) 45#define CMDQ_THR_DO_WARM_RESET BIT(0) 46#define CMDQ_THR_IRQ_DONE 0x1 47#define CMDQ_THR_IRQ_ERROR 0x12 48#define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE) 49#define CMDQ_THR_IS_WAITING BIT(31) 50 51#define CMDQ_JUMP_BY_OFFSET 0x10000000 52#define CMDQ_JUMP_BY_PA 0x10000001 53 54struct cmdq_thread { 55 struct mbox_chan *chan; 56 void __iomem *base; 57 struct list_head task_busy_list; 58 u32 priority; 59}; 60 61struct cmdq_task { 62 struct cmdq *cmdq; 63 struct list_head list_entry; 64 dma_addr_t pa_base; 65 struct cmdq_thread *thread; 66 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */ 67}; 68 69struct cmdq { 70 struct mbox_controller mbox; 71 void __iomem *base; 72 int irq; 73 u32 thread_nr; 74 u32 irq_mask; 75 struct cmdq_thread *thread; 76 struct clk *clock; 77 bool suspended; 78 u8 shift_pa; 79}; 80 81struct gce_plat { 82 u32 thread_nr; 83 u8 shift; 84}; 85 86u8 cmdq_get_shift_pa(struct mbox_chan *chan) 87{ 88 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); 89 90 return cmdq->shift_pa; 91} 92EXPORT_SYMBOL(cmdq_get_shift_pa); 93 94static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) 95{ 96 u32 status; 97 98 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); 99 100 /* If already disabled, treat as suspended successful. */ 101 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 102 return 0; 103 104 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, 105 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) { 106 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", 107 (u32)(thread->base - cmdq->base)); 108 return -EFAULT; 109 } 110 111 return 0; 112} 113 114static void cmdq_thread_resume(struct cmdq_thread *thread) 115{ 116 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); 117} 118 119static void cmdq_init(struct cmdq *cmdq) 120{ 121 int i; 122 123 WARN_ON(clk_enable(cmdq->clock) < 0); 124 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); 125 for (i = 0; i <= CMDQ_MAX_EVENT; i++) 126 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); 127 clk_disable(cmdq->clock); 128} 129 130static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) 131{ 132 u32 warm_reset; 133 134 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET); 135 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET, 136 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET), 137 0, 10)) { 138 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n", 139 (u32)(thread->base - cmdq->base)); 140 return -EFAULT; 141 } 142 143 return 0; 144} 145 146static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread) 147{ 148 cmdq_thread_reset(cmdq, thread); 149 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK); 150} 151 152/* notify GCE to re-fetch commands by setting GCE thread PC */ 153static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread) 154{ 155 writel(readl(thread->base + CMDQ_THR_CURR_ADDR), 156 thread->base + CMDQ_THR_CURR_ADDR); 157} 158 159static void cmdq_task_insert_into_thread(struct cmdq_task *task) 160{ 161 struct device *dev = task->cmdq->mbox.dev; 162 struct cmdq_thread *thread = task->thread; 163 struct cmdq_task *prev_task = list_last_entry( 164 &thread->task_busy_list, typeof(*task), list_entry); 165 u64 *prev_task_base = prev_task->pkt->va_base; 166 167 /* let previous task jump to this task */ 168 dma_sync_single_for_cpu(dev, prev_task->pa_base, 169 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 170 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = 171 (u64)CMDQ_JUMP_BY_PA << 32 | 172 (task->pa_base >> task->cmdq->shift_pa); 173 dma_sync_single_for_device(dev, prev_task->pa_base, 174 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 175 176 cmdq_thread_invalidate_fetched_data(thread); 177} 178 179static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) 180{ 181 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING; 182} 183 184static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta) 185{ 186 struct cmdq_task_cb *cb = &task->pkt->async_cb; 187 struct cmdq_cb_data data; 188 189 WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL); 190 data.sta = sta; 191 data.data = cb->data; 192 cb->cb(data); 193 194 list_del(&task->list_entry); 195} 196 197static void cmdq_task_handle_error(struct cmdq_task *task) 198{ 199 struct cmdq_thread *thread = task->thread; 200 struct cmdq_task *next_task; 201 struct cmdq *cmdq = task->cmdq; 202 203 dev_err(cmdq->mbox.dev, "task 0x%p error\n", task); 204 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 205 next_task = list_first_entry_or_null(&thread->task_busy_list, 206 struct cmdq_task, list_entry); 207 if (next_task) 208 writel(next_task->pa_base >> cmdq->shift_pa, 209 thread->base + CMDQ_THR_CURR_ADDR); 210 cmdq_thread_resume(thread); 211} 212 213static void cmdq_thread_irq_handler(struct cmdq *cmdq, 214 struct cmdq_thread *thread) 215{ 216 struct cmdq_task *task, *tmp, *curr_task = NULL; 217 u32 curr_pa, irq_flag, task_end_pa; 218 bool err; 219 220 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS); 221 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS); 222 223 /* 224 * When ISR call this function, another CPU core could run 225 * "release task" right before we acquire the spin lock, and thus 226 * reset / disable this GCE thread, so we need to check the enable 227 * bit of this GCE thread. 228 */ 229 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 230 return; 231 232 if (irq_flag & CMDQ_THR_IRQ_ERROR) 233 err = true; 234 else if (irq_flag & CMDQ_THR_IRQ_DONE) 235 err = false; 236 else 237 return; 238 239 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa; 240 241 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 242 list_entry) { 243 task_end_pa = task->pa_base + task->pkt->cmd_buf_size; 244 if (curr_pa >= task->pa_base && curr_pa < task_end_pa) 245 curr_task = task; 246 247 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) { 248 cmdq_task_exec_done(task, CMDQ_CB_NORMAL); 249 kfree(task); 250 } else if (err) { 251 cmdq_task_exec_done(task, CMDQ_CB_ERROR); 252 cmdq_task_handle_error(curr_task); 253 kfree(task); 254 } 255 256 if (curr_task) 257 break; 258 } 259 260 if (list_empty(&thread->task_busy_list)) { 261 cmdq_thread_disable(cmdq, thread); 262 clk_disable(cmdq->clock); 263 } 264} 265 266static irqreturn_t cmdq_irq_handler(int irq, void *dev) 267{ 268 struct cmdq *cmdq = dev; 269 unsigned long irq_status, flags = 0L; 270 int bit; 271 272 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; 273 if (!(irq_status ^ cmdq->irq_mask)) 274 return IRQ_NONE; 275 276 for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { 277 struct cmdq_thread *thread = &cmdq->thread[bit]; 278 279 spin_lock_irqsave(&thread->chan->lock, flags); 280 cmdq_thread_irq_handler(cmdq, thread); 281 spin_unlock_irqrestore(&thread->chan->lock, flags); 282 } 283 284 return IRQ_HANDLED; 285} 286 287static int cmdq_suspend(struct device *dev) 288{ 289 struct cmdq *cmdq = dev_get_drvdata(dev); 290 struct cmdq_thread *thread; 291 int i; 292 bool task_running = false; 293 294 cmdq->suspended = true; 295 296 for (i = 0; i < cmdq->thread_nr; i++) { 297 thread = &cmdq->thread[i]; 298 if (!list_empty(&thread->task_busy_list)) { 299 task_running = true; 300 break; 301 } 302 } 303 304 if (task_running) 305 dev_warn(dev, "exist running task(s) in suspend\n"); 306 307 clk_unprepare(cmdq->clock); 308 309 return 0; 310} 311 312static int cmdq_resume(struct device *dev) 313{ 314 struct cmdq *cmdq = dev_get_drvdata(dev); 315 316 WARN_ON(clk_prepare(cmdq->clock) < 0); 317 cmdq->suspended = false; 318 return 0; 319} 320 321static int cmdq_remove(struct platform_device *pdev) 322{ 323 struct cmdq *cmdq = platform_get_drvdata(pdev); 324 325 clk_unprepare(cmdq->clock); 326 327 return 0; 328} 329 330static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) 331{ 332 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; 333 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 334 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 335 struct cmdq_task *task; 336 unsigned long curr_pa, end_pa; 337 338 /* Client should not flush new tasks if suspended. */ 339 WARN_ON(cmdq->suspended); 340 341 task = kzalloc(sizeof(*task), GFP_ATOMIC); 342 if (!task) 343 return -ENOMEM; 344 345 task->cmdq = cmdq; 346 INIT_LIST_HEAD(&task->list_entry); 347 task->pa_base = pkt->pa_base; 348 task->thread = thread; 349 task->pkt = pkt; 350 351 if (list_empty(&thread->task_busy_list)) { 352 WARN_ON(clk_enable(cmdq->clock) < 0); 353 /* 354 * The thread reset will clear thread related register to 0, 355 * including pc, end, priority, irq, suspend and enable. Thus 356 * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable 357 * thread and make it running. 358 */ 359 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); 360 361 writel(task->pa_base >> cmdq->shift_pa, 362 thread->base + CMDQ_THR_CURR_ADDR); 363 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 364 thread->base + CMDQ_THR_END_ADDR); 365 366 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); 367 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); 368 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); 369 } else { 370 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 371 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << 372 cmdq->shift_pa; 373 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) << 374 cmdq->shift_pa; 375 /* check boundary */ 376 if (curr_pa == end_pa - CMDQ_INST_SIZE || 377 curr_pa == end_pa) { 378 /* set to this task directly */ 379 writel(task->pa_base >> cmdq->shift_pa, 380 thread->base + CMDQ_THR_CURR_ADDR); 381 } else { 382 cmdq_task_insert_into_thread(task); 383 smp_mb(); /* modify jump before enable thread */ 384 } 385 writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 386 thread->base + CMDQ_THR_END_ADDR); 387 cmdq_thread_resume(thread); 388 } 389 list_move_tail(&task->list_entry, &thread->task_busy_list); 390 391 return 0; 392} 393 394static int cmdq_mbox_startup(struct mbox_chan *chan) 395{ 396 return 0; 397} 398 399static void cmdq_mbox_shutdown(struct mbox_chan *chan) 400{ 401 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 402 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 403 struct cmdq_task *task, *tmp; 404 unsigned long flags; 405 406 spin_lock_irqsave(&thread->chan->lock, flags); 407 if (list_empty(&thread->task_busy_list)) 408 goto done; 409 410 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 411 412 /* make sure executed tasks have success callback */ 413 cmdq_thread_irq_handler(cmdq, thread); 414 if (list_empty(&thread->task_busy_list)) 415 goto done; 416 417 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 418 list_entry) { 419 cmdq_task_exec_done(task, CMDQ_CB_ERROR); 420 kfree(task); 421 } 422 423 cmdq_thread_disable(cmdq, thread); 424 clk_disable(cmdq->clock); 425done: 426 /* 427 * The thread->task_busy_list empty means thread already disable. The 428 * cmdq_mbox_send_data() always reset thread which clear disable and 429 * suspend statue when first pkt send to channel, so there is no need 430 * to do any operation here, only unlock and leave. 431 */ 432 spin_unlock_irqrestore(&thread->chan->lock, flags); 433} 434 435static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) 436{ 437 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 438 struct cmdq_task_cb *cb; 439 struct cmdq_cb_data data; 440 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 441 struct cmdq_task *task, *tmp; 442 unsigned long flags; 443 u32 enable; 444 445 spin_lock_irqsave(&thread->chan->lock, flags); 446 if (list_empty(&thread->task_busy_list)) 447 goto out; 448 449 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 450 if (!cmdq_thread_is_in_wfe(thread)) 451 goto wait; 452 453 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 454 list_entry) { 455 cb = &task->pkt->async_cb; 456 if (cb->cb) { 457 data.sta = CMDQ_CB_ERROR; 458 data.data = cb->data; 459 cb->cb(data); 460 } 461 list_del(&task->list_entry); 462 kfree(task); 463 } 464 465 cmdq_thread_resume(thread); 466 cmdq_thread_disable(cmdq, thread); 467 clk_disable(cmdq->clock); 468 469out: 470 spin_unlock_irqrestore(&thread->chan->lock, flags); 471 return 0; 472 473wait: 474 cmdq_thread_resume(thread); 475 spin_unlock_irqrestore(&thread->chan->lock, flags); 476 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK, 477 enable, enable == 0, 1, timeout)) { 478 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", 479 (u32)(thread->base - cmdq->base)); 480 481 return -EFAULT; 482 } 483 return 0; 484} 485 486static const struct mbox_chan_ops cmdq_mbox_chan_ops = { 487 .send_data = cmdq_mbox_send_data, 488 .startup = cmdq_mbox_startup, 489 .shutdown = cmdq_mbox_shutdown, 490 .flush = cmdq_mbox_flush, 491}; 492 493static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox, 494 const struct of_phandle_args *sp) 495{ 496 int ind = sp->args[0]; 497 struct cmdq_thread *thread; 498 499 if (ind >= mbox->num_chans) 500 return ERR_PTR(-EINVAL); 501 502 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv; 503 thread->priority = sp->args[1]; 504 thread->chan = &mbox->chans[ind]; 505 506 return &mbox->chans[ind]; 507} 508 509static int cmdq_probe(struct platform_device *pdev) 510{ 511 struct device *dev = &pdev->dev; 512 struct resource *res; 513 struct cmdq *cmdq; 514 int err, i; 515 struct gce_plat *plat_data; 516 517 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); 518 if (!cmdq) 519 return -ENOMEM; 520 521 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 522 cmdq->base = devm_ioremap_resource(dev, res); 523 if (IS_ERR(cmdq->base)) { 524 dev_err(dev, "failed to ioremap gce\n"); 525 return PTR_ERR(cmdq->base); 526 } 527 528 cmdq->irq = platform_get_irq(pdev, 0); 529 if (cmdq->irq < 0) 530 return cmdq->irq; 531 532 plat_data = (struct gce_plat *)of_device_get_match_data(dev); 533 if (!plat_data) { 534 dev_err(dev, "failed to get match data\n"); 535 return -EINVAL; 536 } 537 538 cmdq->thread_nr = plat_data->thread_nr; 539 cmdq->shift_pa = plat_data->shift; 540 cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); 541 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, 542 "mtk_cmdq", cmdq); 543 if (err < 0) { 544 dev_err(dev, "failed to register ISR (%d)\n", err); 545 return err; 546 } 547 548 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n", 549 dev, cmdq->base, cmdq->irq); 550 551 cmdq->clock = devm_clk_get(dev, "gce"); 552 if (IS_ERR(cmdq->clock)) { 553 dev_err(dev, "failed to get gce clk\n"); 554 return PTR_ERR(cmdq->clock); 555 } 556 557 cmdq->mbox.dev = dev; 558 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, 559 sizeof(*cmdq->mbox.chans), GFP_KERNEL); 560 if (!cmdq->mbox.chans) 561 return -ENOMEM; 562 563 cmdq->mbox.num_chans = cmdq->thread_nr; 564 cmdq->mbox.ops = &cmdq_mbox_chan_ops; 565 cmdq->mbox.of_xlate = cmdq_xlate; 566 567 /* make use of TXDONE_BY_ACK */ 568 cmdq->mbox.txdone_irq = false; 569 cmdq->mbox.txdone_poll = false; 570 571 cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr, 572 sizeof(*cmdq->thread), GFP_KERNEL); 573 if (!cmdq->thread) 574 return -ENOMEM; 575 576 for (i = 0; i < cmdq->thread_nr; i++) { 577 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + 578 CMDQ_THR_SIZE * i; 579 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list); 580 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i]; 581 } 582 583 err = devm_mbox_controller_register(dev, &cmdq->mbox); 584 if (err < 0) { 585 dev_err(dev, "failed to register mailbox: %d\n", err); 586 return err; 587 } 588 589 platform_set_drvdata(pdev, cmdq); 590 WARN_ON(clk_prepare(cmdq->clock) < 0); 591 592 cmdq_init(cmdq); 593 594 return 0; 595} 596 597static const struct dev_pm_ops cmdq_pm_ops = { 598 .suspend = cmdq_suspend, 599 .resume = cmdq_resume, 600}; 601 602static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; 603static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; 604static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; 605 606static const struct of_device_id cmdq_of_ids[] = { 607 {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, 608 {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, 609 {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, 610 {} 611}; 612 613static struct platform_driver cmdq_drv = { 614 .probe = cmdq_probe, 615 .remove = cmdq_remove, 616 .driver = { 617 .name = "mtk_cmdq", 618 .pm = &cmdq_pm_ops, 619 .of_match_table = cmdq_of_ids, 620 } 621}; 622 623static int __init cmdq_drv_init(void) 624{ 625 return platform_driver_register(&cmdq_drv); 626} 627 628static void __exit cmdq_drv_exit(void) 629{ 630 platform_driver_unregister(&cmdq_drv); 631} 632 633subsys_initcall(cmdq_drv_init); 634module_exit(cmdq_drv_exit); 635 636MODULE_LICENSE("GPL v2"); 637