1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 4 */ 5 6#include <linux/clk.h> 7#include <linux/firmware/imx/ipc.h> 8#include <linux/interrupt.h> 9#include <linux/io.h> 10#include <linux/iopoll.h> 11#include <linux/kernel.h> 12#include <linux/mailbox_controller.h> 13#include <linux/module.h> 14#include <linux/of_device.h> 15#include <linux/pm_runtime.h> 16#include <linux/suspend.h> 17#include <linux/slab.h> 18 19#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) 20#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) 21#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) 22#define IMX_MU_xSR_BRDIP BIT(9) 23 24/* General Purpose Interrupt Enable */ 25#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) 26/* Receive Interrupt Enable */ 27#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x))) 28/* Transmit Interrupt Enable */ 29#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x))) 30/* General Purpose Interrupt Request */ 31#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x))) 32 33#define IMX_MU_CHANS 16 34/* TX0/RX0/RXDB[0-3] */ 35#define IMX_MU_SCU_CHANS 6 36#define IMX_MU_CHAN_NAME_SIZE 20 37 38enum imx_mu_chan_type { 39 IMX_MU_TYPE_TX, /* Tx */ 40 IMX_MU_TYPE_RX, /* Rx */ 41 IMX_MU_TYPE_TXDB, /* Tx doorbell */ 42 IMX_MU_TYPE_RXDB, /* Rx doorbell */ 43}; 44 45struct imx_sc_rpc_msg_max { 46 struct imx_sc_rpc_msg hdr; 47 u32 data[7]; 48}; 49 50struct imx_mu_con_priv { 51 unsigned int idx; 52 char irq_desc[IMX_MU_CHAN_NAME_SIZE]; 53 enum imx_mu_chan_type type; 54 struct mbox_chan *chan; 55 struct tasklet_struct txdb_tasklet; 56}; 57 58struct imx_mu_priv { 59 struct device *dev; 60 void __iomem *base; 61 spinlock_t xcr_lock; /* control register lock */ 62 63 struct mbox_controller mbox; 64 struct mbox_chan mbox_chans[IMX_MU_CHANS]; 65 66 struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; 67 const struct imx_mu_dcfg *dcfg; 68 struct clk *clk; 69 int irq; 70 bool suspend; 71 72 u32 xcr; 73 74 bool side_b; 75}; 76 77struct imx_mu_dcfg { 78 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); 79 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); 80 void (*init)(struct imx_mu_priv *priv); 81 u32 xTR[4]; /* Transmit Registers */ 82 u32 xRR[4]; /* Receive Registers */ 83 u32 xSR; /* Status Register */ 84 u32 xCR; /* Control Register */ 85}; 86 87static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) 88{ 89 return container_of(mbox, struct imx_mu_priv, mbox); 90} 91 92static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs) 93{ 94 iowrite32(val, priv->base + offs); 95} 96 97static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) 98{ 99 return ioread32(priv->base + offs); 100} 101 102static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) 103{ 104 unsigned long flags; 105 u32 val; 106 107 spin_lock_irqsave(&priv->xcr_lock, flags); 108 val = imx_mu_read(priv, priv->dcfg->xCR); 109 val &= ~clr; 110 val |= set; 111 imx_mu_write(priv, val, priv->dcfg->xCR); 112 spin_unlock_irqrestore(&priv->xcr_lock, flags); 113 114 return val; 115} 116 117static int imx_mu_generic_tx(struct imx_mu_priv *priv, 118 struct imx_mu_con_priv *cp, 119 void *data) 120{ 121 u32 *arg = data; 122 123 switch (cp->type) { 124 case IMX_MU_TYPE_TX: 125 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); 126 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); 127 break; 128 case IMX_MU_TYPE_TXDB: 129 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); 130 tasklet_schedule(&cp->txdb_tasklet); 131 break; 132 default: 133 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 134 return -EINVAL; 135 } 136 137 return 0; 138} 139 140static int imx_mu_generic_rx(struct imx_mu_priv *priv, 141 struct imx_mu_con_priv *cp) 142{ 143 u32 dat; 144 145 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); 146 mbox_chan_received_data(cp->chan, (void *)&dat); 147 148 return 0; 149} 150 151static int imx_mu_scu_tx(struct imx_mu_priv *priv, 152 struct imx_mu_con_priv *cp, 153 void *data) 154{ 155 struct imx_sc_rpc_msg_max *msg = data; 156 u32 *arg = data; 157 int i, ret; 158 u32 xsr; 159 160 switch (cp->type) { 161 case IMX_MU_TYPE_TX: 162 /* 163 * msg->hdr.size specifies the number of u32 words while 164 * sizeof yields bytes. 165 */ 166 167 if (msg->hdr.size > sizeof(*msg) / 4) { 168 /* 169 * The real message size can be different to 170 * struct imx_sc_rpc_msg_max size 171 */ 172 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2); 173 return -EINVAL; 174 } 175 176 for (i = 0; i < 4 && i < msg->hdr.size; i++) 177 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); 178 for (; i < msg->hdr.size; i++) { 179 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, 180 xsr, 181 xsr & IMX_MU_xSR_TEn(i % 4), 182 0, 100); 183 if (ret) { 184 dev_err(priv->dev, "Send data index: %d timeout\n", i); 185 return ret; 186 } 187 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); 188 } 189 190 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); 191 break; 192 default: 193 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); 194 return -EINVAL; 195 } 196 197 return 0; 198} 199 200static int imx_mu_scu_rx(struct imx_mu_priv *priv, 201 struct imx_mu_con_priv *cp) 202{ 203 struct imx_sc_rpc_msg_max msg; 204 u32 *data = (u32 *)&msg; 205 int i, ret; 206 u32 xsr; 207 208 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0)); 209 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]); 210 211 if (msg.hdr.size > sizeof(msg) / 4) { 212 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2); 213 return -EINVAL; 214 } 215 216 for (i = 1; i < msg.hdr.size; i++) { 217 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr, 218 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100); 219 if (ret) { 220 dev_err(priv->dev, "timeout read idx %d\n", i); 221 return ret; 222 } 223 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]); 224 } 225 226 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0); 227 mbox_chan_received_data(cp->chan, (void *)&msg); 228 229 return 0; 230} 231 232static void imx_mu_txdb_tasklet(unsigned long data) 233{ 234 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data; 235 236 mbox_chan_txdone(cp->chan, 0); 237} 238 239static irqreturn_t imx_mu_isr(int irq, void *p) 240{ 241 struct mbox_chan *chan = p; 242 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 243 struct imx_mu_con_priv *cp = chan->con_priv; 244 u32 val, ctrl; 245 246 ctrl = imx_mu_read(priv, priv->dcfg->xCR); 247 val = imx_mu_read(priv, priv->dcfg->xSR); 248 249 switch (cp->type) { 250 case IMX_MU_TYPE_TX: 251 val &= IMX_MU_xSR_TEn(cp->idx) & 252 (ctrl & IMX_MU_xCR_TIEn(cp->idx)); 253 break; 254 case IMX_MU_TYPE_RX: 255 val &= IMX_MU_xSR_RFn(cp->idx) & 256 (ctrl & IMX_MU_xCR_RIEn(cp->idx)); 257 break; 258 case IMX_MU_TYPE_RXDB: 259 val &= IMX_MU_xSR_GIPn(cp->idx) & 260 (ctrl & IMX_MU_xCR_GIEn(cp->idx)); 261 break; 262 default: 263 break; 264 } 265 266 if (!val) 267 return IRQ_NONE; 268 269 if (val == IMX_MU_xSR_TEn(cp->idx)) { 270 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); 271 mbox_chan_txdone(chan, 0); 272 } else if (val == IMX_MU_xSR_RFn(cp->idx)) { 273 priv->dcfg->rx(priv, cp); 274 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { 275 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); 276 mbox_chan_received_data(chan, NULL); 277 } else { 278 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); 279 return IRQ_NONE; 280 } 281 282 if (priv->suspend) 283 pm_system_wakeup(); 284 285 return IRQ_HANDLED; 286} 287 288static int imx_mu_send_data(struct mbox_chan *chan, void *data) 289{ 290 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 291 struct imx_mu_con_priv *cp = chan->con_priv; 292 293 return priv->dcfg->tx(priv, cp, data); 294} 295 296static int imx_mu_startup(struct mbox_chan *chan) 297{ 298 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 299 struct imx_mu_con_priv *cp = chan->con_priv; 300 unsigned long irq_flag = IRQF_SHARED; 301 int ret; 302 303 pm_runtime_get_sync(priv->dev); 304 if (cp->type == IMX_MU_TYPE_TXDB) { 305 /* Tx doorbell don't have ACK support */ 306 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, 307 (unsigned long)cp); 308 return 0; 309 } 310 311 /* IPC MU should be with IRQF_NO_SUSPEND set */ 312 if (!priv->dev->pm_domain) 313 irq_flag |= IRQF_NO_SUSPEND; 314 315 ret = request_irq(priv->irq, imx_mu_isr, irq_flag, 316 cp->irq_desc, chan); 317 if (ret) { 318 dev_err(priv->dev, 319 "Unable to acquire IRQ %d\n", priv->irq); 320 return ret; 321 } 322 323 switch (cp->type) { 324 case IMX_MU_TYPE_RX: 325 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0); 326 break; 327 case IMX_MU_TYPE_RXDB: 328 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0); 329 break; 330 default: 331 break; 332 } 333 334 priv->suspend = true; 335 336 return 0; 337} 338 339static void imx_mu_shutdown(struct mbox_chan *chan) 340{ 341 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); 342 struct imx_mu_con_priv *cp = chan->con_priv; 343 344 if (cp->type == IMX_MU_TYPE_TXDB) { 345 tasklet_kill(&cp->txdb_tasklet); 346 pm_runtime_put_sync(priv->dev); 347 return; 348 } 349 350 switch (cp->type) { 351 case IMX_MU_TYPE_TX: 352 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); 353 break; 354 case IMX_MU_TYPE_RX: 355 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx)); 356 break; 357 case IMX_MU_TYPE_RXDB: 358 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx)); 359 break; 360 default: 361 break; 362 } 363 364 free_irq(priv->irq, chan); 365 pm_runtime_put_sync(priv->dev); 366} 367 368static const struct mbox_chan_ops imx_mu_ops = { 369 .send_data = imx_mu_send_data, 370 .startup = imx_mu_startup, 371 .shutdown = imx_mu_shutdown, 372}; 373 374static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox, 375 const struct of_phandle_args *sp) 376{ 377 u32 type, idx, chan; 378 379 if (sp->args_count != 2) { 380 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 381 return ERR_PTR(-EINVAL); 382 } 383 384 type = sp->args[0]; /* channel type */ 385 idx = sp->args[1]; /* index */ 386 387 switch (type) { 388 case IMX_MU_TYPE_TX: 389 case IMX_MU_TYPE_RX: 390 if (idx != 0) 391 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); 392 chan = type; 393 break; 394 case IMX_MU_TYPE_RXDB: 395 chan = 2 + idx; 396 break; 397 default: 398 dev_err(mbox->dev, "Invalid chan type: %d\n", type); 399 return ERR_PTR(-EINVAL); 400 } 401 402 if (chan >= mbox->num_chans) { 403 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 404 return ERR_PTR(-EINVAL); 405 } 406 407 return &mbox->chans[chan]; 408} 409 410static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, 411 const struct of_phandle_args *sp) 412{ 413 u32 type, idx, chan; 414 415 if (sp->args_count != 2) { 416 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); 417 return ERR_PTR(-EINVAL); 418 } 419 420 type = sp->args[0]; /* channel type */ 421 idx = sp->args[1]; /* index */ 422 chan = type * 4 + idx; 423 424 if (chan >= mbox->num_chans) { 425 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); 426 return ERR_PTR(-EINVAL); 427 } 428 429 return &mbox->chans[chan]; 430} 431 432static void imx_mu_init_generic(struct imx_mu_priv *priv) 433{ 434 unsigned int i; 435 436 for (i = 0; i < IMX_MU_CHANS; i++) { 437 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 438 439 cp->idx = i % 4; 440 cp->type = i >> 2; 441 cp->chan = &priv->mbox_chans[i]; 442 priv->mbox_chans[i].con_priv = cp; 443 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 444 "imx_mu_chan[%i-%i]", cp->type, cp->idx); 445 } 446 447 priv->mbox.num_chans = IMX_MU_CHANS; 448 priv->mbox.of_xlate = imx_mu_xlate; 449 450 if (priv->side_b) 451 return; 452 453 /* Set default MU configuration */ 454 imx_mu_write(priv, 0, priv->dcfg->xCR); 455} 456 457static void imx_mu_init_scu(struct imx_mu_priv *priv) 458{ 459 unsigned int i; 460 461 for (i = 0; i < IMX_MU_SCU_CHANS; i++) { 462 struct imx_mu_con_priv *cp = &priv->con_priv[i]; 463 464 cp->idx = i < 2 ? 0 : i - 2; 465 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; 466 cp->chan = &priv->mbox_chans[i]; 467 priv->mbox_chans[i].con_priv = cp; 468 snprintf(cp->irq_desc, sizeof(cp->irq_desc), 469 "imx_mu_chan[%i-%i]", cp->type, cp->idx); 470 } 471 472 priv->mbox.num_chans = IMX_MU_SCU_CHANS; 473 priv->mbox.of_xlate = imx_mu_scu_xlate; 474 475 /* Set default MU configuration */ 476 imx_mu_write(priv, 0, priv->dcfg->xCR); 477} 478 479static int imx_mu_probe(struct platform_device *pdev) 480{ 481 struct device *dev = &pdev->dev; 482 struct device_node *np = dev->of_node; 483 struct imx_mu_priv *priv; 484 const struct imx_mu_dcfg *dcfg; 485 int ret; 486 487 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 488 if (!priv) 489 return -ENOMEM; 490 491 priv->dev = dev; 492 493 priv->base = devm_platform_ioremap_resource(pdev, 0); 494 if (IS_ERR(priv->base)) 495 return PTR_ERR(priv->base); 496 497 priv->irq = platform_get_irq(pdev, 0); 498 if (priv->irq < 0) 499 return priv->irq; 500 501 dcfg = of_device_get_match_data(dev); 502 if (!dcfg) 503 return -EINVAL; 504 priv->dcfg = dcfg; 505 506 priv->clk = devm_clk_get(dev, NULL); 507 if (IS_ERR(priv->clk)) { 508 if (PTR_ERR(priv->clk) != -ENOENT) 509 return PTR_ERR(priv->clk); 510 511 priv->clk = NULL; 512 } 513 514 ret = clk_prepare_enable(priv->clk); 515 if (ret) { 516 dev_err(dev, "Failed to enable clock\n"); 517 return ret; 518 } 519 520 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); 521 522 priv->dcfg->init(priv); 523 524 spin_lock_init(&priv->xcr_lock); 525 526 priv->mbox.dev = dev; 527 priv->mbox.ops = &imx_mu_ops; 528 priv->mbox.chans = priv->mbox_chans; 529 priv->mbox.txdone_irq = true; 530 531 platform_set_drvdata(pdev, priv); 532 533 ret = devm_mbox_controller_register(dev, &priv->mbox); 534 if (ret) { 535 clk_disable_unprepare(priv->clk); 536 return ret; 537 } 538 539 pm_runtime_enable(dev); 540 541 ret = pm_runtime_get_sync(dev); 542 if (ret < 0) { 543 pm_runtime_put_noidle(dev); 544 goto disable_runtime_pm; 545 } 546 547 ret = pm_runtime_put_sync(dev); 548 if (ret < 0) 549 goto disable_runtime_pm; 550 551 clk_disable_unprepare(priv->clk); 552 553 priv->suspend = false; 554 555 return 0; 556 557disable_runtime_pm: 558 pm_runtime_disable(dev); 559 clk_disable_unprepare(priv->clk); 560 return ret; 561} 562 563static int imx_mu_remove(struct platform_device *pdev) 564{ 565 struct imx_mu_priv *priv = platform_get_drvdata(pdev); 566 567 pm_runtime_disable(priv->dev); 568 569 return 0; 570} 571 572static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 573 .tx = imx_mu_generic_tx, 574 .rx = imx_mu_generic_rx, 575 .init = imx_mu_init_generic, 576 .xTR = {0x0, 0x4, 0x8, 0xc}, 577 .xRR = {0x10, 0x14, 0x18, 0x1c}, 578 .xSR = 0x20, 579 .xCR = 0x24, 580}; 581 582static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 583 .tx = imx_mu_generic_tx, 584 .rx = imx_mu_generic_rx, 585 .init = imx_mu_init_generic, 586 .xTR = {0x20, 0x24, 0x28, 0x2c}, 587 .xRR = {0x40, 0x44, 0x48, 0x4c}, 588 .xSR = 0x60, 589 .xCR = 0x64, 590}; 591 592static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { 593 .tx = imx_mu_scu_tx, 594 .rx = imx_mu_scu_rx, 595 .init = imx_mu_init_scu, 596 .xTR = {0x0, 0x4, 0x8, 0xc}, 597 .xRR = {0x10, 0x14, 0x18, 0x1c}, 598 .xSR = 0x20, 599 .xCR = 0x24, 600}; 601 602static const struct of_device_id imx_mu_dt_ids[] = { 603 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, 604 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, 605 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, 606 { }, 607}; 608MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); 609 610static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) 611{ 612 struct imx_mu_priv *priv = dev_get_drvdata(dev); 613 614 if (!priv->clk) 615 priv->xcr = imx_mu_read(priv, priv->dcfg->xCR); 616 617 return 0; 618} 619 620static int __maybe_unused imx_mu_resume_noirq(struct device *dev) 621{ 622 struct imx_mu_priv *priv = dev_get_drvdata(dev); 623 624 /* 625 * ONLY restore MU when context lost, the TIE could 626 * be set during noirq resume as there is MU data 627 * communication going on, and restore the saved 628 * value will overwrite the TIE and cause MU data 629 * send failed, may lead to system freeze. This issue 630 * is observed by testing freeze mode suspend. 631 */ 632 if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk) 633 imx_mu_write(priv, priv->xcr, priv->dcfg->xCR); 634 635 return 0; 636} 637 638static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 639{ 640 struct imx_mu_priv *priv = dev_get_drvdata(dev); 641 642 clk_disable_unprepare(priv->clk); 643 644 return 0; 645} 646 647static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 648{ 649 struct imx_mu_priv *priv = dev_get_drvdata(dev); 650 int ret; 651 652 ret = clk_prepare_enable(priv->clk); 653 if (ret) 654 dev_err(dev, "failed to enable clock\n"); 655 656 return ret; 657} 658 659static const struct dev_pm_ops imx_mu_pm_ops = { 660 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq, 661 imx_mu_resume_noirq) 662 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 663 imx_mu_runtime_resume, NULL) 664}; 665 666static struct platform_driver imx_mu_driver = { 667 .probe = imx_mu_probe, 668 .remove = imx_mu_remove, 669 .driver = { 670 .name = "imx_mu", 671 .of_match_table = imx_mu_dt_ids, 672 .pm = &imx_mu_pm_ops, 673 }, 674}; 675module_platform_driver(imx_mu_driver); 676 677MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>"); 678MODULE_DESCRIPTION("Message Unit driver for i.MX"); 679MODULE_LICENSE("GPL v2"); 680