1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 8 */ 9 10#define pr_fmt(fmt) "irq-mips-gic: " fmt 11 12#include <linux/bitmap.h> 13#include <linux/clocksource.h> 14#include <linux/cpuhotplug.h> 15#include <linux/init.h> 16#include <linux/interrupt.h> 17#include <linux/irq.h> 18#include <linux/irqchip.h> 19#include <linux/of_address.h> 20#include <linux/percpu.h> 21#include <linux/sched.h> 22#include <linux/smp.h> 23 24#include <asm/mips-cps.h> 25#include <asm/setup.h> 26#include <asm/traps.h> 27 28#include <dt-bindings/interrupt-controller/mips-gic.h> 29 30#define GIC_MAX_INTRS 256 31#define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS) 32 33/* Add 2 to convert GIC CPU pin to core interrupt */ 34#define GIC_CPU_PIN_OFFSET 2 35 36/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 37#define GIC_PIN_TO_VEC_OFFSET 1 38 39/* Convert between local/shared IRQ number and GIC HW IRQ number. */ 40#define GIC_LOCAL_HWIRQ_BASE 0 41#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) 42#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) 43#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS 44#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) 45#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) 46 47void __iomem *mips_gic_base; 48 49static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); 50 51static DEFINE_RAW_SPINLOCK(gic_lock); 52static struct irq_domain *gic_irq_domain; 53static int gic_shared_intrs; 54static unsigned int gic_cpu_pin; 55static unsigned int timer_cpu_pin; 56static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; 57 58#ifdef CONFIG_GENERIC_IRQ_IPI 59static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); 60static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); 61#endif /* CONFIG_GENERIC_IRQ_IPI */ 62 63static struct gic_all_vpes_chip_data { 64 u32 map; 65 bool mask; 66} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; 67 68static void gic_clear_pcpu_masks(unsigned int intr) 69{ 70 unsigned int i; 71 72 /* Clear the interrupt's bit in all pcpu_masks */ 73 for_each_possible_cpu(i) 74 clear_bit(intr, per_cpu_ptr(pcpu_masks, i)); 75} 76 77static bool gic_local_irq_is_routable(int intr) 78{ 79 u32 vpe_ctl; 80 81 /* All local interrupts are routable in EIC mode. */ 82 if (cpu_has_veic) 83 return true; 84 85 vpe_ctl = read_gic_vl_ctl(); 86 switch (intr) { 87 case GIC_LOCAL_INT_TIMER: 88 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; 89 case GIC_LOCAL_INT_PERFCTR: 90 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; 91 case GIC_LOCAL_INT_FDC: 92 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; 93 case GIC_LOCAL_INT_SWINT0: 94 case GIC_LOCAL_INT_SWINT1: 95 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; 96 default: 97 return true; 98 } 99} 100 101static void gic_bind_eic_interrupt(int irq, int set) 102{ 103 /* Convert irq vector # to hw int # */ 104 irq -= GIC_PIN_TO_VEC_OFFSET; 105 106 /* Set irq to use shadow set */ 107 write_gic_vl_eic_shadow_set(irq, set); 108} 109 110static void gic_send_ipi(struct irq_data *d, unsigned int cpu) 111{ 112 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); 113 114 write_gic_wedge(GIC_WEDGE_RW | hwirq); 115} 116 117int gic_get_c0_compare_int(void) 118{ 119 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) 120 return MIPS_CPU_IRQ_BASE + cp0_compare_irq; 121 return irq_create_mapping(gic_irq_domain, 122 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); 123} 124 125int gic_get_c0_perfcount_int(void) 126{ 127 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { 128 /* Is the performance counter shared with the timer? */ 129 if (cp0_perfcount_irq < 0) 130 return -1; 131 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 132 } 133 return irq_create_mapping(gic_irq_domain, 134 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); 135} 136 137int gic_get_c0_fdc_int(void) 138{ 139 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { 140 /* Is the FDC IRQ even present? */ 141 if (cp0_fdc_irq < 0) 142 return -1; 143 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; 144 } 145 146 return irq_create_mapping(gic_irq_domain, 147 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); 148} 149 150static void gic_handle_shared_int(bool chained) 151{ 152 unsigned int intr, virq; 153 unsigned long *pcpu_mask; 154 DECLARE_BITMAP(pending, GIC_MAX_INTRS); 155 156 /* Get per-cpu bitmaps */ 157 pcpu_mask = this_cpu_ptr(pcpu_masks); 158 159 if (mips_cm_is64) 160 __ioread64_copy(pending, addr_gic_pend(), 161 DIV_ROUND_UP(gic_shared_intrs, 64)); 162 else 163 __ioread32_copy(pending, addr_gic_pend(), 164 DIV_ROUND_UP(gic_shared_intrs, 32)); 165 166 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); 167 168 for_each_set_bit(intr, pending, gic_shared_intrs) { 169 virq = irq_linear_revmap(gic_irq_domain, 170 GIC_SHARED_TO_HWIRQ(intr)); 171 if (chained) 172 generic_handle_irq(virq); 173 else 174 do_IRQ(virq); 175 } 176} 177 178static void gic_mask_irq(struct irq_data *d) 179{ 180 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); 181 182 write_gic_rmask(intr); 183 gic_clear_pcpu_masks(intr); 184} 185 186static void gic_unmask_irq(struct irq_data *d) 187{ 188 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); 189 unsigned int cpu; 190 191 write_gic_smask(intr); 192 193 gic_clear_pcpu_masks(intr); 194 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); 195 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); 196} 197 198static void gic_ack_irq(struct irq_data *d) 199{ 200 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); 201 202 write_gic_wedge(irq); 203} 204 205static int gic_set_type(struct irq_data *d, unsigned int type) 206{ 207 unsigned int irq, pol, trig, dual; 208 unsigned long flags; 209 210 irq = GIC_HWIRQ_TO_SHARED(d->hwirq); 211 212 raw_spin_lock_irqsave(&gic_lock, flags); 213 switch (type & IRQ_TYPE_SENSE_MASK) { 214 case IRQ_TYPE_EDGE_FALLING: 215 pol = GIC_POL_FALLING_EDGE; 216 trig = GIC_TRIG_EDGE; 217 dual = GIC_DUAL_SINGLE; 218 break; 219 case IRQ_TYPE_EDGE_RISING: 220 pol = GIC_POL_RISING_EDGE; 221 trig = GIC_TRIG_EDGE; 222 dual = GIC_DUAL_SINGLE; 223 break; 224 case IRQ_TYPE_EDGE_BOTH: 225 pol = 0; /* Doesn't matter */ 226 trig = GIC_TRIG_EDGE; 227 dual = GIC_DUAL_DUAL; 228 break; 229 case IRQ_TYPE_LEVEL_LOW: 230 pol = GIC_POL_ACTIVE_LOW; 231 trig = GIC_TRIG_LEVEL; 232 dual = GIC_DUAL_SINGLE; 233 break; 234 case IRQ_TYPE_LEVEL_HIGH: 235 default: 236 pol = GIC_POL_ACTIVE_HIGH; 237 trig = GIC_TRIG_LEVEL; 238 dual = GIC_DUAL_SINGLE; 239 break; 240 } 241 242 change_gic_pol(irq, pol); 243 change_gic_trig(irq, trig); 244 change_gic_dual(irq, dual); 245 246 if (trig == GIC_TRIG_EDGE) 247 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, 248 handle_edge_irq, NULL); 249 else 250 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, 251 handle_level_irq, NULL); 252 raw_spin_unlock_irqrestore(&gic_lock, flags); 253 254 return 0; 255} 256 257#ifdef CONFIG_SMP 258static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, 259 bool force) 260{ 261 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); 262 unsigned long flags; 263 unsigned int cpu; 264 265 cpu = cpumask_first_and(cpumask, cpu_online_mask); 266 if (cpu >= NR_CPUS) 267 return -EINVAL; 268 269 /* Assumption : cpumask refers to a single CPU */ 270 raw_spin_lock_irqsave(&gic_lock, flags); 271 272 /* Re-route this IRQ */ 273 write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); 274 275 /* Update the pcpu_masks */ 276 gic_clear_pcpu_masks(irq); 277 if (read_gic_mask(irq)) 278 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); 279 280 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 281 raw_spin_unlock_irqrestore(&gic_lock, flags); 282 283 return IRQ_SET_MASK_OK; 284} 285#endif 286 287static struct irq_chip gic_level_irq_controller = { 288 .name = "MIPS GIC", 289 .irq_mask = gic_mask_irq, 290 .irq_unmask = gic_unmask_irq, 291 .irq_set_type = gic_set_type, 292#ifdef CONFIG_SMP 293 .irq_set_affinity = gic_set_affinity, 294#endif 295}; 296 297static struct irq_chip gic_edge_irq_controller = { 298 .name = "MIPS GIC", 299 .irq_ack = gic_ack_irq, 300 .irq_mask = gic_mask_irq, 301 .irq_unmask = gic_unmask_irq, 302 .irq_set_type = gic_set_type, 303#ifdef CONFIG_SMP 304 .irq_set_affinity = gic_set_affinity, 305#endif 306 .ipi_send_single = gic_send_ipi, 307}; 308 309static void gic_handle_local_int(bool chained) 310{ 311 unsigned long pending, masked; 312 unsigned int intr, virq; 313 314 pending = read_gic_vl_pend(); 315 masked = read_gic_vl_mask(); 316 317 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); 318 319 for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) { 320 virq = irq_linear_revmap(gic_irq_domain, 321 GIC_LOCAL_TO_HWIRQ(intr)); 322 if (chained) 323 generic_handle_irq(virq); 324 else 325 do_IRQ(virq); 326 } 327} 328 329static void gic_mask_local_irq(struct irq_data *d) 330{ 331 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); 332 333 write_gic_vl_rmask(BIT(intr)); 334} 335 336static void gic_unmask_local_irq(struct irq_data *d) 337{ 338 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); 339 340 write_gic_vl_smask(BIT(intr)); 341} 342 343static struct irq_chip gic_local_irq_controller = { 344 .name = "MIPS GIC Local", 345 .irq_mask = gic_mask_local_irq, 346 .irq_unmask = gic_unmask_local_irq, 347}; 348 349static void gic_mask_local_irq_all_vpes(struct irq_data *d) 350{ 351 struct gic_all_vpes_chip_data *cd; 352 unsigned long flags; 353 int intr, cpu; 354 355 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); 356 cd = irq_data_get_irq_chip_data(d); 357 cd->mask = false; 358 359 raw_spin_lock_irqsave(&gic_lock, flags); 360 for_each_online_cpu(cpu) { 361 write_gic_vl_other(mips_cm_vp_id(cpu)); 362 write_gic_vo_rmask(BIT(intr)); 363 } 364 raw_spin_unlock_irqrestore(&gic_lock, flags); 365} 366 367static void gic_unmask_local_irq_all_vpes(struct irq_data *d) 368{ 369 struct gic_all_vpes_chip_data *cd; 370 unsigned long flags; 371 int intr, cpu; 372 373 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); 374 cd = irq_data_get_irq_chip_data(d); 375 cd->mask = true; 376 377 raw_spin_lock_irqsave(&gic_lock, flags); 378 for_each_online_cpu(cpu) { 379 write_gic_vl_other(mips_cm_vp_id(cpu)); 380 write_gic_vo_smask(BIT(intr)); 381 } 382 raw_spin_unlock_irqrestore(&gic_lock, flags); 383} 384 385static void gic_all_vpes_irq_cpu_online(void) 386{ 387 static const unsigned int local_intrs[] = { 388 GIC_LOCAL_INT_TIMER, 389 GIC_LOCAL_INT_PERFCTR, 390 GIC_LOCAL_INT_FDC, 391 }; 392 unsigned long flags; 393 int i; 394 395 raw_spin_lock_irqsave(&gic_lock, flags); 396 397 for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { 398 unsigned int intr = local_intrs[i]; 399 struct gic_all_vpes_chip_data *cd; 400 401 cd = &gic_all_vpes_chip_data[intr]; 402 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); 403 if (cd->mask) 404 write_gic_vl_smask(BIT(intr)); 405 } 406 407 raw_spin_unlock_irqrestore(&gic_lock, flags); 408} 409 410static struct irq_chip gic_all_vpes_local_irq_controller = { 411 .name = "MIPS GIC Local", 412 .irq_mask = gic_mask_local_irq_all_vpes, 413 .irq_unmask = gic_unmask_local_irq_all_vpes, 414}; 415 416static void __gic_irq_dispatch(void) 417{ 418 gic_handle_local_int(false); 419 gic_handle_shared_int(false); 420} 421 422static void gic_irq_dispatch(struct irq_desc *desc) 423{ 424 gic_handle_local_int(true); 425 gic_handle_shared_int(true); 426} 427 428static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, 429 irq_hw_number_t hw, unsigned int cpu) 430{ 431 int intr = GIC_HWIRQ_TO_SHARED(hw); 432 struct irq_data *data; 433 unsigned long flags; 434 435 data = irq_get_irq_data(virq); 436 437 raw_spin_lock_irqsave(&gic_lock, flags); 438 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); 439 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); 440 irq_data_update_effective_affinity(data, cpumask_of(cpu)); 441 raw_spin_unlock_irqrestore(&gic_lock, flags); 442 443 return 0; 444} 445 446static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, 447 const u32 *intspec, unsigned int intsize, 448 irq_hw_number_t *out_hwirq, 449 unsigned int *out_type) 450{ 451 if (intsize != 3) 452 return -EINVAL; 453 454 if (intspec[0] == GIC_SHARED) 455 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); 456 else if (intspec[0] == GIC_LOCAL) 457 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); 458 else 459 return -EINVAL; 460 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 461 462 return 0; 463} 464 465static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, 466 irq_hw_number_t hwirq) 467{ 468 struct gic_all_vpes_chip_data *cd; 469 unsigned long flags; 470 unsigned int intr; 471 int err, cpu; 472 u32 map; 473 474 if (hwirq >= GIC_SHARED_HWIRQ_BASE) { 475#ifdef CONFIG_GENERIC_IRQ_IPI 476 /* verify that shared irqs don't conflict with an IPI irq */ 477 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv)) 478 return -EBUSY; 479#endif /* CONFIG_GENERIC_IRQ_IPI */ 480 481 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, 482 &gic_level_irq_controller, 483 NULL); 484 if (err) 485 return err; 486 487 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); 488 return gic_shared_irq_domain_map(d, virq, hwirq, 0); 489 } 490 491 intr = GIC_HWIRQ_TO_LOCAL(hwirq); 492 map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; 493 494 /* 495 * If adding support for more per-cpu interrupts, keep the the 496 * array in gic_all_vpes_irq_cpu_online() in sync. 497 */ 498 switch (intr) { 499 case GIC_LOCAL_INT_TIMER: 500 /* CONFIG_MIPS_CMP workaround (see __gic_init) */ 501 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin; 502 fallthrough; 503 case GIC_LOCAL_INT_PERFCTR: 504 case GIC_LOCAL_INT_FDC: 505 /* 506 * HACK: These are all really percpu interrupts, but 507 * the rest of the MIPS kernel code does not use the 508 * percpu IRQ API for them. 509 */ 510 cd = &gic_all_vpes_chip_data[intr]; 511 cd->map = map; 512 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, 513 &gic_all_vpes_local_irq_controller, 514 cd); 515 if (err) 516 return err; 517 518 irq_set_handler(virq, handle_percpu_irq); 519 break; 520 521 default: 522 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, 523 &gic_local_irq_controller, 524 NULL); 525 if (err) 526 return err; 527 528 irq_set_handler(virq, handle_percpu_devid_irq); 529 irq_set_percpu_devid(virq); 530 break; 531 } 532 533 if (!gic_local_irq_is_routable(intr)) 534 return -EPERM; 535 536 raw_spin_lock_irqsave(&gic_lock, flags); 537 for_each_online_cpu(cpu) { 538 write_gic_vl_other(mips_cm_vp_id(cpu)); 539 write_gic_vo_map(mips_gic_vx_map_reg(intr), map); 540 } 541 raw_spin_unlock_irqrestore(&gic_lock, flags); 542 543 return 0; 544} 545 546static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, 547 unsigned int nr_irqs, void *arg) 548{ 549 struct irq_fwspec *fwspec = arg; 550 irq_hw_number_t hwirq; 551 552 if (fwspec->param[0] == GIC_SHARED) 553 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]); 554 else 555 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]); 556 557 return gic_irq_domain_map(d, virq, hwirq); 558} 559 560void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, 561 unsigned int nr_irqs) 562{ 563} 564 565static const struct irq_domain_ops gic_irq_domain_ops = { 566 .xlate = gic_irq_domain_xlate, 567 .alloc = gic_irq_domain_alloc, 568 .free = gic_irq_domain_free, 569 .map = gic_irq_domain_map, 570}; 571 572#ifdef CONFIG_GENERIC_IRQ_IPI 573 574static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, 575 const u32 *intspec, unsigned int intsize, 576 irq_hw_number_t *out_hwirq, 577 unsigned int *out_type) 578{ 579 /* 580 * There's nothing to translate here. hwirq is dynamically allocated and 581 * the irq type is always edge triggered. 582 * */ 583 *out_hwirq = 0; 584 *out_type = IRQ_TYPE_EDGE_RISING; 585 586 return 0; 587} 588 589static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, 590 unsigned int nr_irqs, void *arg) 591{ 592 struct cpumask *ipimask = arg; 593 irq_hw_number_t hwirq, base_hwirq; 594 int cpu, ret, i; 595 596 base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); 597 if (base_hwirq == gic_shared_intrs) 598 return -ENOMEM; 599 600 /* check that we have enough space */ 601 for (i = base_hwirq; i < nr_irqs; i++) { 602 if (!test_bit(i, ipi_available)) 603 return -EBUSY; 604 } 605 bitmap_clear(ipi_available, base_hwirq, nr_irqs); 606 607 /* map the hwirq for each cpu consecutively */ 608 i = 0; 609 for_each_cpu(cpu, ipimask) { 610 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); 611 612 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, 613 &gic_edge_irq_controller, 614 NULL); 615 if (ret) 616 goto error; 617 618 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq, 619 &gic_edge_irq_controller, 620 NULL); 621 if (ret) 622 goto error; 623 624 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); 625 if (ret) 626 goto error; 627 628 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); 629 if (ret) 630 goto error; 631 632 i++; 633 } 634 635 return 0; 636error: 637 bitmap_set(ipi_available, base_hwirq, nr_irqs); 638 return ret; 639} 640 641static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, 642 unsigned int nr_irqs) 643{ 644 irq_hw_number_t base_hwirq; 645 struct irq_data *data; 646 647 data = irq_get_irq_data(virq); 648 if (!data) 649 return; 650 651 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); 652 bitmap_set(ipi_available, base_hwirq, nr_irqs); 653} 654 655static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, 656 enum irq_domain_bus_token bus_token) 657{ 658 bool is_ipi; 659 660 switch (bus_token) { 661 case DOMAIN_BUS_IPI: 662 is_ipi = d->bus_token == bus_token; 663 return (!node || to_of_node(d->fwnode) == node) && is_ipi; 664 break; 665 default: 666 return 0; 667 } 668} 669 670static const struct irq_domain_ops gic_ipi_domain_ops = { 671 .xlate = gic_ipi_domain_xlate, 672 .alloc = gic_ipi_domain_alloc, 673 .free = gic_ipi_domain_free, 674 .match = gic_ipi_domain_match, 675}; 676 677static int gic_register_ipi_domain(struct device_node *node) 678{ 679 struct irq_domain *gic_ipi_domain; 680 unsigned int v[2], num_ipis; 681 682 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, 683 IRQ_DOMAIN_FLAG_IPI_PER_CPU, 684 GIC_NUM_LOCAL_INTRS + gic_shared_intrs, 685 node, &gic_ipi_domain_ops, NULL); 686 if (!gic_ipi_domain) { 687 pr_err("Failed to add IPI domain"); 688 return -ENXIO; 689 } 690 691 irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI); 692 693 if (node && 694 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) { 695 bitmap_set(ipi_resrv, v[0], v[1]); 696 } else { 697 /* 698 * Reserve 2 interrupts per possible CPU/VP for use as IPIs, 699 * meeting the requirements of arch/mips SMP. 700 */ 701 num_ipis = 2 * num_possible_cpus(); 702 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis); 703 } 704 705 bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); 706 707 return 0; 708} 709 710#else /* !CONFIG_GENERIC_IRQ_IPI */ 711 712static inline int gic_register_ipi_domain(struct device_node *node) 713{ 714 return 0; 715} 716 717#endif /* !CONFIG_GENERIC_IRQ_IPI */ 718 719static int gic_cpu_startup(unsigned int cpu) 720{ 721 /* Enable or disable EIC */ 722 change_gic_vl_ctl(GIC_VX_CTL_EIC, 723 cpu_has_veic ? GIC_VX_CTL_EIC : 0); 724 725 /* Clear all local IRQ masks (ie. disable all local interrupts) */ 726 write_gic_vl_rmask(~0); 727 728 /* Enable desired interrupts */ 729 gic_all_vpes_irq_cpu_online(); 730 731 return 0; 732} 733 734static int __init gic_of_init(struct device_node *node, 735 struct device_node *parent) 736{ 737 unsigned int cpu_vec, i, gicconfig; 738 unsigned long reserved; 739 phys_addr_t gic_base; 740 struct resource res; 741 size_t gic_len; 742 int ret; 743 744 /* Find the first available CPU vector. */ 745 i = 0; 746 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); 747 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", 748 i++, &cpu_vec)) 749 reserved |= BIT(cpu_vec); 750 751 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); 752 if (cpu_vec == hweight_long(ST0_IM)) { 753 pr_err("No CPU vectors available\n"); 754 return -ENODEV; 755 } 756 757 if (of_address_to_resource(node, 0, &res)) { 758 /* 759 * Probe the CM for the GIC base address if not specified 760 * in the device-tree. 761 */ 762 if (mips_cm_present()) { 763 gic_base = read_gcr_gic_base() & 764 ~CM_GCR_GIC_BASE_GICEN; 765 gic_len = 0x20000; 766 pr_warn("Using inherited base address %pa\n", 767 &gic_base); 768 } else { 769 pr_err("Failed to get memory range\n"); 770 return -ENODEV; 771 } 772 } else { 773 gic_base = res.start; 774 gic_len = resource_size(&res); 775 } 776 777 if (mips_cm_present()) { 778 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); 779 /* Ensure GIC region is enabled before trying to access it */ 780 __sync(); 781 } 782 783 mips_gic_base = ioremap(gic_base, gic_len); 784 if (!mips_gic_base) { 785 pr_err("Failed to ioremap gic_base\n"); 786 return -ENOMEM; 787 } 788 789 gicconfig = read_gic_config(); 790 gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS; 791 gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS); 792 gic_shared_intrs = (gic_shared_intrs + 1) * 8; 793 794 if (cpu_has_veic) { 795 /* Always use vector 1 in EIC mode */ 796 gic_cpu_pin = 0; 797 timer_cpu_pin = gic_cpu_pin; 798 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, 799 __gic_irq_dispatch); 800 } else { 801 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; 802 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, 803 gic_irq_dispatch); 804 /* 805 * With the CMP implementation of SMP (deprecated), other CPUs 806 * are started by the bootloader and put into a timer based 807 * waiting poll loop. We must not re-route those CPU's local 808 * timer interrupts as the wait instruction will never finish, 809 * so just handle whatever CPU interrupt it is routed to by 810 * default. 811 * 812 * This workaround should be removed when CMP support is 813 * dropped. 814 */ 815 if (IS_ENABLED(CONFIG_MIPS_CMP) && 816 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { 817 timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP; 818 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 819 GIC_CPU_PIN_OFFSET + 820 timer_cpu_pin, 821 gic_irq_dispatch); 822 } else { 823 timer_cpu_pin = gic_cpu_pin; 824 } 825 } 826 827 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + 828 gic_shared_intrs, 0, 829 &gic_irq_domain_ops, NULL); 830 if (!gic_irq_domain) { 831 pr_err("Failed to add IRQ domain"); 832 return -ENXIO; 833 } 834 835 ret = gic_register_ipi_domain(node); 836 if (ret) 837 return ret; 838 839 board_bind_eic_interrupt = &gic_bind_eic_interrupt; 840 841 /* Setup defaults */ 842 for (i = 0; i < gic_shared_intrs; i++) { 843 change_gic_pol(i, GIC_POL_ACTIVE_HIGH); 844 change_gic_trig(i, GIC_TRIG_LEVEL); 845 write_gic_rmask(i); 846 } 847 848 return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING, 849 "irqchip/mips/gic:starting", 850 gic_cpu_startup, NULL); 851} 852IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); 853