1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * CPU-agnostic ARM page table allocator. 4 * 5 * ARMv7 Short-descriptor format, supporting 6 * - Basic memory attributes 7 * - Simplified access permissions (AP[2:1] model) 8 * - Backwards-compatible TEX remap 9 * - Large pages/supersections (if indicated by the caller) 10 * 11 * Not supporting: 12 * - Legacy access permissions (AP[2:0] model) 13 * 14 * Almost certainly never supporting: 15 * - PXN 16 * - Domains 17 * 18 * Copyright (C) 2014-2015 ARM Limited 19 * Copyright (c) 2014-2015 MediaTek Inc. 20 */ 21 22#define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt 23 24#include <linux/atomic.h> 25#include <linux/dma-mapping.h> 26#include <linux/gfp.h> 27#include <linux/io-pgtable.h> 28#include <linux/iommu.h> 29#include <linux/kernel.h> 30#include <linux/kmemleak.h> 31#include <linux/sizes.h> 32#include <linux/slab.h> 33#include <linux/spinlock.h> 34#include <linux/types.h> 35 36#include <asm/barrier.h> 37 38/* Struct accessors */ 39#define io_pgtable_to_data(x) \ 40 container_of((x), struct arm_v7s_io_pgtable, iop) 41 42#define io_pgtable_ops_to_data(x) \ 43 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) 44 45/* 46 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2, 47 * and 12 bits in a page. With some carefully-chosen coefficients we can 48 * hide the ugly inconsistencies behind these macros and at least let the 49 * rest of the code pretend to be somewhat sane. 50 */ 51#define ARM_V7S_ADDR_BITS 32 52#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) 53#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) 54#define ARM_V7S_TABLE_SHIFT 10 55 56#define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl)) 57#define ARM_V7S_TABLE_SIZE(lvl) \ 58 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte)) 59 60#define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl)) 61#define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl))) 62#define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT)) 63#define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1) 64#define ARM_V7S_LVL_IDX(addr, lvl) ({ \ 65 int _l = lvl; \ 66 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \ 67}) 68 69/* 70 * Large page/supersection entries are effectively a block of 16 page/section 71 * entries, along the lines of the LPAE contiguous hint, but all with the 72 * same output address. For want of a better common name we'll call them 73 * "contiguous" versions of their respective page/section entries here, but 74 * noting the distinction (WRT to TLB maintenance) that they represent *one* 75 * entry repeated 16 times, not 16 separate entries (as in the LPAE case). 76 */ 77#define ARM_V7S_CONT_PAGES 16 78 79/* PTE type bits: these are all mixed up with XN/PXN bits in most cases */ 80#define ARM_V7S_PTE_TYPE_TABLE 0x1 81#define ARM_V7S_PTE_TYPE_PAGE 0x2 82#define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1 83 84#define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) 85#define ARM_V7S_PTE_IS_TABLE(pte, lvl) \ 86 ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE)) 87 88/* Page table bits */ 89#define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl))) 90#define ARM_V7S_ATTR_B BIT(2) 91#define ARM_V7S_ATTR_C BIT(3) 92#define ARM_V7S_ATTR_NS_TABLE BIT(3) 93#define ARM_V7S_ATTR_NS_SECTION BIT(19) 94 95#define ARM_V7S_CONT_SECTION BIT(18) 96#define ARM_V7S_CONT_PAGE_XN_SHIFT 15 97 98/* 99 * The attribute bits are consistently ordered*, but occupy bits [17:10] of 100 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual 101 * fields relative to that 8-bit block, plus a total shift relative to the PTE. 102 */ 103#define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6) 104 105#define ARM_V7S_ATTR_MASK 0xff 106#define ARM_V7S_ATTR_AP0 BIT(0) 107#define ARM_V7S_ATTR_AP1 BIT(1) 108#define ARM_V7S_ATTR_AP2 BIT(5) 109#define ARM_V7S_ATTR_S BIT(6) 110#define ARM_V7S_ATTR_NG BIT(7) 111#define ARM_V7S_TEX_SHIFT 2 112#define ARM_V7S_TEX_MASK 0x7 113#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) 114 115/* MediaTek extend the two bits for PA 32bit/33bit */ 116#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) 117#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) 118 119/* *well, except for TEX on level 2 large pages, of course :( */ 120#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 121#define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT) 122 123/* Simplified access permissions */ 124#define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0 125#define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1 126#define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2 127 128/* Register bits */ 129#define ARM_V7S_RGN_NC 0 130#define ARM_V7S_RGN_WBWA 1 131#define ARM_V7S_RGN_WT 2 132#define ARM_V7S_RGN_WB 3 133 134#define ARM_V7S_PRRR_TYPE_DEVICE 1 135#define ARM_V7S_PRRR_TYPE_NORMAL 2 136#define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2)) 137#define ARM_V7S_PRRR_DS0 BIT(16) 138#define ARM_V7S_PRRR_DS1 BIT(17) 139#define ARM_V7S_PRRR_NS0 BIT(18) 140#define ARM_V7S_PRRR_NS1 BIT(19) 141#define ARM_V7S_PRRR_NOS(n) BIT((n) + 24) 142 143#define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2)) 144#define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16)) 145 146#define ARM_V7S_TTBR_S BIT(1) 147#define ARM_V7S_TTBR_NOS BIT(5) 148#define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3) 149#define ARM_V7S_TTBR_IRGN_ATTR(attr) \ 150 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1)) 151 152#ifdef CONFIG_ZONE_DMA32 153#define ARM_V7S_TABLE_GFP_DMA GFP_DMA32 154#define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA32 155#else 156#define ARM_V7S_TABLE_GFP_DMA GFP_DMA 157#define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA 158#endif 159 160typedef u32 arm_v7s_iopte; 161 162static bool selftest_running; 163 164struct arm_v7s_io_pgtable { 165 struct io_pgtable iop; 166 167 arm_v7s_iopte *pgd; 168 struct kmem_cache *l2_tables; 169 spinlock_t split_lock; 170}; 171 172static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl); 173 174static dma_addr_t __arm_v7s_dma_addr(void *pages) 175{ 176 return (dma_addr_t)virt_to_phys(pages); 177} 178 179static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) 180{ 181 return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 182 (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); 183} 184 185static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, 186 struct io_pgtable_cfg *cfg) 187{ 188 arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl); 189 190 if (!arm_v7s_is_mtk_enabled(cfg)) 191 return pte; 192 193 if (paddr & BIT_ULL(32)) 194 pte |= ARM_V7S_ATTR_MTK_PA_BIT32; 195 if (paddr & BIT_ULL(33)) 196 pte |= ARM_V7S_ATTR_MTK_PA_BIT33; 197 return pte; 198} 199 200static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, 201 struct io_pgtable_cfg *cfg) 202{ 203 arm_v7s_iopte mask; 204 phys_addr_t paddr; 205 206 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) 207 mask = ARM_V7S_TABLE_MASK; 208 else if (arm_v7s_pte_is_cont(pte, lvl)) 209 mask = ARM_V7S_LVL_MASK(lvl) * ARM_V7S_CONT_PAGES; 210 else 211 mask = ARM_V7S_LVL_MASK(lvl); 212 213 paddr = pte & mask; 214 if (!arm_v7s_is_mtk_enabled(cfg)) 215 return paddr; 216 217 if (pte & ARM_V7S_ATTR_MTK_PA_BIT32) 218 paddr |= BIT_ULL(32); 219 if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) 220 paddr |= BIT_ULL(33); 221 return paddr; 222} 223 224static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl, 225 struct arm_v7s_io_pgtable *data) 226{ 227 return phys_to_virt(iopte_to_paddr(pte, lvl, &data->iop.cfg)); 228} 229 230static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp, 231 struct arm_v7s_io_pgtable *data) 232{ 233 struct io_pgtable_cfg *cfg = &data->iop.cfg; 234 struct device *dev = cfg->iommu_dev; 235 phys_addr_t phys; 236 dma_addr_t dma; 237 size_t size = ARM_V7S_TABLE_SIZE(lvl); 238 void *table = NULL; 239 240 if (lvl == 1) 241 table = (void *)__get_free_pages( 242 __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size)); 243 else if (lvl == 2) 244 table = kmem_cache_zalloc(data->l2_tables, gfp); 245 246 if (!table) 247 return NULL; 248 249 phys = virt_to_phys(table); 250 if (phys != (arm_v7s_iopte)phys) { 251 /* Doesn't fit in PTE */ 252 dev_err(dev, "Page table does not fit in PTE: %pa", &phys); 253 goto out_free; 254 } 255 if (!cfg->coherent_walk) { 256 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE); 257 if (dma_mapping_error(dev, dma)) 258 goto out_free; 259 /* 260 * We depend on the IOMMU being able to work with any physical 261 * address directly, so if the DMA layer suggests otherwise by 262 * translating or truncating them, that bodes very badly... 263 */ 264 if (dma != phys) 265 goto out_unmap; 266 } 267 if (lvl == 2) 268 kmemleak_ignore(table); 269 return table; 270 271out_unmap: 272 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); 273 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); 274out_free: 275 if (lvl == 1) 276 free_pages((unsigned long)table, get_order(size)); 277 else 278 kmem_cache_free(data->l2_tables, table); 279 return NULL; 280} 281 282static void __arm_v7s_free_table(void *table, int lvl, 283 struct arm_v7s_io_pgtable *data) 284{ 285 struct io_pgtable_cfg *cfg = &data->iop.cfg; 286 struct device *dev = cfg->iommu_dev; 287 size_t size = ARM_V7S_TABLE_SIZE(lvl); 288 289 if (!cfg->coherent_walk) 290 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size, 291 DMA_TO_DEVICE); 292 if (lvl == 1) 293 free_pages((unsigned long)table, get_order(size)); 294 else 295 kmem_cache_free(data->l2_tables, table); 296} 297 298static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries, 299 struct io_pgtable_cfg *cfg) 300{ 301 if (cfg->coherent_walk) 302 return; 303 304 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep), 305 num_entries * sizeof(*ptep), DMA_TO_DEVICE); 306} 307static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte, 308 int num_entries, struct io_pgtable_cfg *cfg) 309{ 310 int i; 311 312 for (i = 0; i < num_entries; i++) 313 ptep[i] = pte; 314 315 __arm_v7s_pte_sync(ptep, num_entries, cfg); 316} 317 318static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, 319 struct io_pgtable_cfg *cfg) 320{ 321 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS); 322 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S; 323 324 if (!(prot & IOMMU_MMIO)) 325 pte |= ARM_V7S_ATTR_TEX(1); 326 if (ap) { 327 pte |= ARM_V7S_PTE_AF; 328 if (!(prot & IOMMU_PRIV)) 329 pte |= ARM_V7S_PTE_AP_UNPRIV; 330 if (!(prot & IOMMU_WRITE)) 331 pte |= ARM_V7S_PTE_AP_RDONLY; 332 } 333 pte <<= ARM_V7S_ATTR_SHIFT(lvl); 334 335 if ((prot & IOMMU_NOEXEC) && ap) 336 pte |= ARM_V7S_ATTR_XN(lvl); 337 if (prot & IOMMU_MMIO) 338 pte |= ARM_V7S_ATTR_B; 339 else if (prot & IOMMU_CACHE) 340 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C; 341 342 pte |= ARM_V7S_PTE_TYPE_PAGE; 343 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) 344 pte |= ARM_V7S_ATTR_NS_SECTION; 345 346 return pte; 347} 348 349static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl) 350{ 351 int prot = IOMMU_READ; 352 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl); 353 354 if (!(attr & ARM_V7S_PTE_AP_RDONLY)) 355 prot |= IOMMU_WRITE; 356 if (!(attr & ARM_V7S_PTE_AP_UNPRIV)) 357 prot |= IOMMU_PRIV; 358 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0) 359 prot |= IOMMU_MMIO; 360 else if (pte & ARM_V7S_ATTR_C) 361 prot |= IOMMU_CACHE; 362 if (pte & ARM_V7S_ATTR_XN(lvl)) 363 prot |= IOMMU_NOEXEC; 364 365 return prot; 366} 367 368static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl) 369{ 370 if (lvl == 1) { 371 pte |= ARM_V7S_CONT_SECTION; 372 } else if (lvl == 2) { 373 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl); 374 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK; 375 376 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE; 377 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) | 378 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) | 379 ARM_V7S_PTE_TYPE_CONT_PAGE; 380 } 381 return pte; 382} 383 384static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl) 385{ 386 if (lvl == 1) { 387 pte &= ~ARM_V7S_CONT_SECTION; 388 } else if (lvl == 2) { 389 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT); 390 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK << 391 ARM_V7S_CONT_PAGE_TEX_SHIFT); 392 393 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE; 394 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) | 395 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) | 396 ARM_V7S_PTE_TYPE_PAGE; 397 } 398 return pte; 399} 400 401static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl) 402{ 403 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl)) 404 return pte & ARM_V7S_CONT_SECTION; 405 else if (lvl == 2) 406 return !(pte & ARM_V7S_PTE_TYPE_PAGE); 407 return false; 408} 409 410static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *, 411 struct iommu_iotlb_gather *, unsigned long, 412 size_t, int, arm_v7s_iopte *); 413 414static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, 415 unsigned long iova, phys_addr_t paddr, int prot, 416 int lvl, int num_entries, arm_v7s_iopte *ptep) 417{ 418 struct io_pgtable_cfg *cfg = &data->iop.cfg; 419 arm_v7s_iopte pte; 420 int i; 421 422 for (i = 0; i < num_entries; i++) 423 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) { 424 /* 425 * We need to unmap and free the old table before 426 * overwriting it with a block entry. 427 */ 428 arm_v7s_iopte *tblp; 429 size_t sz = ARM_V7S_BLOCK_SIZE(lvl); 430 431 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl); 432 if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz, 433 sz, lvl, tblp) != sz)) 434 return -EINVAL; 435 } else if (ptep[i]) { 436 /* We require an unmap first */ 437 WARN_ON(!selftest_running); 438 return -EEXIST; 439 } 440 441 pte = arm_v7s_prot_to_pte(prot, lvl, cfg); 442 if (num_entries > 1) 443 pte = arm_v7s_pte_to_cont(pte, lvl); 444 445 pte |= paddr_to_iopte(paddr, lvl, cfg); 446 447 __arm_v7s_set_pte(ptep, pte, num_entries, cfg); 448 return 0; 449} 450 451static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, 452 arm_v7s_iopte *ptep, 453 arm_v7s_iopte curr, 454 struct io_pgtable_cfg *cfg) 455{ 456 arm_v7s_iopte old, new; 457 458 new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE; 459 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) 460 new |= ARM_V7S_ATTR_NS_TABLE; 461 462 /* 463 * Ensure the table itself is visible before its PTE can be. 464 * Whilst we could get away with cmpxchg64_release below, this 465 * doesn't have any ordering semantics when !CONFIG_SMP. 466 */ 467 dma_wmb(); 468 469 old = cmpxchg_relaxed(ptep, curr, new); 470 __arm_v7s_pte_sync(ptep, 1, cfg); 471 472 return old; 473} 474 475static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova, 476 phys_addr_t paddr, size_t size, int prot, 477 int lvl, arm_v7s_iopte *ptep, gfp_t gfp) 478{ 479 struct io_pgtable_cfg *cfg = &data->iop.cfg; 480 arm_v7s_iopte pte, *cptep; 481 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); 482 483 /* Find our entry at the current level */ 484 ptep += ARM_V7S_LVL_IDX(iova, lvl); 485 486 /* If we can install a leaf entry at this level, then do so */ 487 if (num_entries) 488 return arm_v7s_init_pte(data, iova, paddr, prot, 489 lvl, num_entries, ptep); 490 491 /* We can't allocate tables at the final level */ 492 if (WARN_ON(lvl == 2)) 493 return -EINVAL; 494 495 /* Grab a pointer to the next level */ 496 pte = READ_ONCE(*ptep); 497 if (!pte) { 498 cptep = __arm_v7s_alloc_table(lvl + 1, gfp, data); 499 if (!cptep) 500 return -ENOMEM; 501 502 pte = arm_v7s_install_table(cptep, ptep, 0, cfg); 503 if (pte) 504 __arm_v7s_free_table(cptep, lvl + 1, data); 505 } else { 506 /* We've no easy way of knowing if it's synced yet, so... */ 507 __arm_v7s_pte_sync(ptep, 1, cfg); 508 } 509 510 if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) { 511 cptep = iopte_deref(pte, lvl, data); 512 } else if (pte) { 513 /* We require an unmap first */ 514 WARN_ON(!selftest_running); 515 return -EEXIST; 516 } 517 518 /* Rinse, repeat */ 519 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp); 520} 521 522static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova, 523 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 524{ 525 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 526 struct io_pgtable *iop = &data->iop; 527 int ret; 528 529 /* If no access, then nothing to do */ 530 if (!(prot & (IOMMU_READ | IOMMU_WRITE))) 531 return 0; 532 533 if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) || 534 paddr >= (1ULL << data->iop.cfg.oas))) 535 return -ERANGE; 536 537 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd, gfp); 538 /* 539 * Synchronise all PTE updates for the new mapping before there's 540 * a chance for anything to kick off a table walk for the new iova. 541 */ 542 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) { 543 io_pgtable_tlb_flush_walk(iop, iova, size, 544 ARM_V7S_BLOCK_SIZE(2)); 545 } else { 546 wmb(); 547 } 548 549 return ret; 550} 551 552static void arm_v7s_free_pgtable(struct io_pgtable *iop) 553{ 554 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop); 555 int i; 556 557 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) { 558 arm_v7s_iopte pte = data->pgd[i]; 559 560 if (ARM_V7S_PTE_IS_TABLE(pte, 1)) 561 __arm_v7s_free_table(iopte_deref(pte, 1, data), 562 2, data); 563 } 564 __arm_v7s_free_table(data->pgd, 1, data); 565 kmem_cache_destroy(data->l2_tables); 566 kfree(data); 567} 568 569static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data, 570 unsigned long iova, int idx, int lvl, 571 arm_v7s_iopte *ptep) 572{ 573 struct io_pgtable *iop = &data->iop; 574 arm_v7s_iopte pte; 575 size_t size = ARM_V7S_BLOCK_SIZE(lvl); 576 int i; 577 578 /* Check that we didn't lose a race to get the lock */ 579 pte = *ptep; 580 if (!arm_v7s_pte_is_cont(pte, lvl)) 581 return pte; 582 583 ptep -= idx & (ARM_V7S_CONT_PAGES - 1); 584 pte = arm_v7s_cont_to_pte(pte, lvl); 585 for (i = 0; i < ARM_V7S_CONT_PAGES; i++) 586 ptep[i] = pte + i * size; 587 588 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg); 589 590 size *= ARM_V7S_CONT_PAGES; 591 io_pgtable_tlb_flush_leaf(iop, iova, size, size); 592 return pte; 593} 594 595static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data, 596 struct iommu_iotlb_gather *gather, 597 unsigned long iova, size_t size, 598 arm_v7s_iopte blk_pte, 599 arm_v7s_iopte *ptep) 600{ 601 struct io_pgtable_cfg *cfg = &data->iop.cfg; 602 arm_v7s_iopte pte, *tablep; 603 int i, unmap_idx, num_entries, num_ptes; 604 605 tablep = __arm_v7s_alloc_table(2, GFP_ATOMIC, data); 606 if (!tablep) 607 return 0; /* Bytes unmapped */ 608 609 num_ptes = ARM_V7S_PTES_PER_LVL(2); 610 num_entries = size >> ARM_V7S_LVL_SHIFT(2); 611 unmap_idx = ARM_V7S_LVL_IDX(iova, 2); 612 613 pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg); 614 if (num_entries > 1) 615 pte = arm_v7s_pte_to_cont(pte, 2); 616 617 for (i = 0; i < num_ptes; i += num_entries, pte += size) { 618 /* Unmap! */ 619 if (i == unmap_idx) 620 continue; 621 622 __arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg); 623 } 624 625 pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg); 626 if (pte != blk_pte) { 627 __arm_v7s_free_table(tablep, 2, data); 628 629 if (!ARM_V7S_PTE_IS_TABLE(pte, 1)) 630 return 0; 631 632 tablep = iopte_deref(pte, 1, data); 633 return __arm_v7s_unmap(data, gather, iova, size, 2, tablep); 634 } 635 636 io_pgtable_tlb_add_page(&data->iop, gather, iova, size); 637 return size; 638} 639 640static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data, 641 struct iommu_iotlb_gather *gather, 642 unsigned long iova, size_t size, int lvl, 643 arm_v7s_iopte *ptep) 644{ 645 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES]; 646 struct io_pgtable *iop = &data->iop; 647 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); 648 649 /* Something went horribly wrong and we ran out of page table */ 650 if (WARN_ON(lvl > 2)) 651 return 0; 652 653 idx = ARM_V7S_LVL_IDX(iova, lvl); 654 ptep += idx; 655 do { 656 pte[i] = READ_ONCE(ptep[i]); 657 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i]))) 658 return 0; 659 } while (++i < num_entries); 660 661 /* 662 * If we've hit a contiguous 'large page' entry at this level, it 663 * needs splitting first, unless we're unmapping the whole lot. 664 * 665 * For splitting, we can't rewrite 16 PTEs atomically, and since we 666 * can't necessarily assume TEX remap we don't have a software bit to 667 * mark live entries being split. In practice (i.e. DMA API code), we 668 * will never be splitting large pages anyway, so just wrap this edge 669 * case in a lock for the sake of correctness and be done with it. 670 */ 671 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) { 672 unsigned long flags; 673 674 spin_lock_irqsave(&data->split_lock, flags); 675 pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep); 676 spin_unlock_irqrestore(&data->split_lock, flags); 677 } 678 679 /* If the size matches this level, we're in the right place */ 680 if (num_entries) { 681 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl); 682 683 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg); 684 685 for (i = 0; i < num_entries; i++) { 686 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) { 687 /* Also flush any partial walks */ 688 io_pgtable_tlb_flush_walk(iop, iova, blk_size, 689 ARM_V7S_BLOCK_SIZE(lvl + 1)); 690 ptep = iopte_deref(pte[i], lvl, data); 691 __arm_v7s_free_table(ptep, lvl + 1, data); 692 } else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) { 693 /* 694 * Order the PTE update against queueing the IOVA, to 695 * guarantee that a flush callback from a different CPU 696 * has observed it before the TLBIALL can be issued. 697 */ 698 smp_wmb(); 699 } else { 700 io_pgtable_tlb_add_page(iop, gather, iova, blk_size); 701 } 702 iova += blk_size; 703 } 704 return size; 705 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) { 706 /* 707 * Insert a table at the next level to map the old region, 708 * minus the part we want to unmap 709 */ 710 return arm_v7s_split_blk_unmap(data, gather, iova, size, pte[0], 711 ptep); 712 } 713 714 /* Keep on walkin' */ 715 ptep = iopte_deref(pte[0], lvl, data); 716 return __arm_v7s_unmap(data, gather, iova, size, lvl + 1, ptep); 717} 718 719static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova, 720 size_t size, struct iommu_iotlb_gather *gather) 721{ 722 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 723 724 if (WARN_ON(upper_32_bits(iova))) 725 return 0; 726 727 return __arm_v7s_unmap(data, gather, iova, size, 1, data->pgd); 728} 729 730static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, 731 unsigned long iova) 732{ 733 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); 734 arm_v7s_iopte *ptep = data->pgd, pte; 735 int lvl = 0; 736 u32 mask; 737 738 do { 739 ptep += ARM_V7S_LVL_IDX(iova, ++lvl); 740 pte = READ_ONCE(*ptep); 741 ptep = iopte_deref(pte, lvl, data); 742 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl)); 743 744 if (!ARM_V7S_PTE_IS_VALID(pte)) 745 return 0; 746 747 mask = ARM_V7S_LVL_MASK(lvl); 748 if (arm_v7s_pte_is_cont(pte, lvl)) 749 mask *= ARM_V7S_CONT_PAGES; 750 return iopte_to_paddr(pte, lvl, &data->iop.cfg) | (iova & ~mask); 751} 752 753static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, 754 void *cookie) 755{ 756 struct arm_v7s_io_pgtable *data; 757 758 if (cfg->ias > ARM_V7S_ADDR_BITS) 759 return NULL; 760 761 if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) 762 return NULL; 763 764 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | 765 IO_PGTABLE_QUIRK_NO_PERMS | 766 IO_PGTABLE_QUIRK_TLBI_ON_MAP | 767 IO_PGTABLE_QUIRK_ARM_MTK_EXT | 768 IO_PGTABLE_QUIRK_NON_STRICT)) 769 return NULL; 770 771 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ 772 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT && 773 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS)) 774 return NULL; 775 776 data = kmalloc(sizeof(*data), GFP_KERNEL); 777 if (!data) 778 return NULL; 779 780 spin_lock_init(&data->split_lock); 781 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", 782 ARM_V7S_TABLE_SIZE(2), 783 ARM_V7S_TABLE_SIZE(2), 784 ARM_V7S_TABLE_SLAB_FLAGS, NULL); 785 if (!data->l2_tables) 786 goto out_free_data; 787 788 data->iop.ops = (struct io_pgtable_ops) { 789 .map = arm_v7s_map, 790 .unmap = arm_v7s_unmap, 791 .iova_to_phys = arm_v7s_iova_to_phys, 792 }; 793 794 /* We have to do this early for __arm_v7s_alloc_table to work... */ 795 data->iop.cfg = *cfg; 796 797 /* 798 * Unless the IOMMU driver indicates supersection support by 799 * having SZ_16M set in the initial bitmap, they won't be used. 800 */ 801 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; 802 803 /* TCR: T0SZ=0, EAE=0 (if applicable) */ 804 cfg->arm_v7s_cfg.tcr = 0; 805 806 /* 807 * TEX remap: the indices used map to the closest equivalent types 808 * under the non-TEX-remap interpretation of those attribute bits, 809 * excepting various implementation-defined aspects of shareability. 810 */ 811 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) | 812 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) | 813 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) | 814 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 | 815 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7); 816 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) | 817 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA); 818 819 /* Looking good; allocate a pgd */ 820 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data); 821 if (!data->pgd) 822 goto out_free_data; 823 824 /* Ensure the empty pgd is visible before any actual TTBR write */ 825 wmb(); 826 827 /* TTBR */ 828 cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S | 829 (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS | 830 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | 831 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) : 832 (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) | 833 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC))); 834 return &data->iop; 835 836out_free_data: 837 kmem_cache_destroy(data->l2_tables); 838 kfree(data); 839 return NULL; 840} 841 842struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = { 843 .alloc = arm_v7s_alloc_pgtable, 844 .free = arm_v7s_free_pgtable, 845}; 846 847#ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST 848 849static struct io_pgtable_cfg *cfg_cookie __initdata; 850 851static void __init dummy_tlb_flush_all(void *cookie) 852{ 853 WARN_ON(cookie != cfg_cookie); 854} 855 856static void __init dummy_tlb_flush(unsigned long iova, size_t size, 857 size_t granule, void *cookie) 858{ 859 WARN_ON(cookie != cfg_cookie); 860 WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); 861} 862 863static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather, 864 unsigned long iova, size_t granule, 865 void *cookie) 866{ 867 dummy_tlb_flush(iova, granule, granule, cookie); 868} 869 870static const struct iommu_flush_ops dummy_tlb_ops __initconst = { 871 .tlb_flush_all = dummy_tlb_flush_all, 872 .tlb_flush_walk = dummy_tlb_flush, 873 .tlb_flush_leaf = dummy_tlb_flush, 874 .tlb_add_page = dummy_tlb_add_page, 875}; 876 877#define __FAIL(ops) ({ \ 878 WARN(1, "selftest: test failed\n"); \ 879 selftest_running = false; \ 880 -EFAULT; \ 881}) 882 883static int __init arm_v7s_do_selftests(void) 884{ 885 struct io_pgtable_ops *ops; 886 struct io_pgtable_cfg cfg = { 887 .tlb = &dummy_tlb_ops, 888 .oas = 32, 889 .ias = 32, 890 .coherent_walk = true, 891 .quirks = IO_PGTABLE_QUIRK_ARM_NS, 892 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 893 }; 894 unsigned int iova, size, iova_start; 895 unsigned int i, loopnr = 0; 896 897 selftest_running = true; 898 899 cfg_cookie = &cfg; 900 901 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg); 902 if (!ops) { 903 pr_err("selftest: failed to allocate io pgtable ops\n"); 904 return -EINVAL; 905 } 906 907 /* 908 * Initial sanity checks. 909 * Empty page tables shouldn't provide any translations. 910 */ 911 if (ops->iova_to_phys(ops, 42)) 912 return __FAIL(ops); 913 914 if (ops->iova_to_phys(ops, SZ_1G + 42)) 915 return __FAIL(ops); 916 917 if (ops->iova_to_phys(ops, SZ_2G + 42)) 918 return __FAIL(ops); 919 920 /* 921 * Distinct mappings of different granule sizes. 922 */ 923 iova = 0; 924 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) { 925 size = 1UL << i; 926 if (ops->map(ops, iova, iova, size, IOMMU_READ | 927 IOMMU_WRITE | 928 IOMMU_NOEXEC | 929 IOMMU_CACHE, GFP_KERNEL)) 930 return __FAIL(ops); 931 932 /* Overlapping mappings */ 933 if (!ops->map(ops, iova, iova + size, size, 934 IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL)) 935 return __FAIL(ops); 936 937 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) 938 return __FAIL(ops); 939 940 iova += SZ_16M; 941 loopnr++; 942 } 943 944 /* Partial unmap */ 945 i = 1; 946 size = 1UL << __ffs(cfg.pgsize_bitmap); 947 while (i < loopnr) { 948 iova_start = i * SZ_16M; 949 if (ops->unmap(ops, iova_start + size, size, NULL) != size) 950 return __FAIL(ops); 951 952 /* Remap of partial unmap */ 953 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ, GFP_KERNEL)) 954 return __FAIL(ops); 955 956 if (ops->iova_to_phys(ops, iova_start + size + 42) 957 != (size + 42)) 958 return __FAIL(ops); 959 i++; 960 } 961 962 /* Full unmap */ 963 iova = 0; 964 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) { 965 size = 1UL << i; 966 967 if (ops->unmap(ops, iova, size, NULL) != size) 968 return __FAIL(ops); 969 970 if (ops->iova_to_phys(ops, iova + 42)) 971 return __FAIL(ops); 972 973 /* Remap full block */ 974 if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL)) 975 return __FAIL(ops); 976 977 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) 978 return __FAIL(ops); 979 980 iova += SZ_16M; 981 } 982 983 free_io_pgtable_ops(ops); 984 985 selftest_running = false; 986 987 pr_info("self test ok\n"); 988 return 0; 989} 990subsys_initcall(arm_v7s_do_selftests); 991#endif 992