1// SPDX-License-Identifier: GPL-2.0 2 3#define pr_fmt(fmt) "DMAR-IR: " fmt 4 5#include <linux/interrupt.h> 6#include <linux/dmar.h> 7#include <linux/spinlock.h> 8#include <linux/slab.h> 9#include <linux/jiffies.h> 10#include <linux/hpet.h> 11#include <linux/pci.h> 12#include <linux/irq.h> 13#include <linux/intel-iommu.h> 14#include <linux/acpi.h> 15#include <linux/irqdomain.h> 16#include <linux/crash_dump.h> 17#include <asm/io_apic.h> 18#include <asm/apic.h> 19#include <asm/smp.h> 20#include <asm/cpu.h> 21#include <asm/irq_remapping.h> 22#include <asm/pci-direct.h> 23#include <asm/msidef.h> 24 25#include "../irq_remapping.h" 26 27enum irq_mode { 28 IRQ_REMAPPING, 29 IRQ_POSTING, 30}; 31 32struct ioapic_scope { 33 struct intel_iommu *iommu; 34 unsigned int id; 35 unsigned int bus; /* PCI bus number */ 36 unsigned int devfn; /* PCI devfn number */ 37}; 38 39struct hpet_scope { 40 struct intel_iommu *iommu; 41 u8 id; 42 unsigned int bus; 43 unsigned int devfn; 44}; 45 46struct irq_2_iommu { 47 struct intel_iommu *iommu; 48 u16 irte_index; 49 u16 sub_handle; 50 u8 irte_mask; 51 enum irq_mode mode; 52}; 53 54struct intel_ir_data { 55 struct irq_2_iommu irq_2_iommu; 56 struct irte irte_entry; 57 union { 58 struct msi_msg msi_entry; 59 }; 60}; 61 62#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) 63#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) 64 65static int __read_mostly eim_mode; 66static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; 67static struct hpet_scope ir_hpet[MAX_HPET_TBS]; 68 69/* 70 * Lock ordering: 71 * ->dmar_global_lock 72 * ->irq_2_ir_lock 73 * ->qi->q_lock 74 * ->iommu->register_lock 75 * Note: 76 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called 77 * in single-threaded environment with interrupt disabled, so no need to tabke 78 * the dmar_global_lock. 79 */ 80DEFINE_RAW_SPINLOCK(irq_2_ir_lock); 81static const struct irq_domain_ops intel_ir_domain_ops; 82 83static void iommu_disable_irq_remapping(struct intel_iommu *iommu); 84static int __init parse_ioapics_under_ir(void); 85 86static bool ir_pre_enabled(struct intel_iommu *iommu) 87{ 88 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); 89} 90 91static void clear_ir_pre_enabled(struct intel_iommu *iommu) 92{ 93 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; 94} 95 96static void init_ir_status(struct intel_iommu *iommu) 97{ 98 u32 gsts; 99 100 gsts = readl(iommu->reg + DMAR_GSTS_REG); 101 if (gsts & DMA_GSTS_IRES) 102 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED; 103} 104 105static int alloc_irte(struct intel_iommu *iommu, 106 struct irq_2_iommu *irq_iommu, u16 count) 107{ 108 struct ir_table *table = iommu->ir_table; 109 unsigned int mask = 0; 110 unsigned long flags; 111 int index; 112 113 if (!count || !irq_iommu) 114 return -1; 115 116 if (count > 1) { 117 count = __roundup_pow_of_two(count); 118 mask = ilog2(count); 119 } 120 121 if (mask > ecap_max_handle_mask(iommu->ecap)) { 122 pr_err("Requested mask %x exceeds the max invalidation handle" 123 " mask value %Lx\n", mask, 124 ecap_max_handle_mask(iommu->ecap)); 125 return -1; 126 } 127 128 raw_spin_lock_irqsave(&irq_2_ir_lock, flags); 129 index = bitmap_find_free_region(table->bitmap, 130 INTR_REMAP_TABLE_ENTRIES, mask); 131 if (index < 0) { 132 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); 133 } else { 134 irq_iommu->iommu = iommu; 135 irq_iommu->irte_index = index; 136 irq_iommu->sub_handle = 0; 137 irq_iommu->irte_mask = mask; 138 irq_iommu->mode = IRQ_REMAPPING; 139 } 140 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); 141 142 return index; 143} 144 145static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) 146{ 147 struct qi_desc desc; 148 149 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) 150 | QI_IEC_SELECTIVE; 151 desc.qw1 = 0; 152 desc.qw2 = 0; 153 desc.qw3 = 0; 154 155 return qi_submit_sync(iommu, &desc, 1, 0); 156} 157 158static int modify_irte(struct irq_2_iommu *irq_iommu, 159 struct irte *irte_modified) 160{ 161 struct intel_iommu *iommu; 162 unsigned long flags; 163 struct irte *irte; 164 int rc, index; 165 166 if (!irq_iommu) 167 return -1; 168 169 raw_spin_lock_irqsave(&irq_2_ir_lock, flags); 170 171 iommu = irq_iommu->iommu; 172 173 index = irq_iommu->irte_index + irq_iommu->sub_handle; 174 irte = &iommu->ir_table->base[index]; 175 176#if defined(CONFIG_HAVE_CMPXCHG_DOUBLE) 177 if ((irte->pst == 1) || (irte_modified->pst == 1)) { 178 bool ret; 179 180 ret = cmpxchg_double(&irte->low, &irte->high, 181 irte->low, irte->high, 182 irte_modified->low, irte_modified->high); 183 /* 184 * We use cmpxchg16 to atomically update the 128-bit IRTE, 185 * and it cannot be updated by the hardware or other processors 186 * behind us, so the return value of cmpxchg16 should be the 187 * same as the old value. 188 */ 189 WARN_ON(!ret); 190 } else 191#endif 192 { 193 set_64bit(&irte->low, irte_modified->low); 194 set_64bit(&irte->high, irte_modified->high); 195 } 196 __iommu_flush_cache(iommu, irte, sizeof(*irte)); 197 198 rc = qi_flush_iec(iommu, index, 0); 199 200 /* Update iommu mode according to the IRTE mode */ 201 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING; 202 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); 203 204 return rc; 205} 206 207static struct irq_domain *map_hpet_to_ir(u8 hpet_id) 208{ 209 int i; 210 211 for (i = 0; i < MAX_HPET_TBS; i++) { 212 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) 213 return ir_hpet[i].iommu->ir_domain; 214 } 215 return NULL; 216} 217 218static struct intel_iommu *map_ioapic_to_iommu(int apic) 219{ 220 int i; 221 222 for (i = 0; i < MAX_IO_APICS; i++) { 223 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) 224 return ir_ioapic[i].iommu; 225 } 226 return NULL; 227} 228 229static struct irq_domain *map_ioapic_to_ir(int apic) 230{ 231 struct intel_iommu *iommu = map_ioapic_to_iommu(apic); 232 233 return iommu ? iommu->ir_domain : NULL; 234} 235 236static struct irq_domain *map_dev_to_ir(struct pci_dev *dev) 237{ 238 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev); 239 240 return drhd ? drhd->iommu->ir_msi_domain : NULL; 241} 242 243static int clear_entries(struct irq_2_iommu *irq_iommu) 244{ 245 struct irte *start, *entry, *end; 246 struct intel_iommu *iommu; 247 int index; 248 249 if (irq_iommu->sub_handle) 250 return 0; 251 252 iommu = irq_iommu->iommu; 253 index = irq_iommu->irte_index; 254 255 start = iommu->ir_table->base + index; 256 end = start + (1 << irq_iommu->irte_mask); 257 258 for (entry = start; entry < end; entry++) { 259 set_64bit(&entry->low, 0); 260 set_64bit(&entry->high, 0); 261 } 262 bitmap_release_region(iommu->ir_table->bitmap, index, 263 irq_iommu->irte_mask); 264 265 return qi_flush_iec(iommu, index, irq_iommu->irte_mask); 266} 267 268/* 269 * source validation type 270 */ 271#define SVT_NO_VERIFY 0x0 /* no verification is required */ 272#define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ 273#define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ 274 275/* 276 * source-id qualifier 277 */ 278#define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ 279#define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore 280 * the third least significant bit 281 */ 282#define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore 283 * the second and third least significant bits 284 */ 285#define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore 286 * the least three significant bits 287 */ 288 289/* 290 * set SVT, SQ and SID fields of irte to verify 291 * source ids of interrupt requests 292 */ 293static void set_irte_sid(struct irte *irte, unsigned int svt, 294 unsigned int sq, unsigned int sid) 295{ 296 if (disable_sourceid_checking) 297 svt = SVT_NO_VERIFY; 298 irte->svt = svt; 299 irte->sq = sq; 300 irte->sid = sid; 301} 302 303/* 304 * Set an IRTE to match only the bus number. Interrupt requests that reference 305 * this IRTE must have a requester-id whose bus number is between or equal 306 * to the start_bus and end_bus arguments. 307 */ 308static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus, 309 unsigned int end_bus) 310{ 311 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, 312 (start_bus << 8) | end_bus); 313} 314 315static int set_ioapic_sid(struct irte *irte, int apic) 316{ 317 int i; 318 u16 sid = 0; 319 320 if (!irte) 321 return -1; 322 323 down_read(&dmar_global_lock); 324 for (i = 0; i < MAX_IO_APICS; i++) { 325 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { 326 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; 327 break; 328 } 329 } 330 up_read(&dmar_global_lock); 331 332 if (sid == 0) { 333 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic); 334 return -1; 335 } 336 337 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); 338 339 return 0; 340} 341 342static int set_hpet_sid(struct irte *irte, u8 id) 343{ 344 int i; 345 u16 sid = 0; 346 347 if (!irte) 348 return -1; 349 350 down_read(&dmar_global_lock); 351 for (i = 0; i < MAX_HPET_TBS; i++) { 352 if (ir_hpet[i].iommu && ir_hpet[i].id == id) { 353 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; 354 break; 355 } 356 } 357 up_read(&dmar_global_lock); 358 359 if (sid == 0) { 360 pr_warn("Failed to set source-id of HPET block (%d)\n", id); 361 return -1; 362 } 363 364 /* 365 * Should really use SQ_ALL_16. Some platforms are broken. 366 * While we figure out the right quirks for these broken platforms, use 367 * SQ_13_IGNORE_3 for now. 368 */ 369 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); 370 371 return 0; 372} 373 374struct set_msi_sid_data { 375 struct pci_dev *pdev; 376 u16 alias; 377 int count; 378 int busmatch_count; 379}; 380 381static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) 382{ 383 struct set_msi_sid_data *data = opaque; 384 385 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias)) 386 data->busmatch_count++; 387 388 data->pdev = pdev; 389 data->alias = alias; 390 data->count++; 391 392 return 0; 393} 394 395static int set_msi_sid(struct irte *irte, struct pci_dev *dev) 396{ 397 struct set_msi_sid_data data; 398 399 if (!irte || !dev) 400 return -1; 401 402 data.count = 0; 403 data.busmatch_count = 0; 404 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); 405 406 /* 407 * DMA alias provides us with a PCI device and alias. The only case 408 * where the it will return an alias on a different bus than the 409 * device is the case of a PCIe-to-PCI bridge, where the alias is for 410 * the subordinate bus. In this case we can only verify the bus. 411 * 412 * If there are multiple aliases, all with the same bus number, 413 * then all we can do is verify the bus. This is typical in NTB 414 * hardware which use proxy IDs where the device will generate traffic 415 * from multiple devfn numbers on the same bus. 416 * 417 * If the alias device is on a different bus than our source device 418 * then we have a topology based alias, use it. 419 * 420 * Otherwise, the alias is for a device DMA quirk and we cannot 421 * assume that MSI uses the same requester ID. Therefore use the 422 * original device. 423 */ 424 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) 425 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias), 426 dev->bus->number); 427 else if (data.count >= 2 && data.busmatch_count == data.count) 428 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number); 429 else if (data.pdev->bus->number != dev->bus->number) 430 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); 431 else 432 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, 433 pci_dev_id(dev)); 434 435 return 0; 436} 437 438static int iommu_load_old_irte(struct intel_iommu *iommu) 439{ 440 struct irte *old_ir_table; 441 phys_addr_t irt_phys; 442 unsigned int i; 443 size_t size; 444 u64 irta; 445 446 /* Check whether the old ir-table has the same size as ours */ 447 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); 448 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) 449 != INTR_REMAP_TABLE_REG_SIZE) 450 return -EINVAL; 451 452 irt_phys = irta & VTD_PAGE_MASK; 453 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte); 454 455 /* Map the old IR table */ 456 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB); 457 if (!old_ir_table) 458 return -ENOMEM; 459 460 /* Copy data over */ 461 memcpy(iommu->ir_table->base, old_ir_table, size); 462 463 __iommu_flush_cache(iommu, iommu->ir_table->base, size); 464 465 /* 466 * Now check the table for used entries and mark those as 467 * allocated in the bitmap 468 */ 469 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) { 470 if (iommu->ir_table->base[i].present) 471 bitmap_set(iommu->ir_table->bitmap, i, 1); 472 } 473 474 memunmap(old_ir_table); 475 476 return 0; 477} 478 479 480static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) 481{ 482 unsigned long flags; 483 u64 addr; 484 u32 sts; 485 486 addr = virt_to_phys((void *)iommu->ir_table->base); 487 488 raw_spin_lock_irqsave(&iommu->register_lock, flags); 489 490 dmar_writeq(iommu->reg + DMAR_IRTA_REG, 491 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); 492 493 /* Set interrupt-remapping table pointer */ 494 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); 495 496 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 497 readl, (sts & DMA_GSTS_IRTPS), sts); 498 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 499 500 /* 501 * Global invalidation of interrupt entry cache to make sure the 502 * hardware uses the new irq remapping table. 503 */ 504 qi_global_iec(iommu); 505} 506 507static void iommu_enable_irq_remapping(struct intel_iommu *iommu) 508{ 509 unsigned long flags; 510 u32 sts; 511 512 raw_spin_lock_irqsave(&iommu->register_lock, flags); 513 514 /* Enable interrupt-remapping */ 515 iommu->gcmd |= DMA_GCMD_IRE; 516 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 517 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 518 readl, (sts & DMA_GSTS_IRES), sts); 519 520 /* Block compatibility-format MSIs */ 521 if (sts & DMA_GSTS_CFIS) { 522 iommu->gcmd &= ~DMA_GCMD_CFI; 523 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 524 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 525 readl, !(sts & DMA_GSTS_CFIS), sts); 526 } 527 528 /* 529 * With CFI clear in the Global Command register, we should be 530 * protected from dangerous (i.e. compatibility) interrupts 531 * regardless of x2apic status. Check just to be sure. 532 */ 533 if (sts & DMA_GSTS_CFIS) 534 WARN(1, KERN_WARNING 535 "Compatibility-format IRQs enabled despite intr remapping;\n" 536 "you are vulnerable to IRQ injection.\n"); 537 538 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 539} 540 541static int intel_setup_irq_remapping(struct intel_iommu *iommu) 542{ 543 struct ir_table *ir_table; 544 struct fwnode_handle *fn; 545 unsigned long *bitmap; 546 struct page *pages; 547 548 if (iommu->ir_table) 549 return 0; 550 551 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); 552 if (!ir_table) 553 return -ENOMEM; 554 555 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, 556 INTR_REMAP_PAGE_ORDER); 557 if (!pages) { 558 pr_err("IR%d: failed to allocate pages of order %d\n", 559 iommu->seq_id, INTR_REMAP_PAGE_ORDER); 560 goto out_free_table; 561 } 562 563 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC); 564 if (bitmap == NULL) { 565 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); 566 goto out_free_pages; 567 } 568 569 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id); 570 if (!fn) 571 goto out_free_bitmap; 572 573 iommu->ir_domain = 574 irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 575 0, INTR_REMAP_TABLE_ENTRIES, 576 fn, &intel_ir_domain_ops, 577 iommu); 578 if (!iommu->ir_domain) { 579 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); 580 goto out_free_fwnode; 581 } 582 iommu->ir_msi_domain = 583 arch_create_remap_msi_irq_domain(iommu->ir_domain, 584 "INTEL-IR-MSI", 585 iommu->seq_id); 586 587 ir_table->base = page_address(pages); 588 ir_table->bitmap = bitmap; 589 iommu->ir_table = ir_table; 590 591 /* 592 * If the queued invalidation is already initialized, 593 * shouldn't disable it. 594 */ 595 if (!iommu->qi) { 596 /* 597 * Clear previous faults. 598 */ 599 dmar_fault(-1, iommu); 600 dmar_disable_qi(iommu); 601 602 if (dmar_enable_qi(iommu)) { 603 pr_err("Failed to enable queued invalidation\n"); 604 goto out_free_ir_domain; 605 } 606 } 607 608 init_ir_status(iommu); 609 610 if (ir_pre_enabled(iommu)) { 611 if (!is_kdump_kernel()) { 612 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n", 613 iommu->name); 614 clear_ir_pre_enabled(iommu); 615 iommu_disable_irq_remapping(iommu); 616 } else if (iommu_load_old_irte(iommu)) 617 pr_err("Failed to copy IR table for %s from previous kernel\n", 618 iommu->name); 619 else 620 pr_info("Copied IR table for %s from previous kernel\n", 621 iommu->name); 622 } 623 624 iommu_set_irq_remapping(iommu, eim_mode); 625 626 return 0; 627 628out_free_ir_domain: 629 if (iommu->ir_msi_domain) 630 irq_domain_remove(iommu->ir_msi_domain); 631 iommu->ir_msi_domain = NULL; 632 irq_domain_remove(iommu->ir_domain); 633 iommu->ir_domain = NULL; 634out_free_fwnode: 635 irq_domain_free_fwnode(fn); 636out_free_bitmap: 637 bitmap_free(bitmap); 638out_free_pages: 639 __free_pages(pages, INTR_REMAP_PAGE_ORDER); 640out_free_table: 641 kfree(ir_table); 642 643 iommu->ir_table = NULL; 644 645 return -ENOMEM; 646} 647 648static void intel_teardown_irq_remapping(struct intel_iommu *iommu) 649{ 650 struct fwnode_handle *fn; 651 652 if (iommu && iommu->ir_table) { 653 if (iommu->ir_msi_domain) { 654 fn = iommu->ir_msi_domain->fwnode; 655 656 irq_domain_remove(iommu->ir_msi_domain); 657 irq_domain_free_fwnode(fn); 658 iommu->ir_msi_domain = NULL; 659 } 660 if (iommu->ir_domain) { 661 fn = iommu->ir_domain->fwnode; 662 663 irq_domain_remove(iommu->ir_domain); 664 irq_domain_free_fwnode(fn); 665 iommu->ir_domain = NULL; 666 } 667 free_pages((unsigned long)iommu->ir_table->base, 668 INTR_REMAP_PAGE_ORDER); 669 bitmap_free(iommu->ir_table->bitmap); 670 kfree(iommu->ir_table); 671 iommu->ir_table = NULL; 672 } 673} 674 675/* 676 * Disable Interrupt Remapping. 677 */ 678static void iommu_disable_irq_remapping(struct intel_iommu *iommu) 679{ 680 unsigned long flags; 681 u32 sts; 682 683 if (!ecap_ir_support(iommu->ecap)) 684 return; 685 686 /* 687 * global invalidation of interrupt entry cache before disabling 688 * interrupt-remapping. 689 */ 690 qi_global_iec(iommu); 691 692 raw_spin_lock_irqsave(&iommu->register_lock, flags); 693 694 sts = readl(iommu->reg + DMAR_GSTS_REG); 695 if (!(sts & DMA_GSTS_IRES)) 696 goto end; 697 698 iommu->gcmd &= ~DMA_GCMD_IRE; 699 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 700 701 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, 702 readl, !(sts & DMA_GSTS_IRES), sts); 703 704end: 705 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 706} 707 708static int __init dmar_x2apic_optout(void) 709{ 710 struct acpi_table_dmar *dmar; 711 dmar = (struct acpi_table_dmar *)dmar_tbl; 712 if (!dmar || no_x2apic_optout) 713 return 0; 714 return dmar->flags & DMAR_X2APIC_OPT_OUT; 715} 716 717static void __init intel_cleanup_irq_remapping(void) 718{ 719 struct dmar_drhd_unit *drhd; 720 struct intel_iommu *iommu; 721 722 for_each_iommu(iommu, drhd) { 723 if (ecap_ir_support(iommu->ecap)) { 724 iommu_disable_irq_remapping(iommu); 725 intel_teardown_irq_remapping(iommu); 726 } 727 } 728 729 if (x2apic_supported()) 730 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); 731} 732 733static int __init intel_prepare_irq_remapping(void) 734{ 735 struct dmar_drhd_unit *drhd; 736 struct intel_iommu *iommu; 737 int eim = 0; 738 739 if (irq_remap_broken) { 740 pr_warn("This system BIOS has enabled interrupt remapping\n" 741 "on a chipset that contains an erratum making that\n" 742 "feature unstable. To maintain system stability\n" 743 "interrupt remapping is being disabled. Please\n" 744 "contact your BIOS vendor for an update\n"); 745 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 746 return -ENODEV; 747 } 748 749 if (dmar_table_init() < 0) 750 return -ENODEV; 751 752 if (!dmar_ir_support()) 753 return -ENODEV; 754 755 if (parse_ioapics_under_ir()) { 756 pr_info("Not enabling interrupt remapping\n"); 757 goto error; 758 } 759 760 /* First make sure all IOMMUs support IRQ remapping */ 761 for_each_iommu(iommu, drhd) 762 if (!ecap_ir_support(iommu->ecap)) 763 goto error; 764 765 /* Detect remapping mode: lapic or x2apic */ 766 if (x2apic_supported()) { 767 eim = !dmar_x2apic_optout(); 768 if (!eim) { 769 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit."); 770 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n"); 771 } 772 } 773 774 for_each_iommu(iommu, drhd) { 775 if (eim && !ecap_eim_support(iommu->ecap)) { 776 pr_info("%s does not support EIM\n", iommu->name); 777 eim = 0; 778 } 779 } 780 781 eim_mode = eim; 782 if (eim) 783 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); 784 785 /* Do the initializations early */ 786 for_each_iommu(iommu, drhd) { 787 if (intel_setup_irq_remapping(iommu)) { 788 pr_err("Failed to setup irq remapping for %s\n", 789 iommu->name); 790 goto error; 791 } 792 } 793 794 return 0; 795 796error: 797 intel_cleanup_irq_remapping(); 798 return -ENODEV; 799} 800 801/* 802 * Set Posted-Interrupts capability. 803 */ 804static inline void set_irq_posting_cap(void) 805{ 806 struct dmar_drhd_unit *drhd; 807 struct intel_iommu *iommu; 808 809 if (!disable_irq_post) { 810 /* 811 * If IRTE is in posted format, the 'pda' field goes across the 812 * 64-bit boundary, we need use cmpxchg16b to atomically update 813 * it. We only expose posted-interrupt when X86_FEATURE_CX16 814 * is supported. Actually, hardware platforms supporting PI 815 * should have X86_FEATURE_CX16 support, this has been confirmed 816 * with Intel hardware guys. 817 */ 818 if (boot_cpu_has(X86_FEATURE_CX16)) 819 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP; 820 821 for_each_iommu(iommu, drhd) 822 if (!cap_pi_support(iommu->cap)) { 823 intel_irq_remap_ops.capability &= 824 ~(1 << IRQ_POSTING_CAP); 825 break; 826 } 827 } 828} 829 830static int __init intel_enable_irq_remapping(void) 831{ 832 struct dmar_drhd_unit *drhd; 833 struct intel_iommu *iommu; 834 bool setup = false; 835 836 /* 837 * Setup Interrupt-remapping for all the DRHD's now. 838 */ 839 for_each_iommu(iommu, drhd) { 840 if (!ir_pre_enabled(iommu)) 841 iommu_enable_irq_remapping(iommu); 842 setup = true; 843 } 844 845 if (!setup) 846 goto error; 847 848 irq_remapping_enabled = 1; 849 850 set_irq_posting_cap(); 851 852 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic"); 853 854 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; 855 856error: 857 intel_cleanup_irq_remapping(); 858 return -1; 859} 860 861static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, 862 struct intel_iommu *iommu, 863 struct acpi_dmar_hardware_unit *drhd) 864{ 865 struct acpi_dmar_pci_path *path; 866 u8 bus; 867 int count, free = -1; 868 869 bus = scope->bus; 870 path = (struct acpi_dmar_pci_path *)(scope + 1); 871 count = (scope->length - sizeof(struct acpi_dmar_device_scope)) 872 / sizeof(struct acpi_dmar_pci_path); 873 874 while (--count > 0) { 875 /* 876 * Access PCI directly due to the PCI 877 * subsystem isn't initialized yet. 878 */ 879 bus = read_pci_config_byte(bus, path->device, path->function, 880 PCI_SECONDARY_BUS); 881 path++; 882 } 883 884 for (count = 0; count < MAX_HPET_TBS; count++) { 885 if (ir_hpet[count].iommu == iommu && 886 ir_hpet[count].id == scope->enumeration_id) 887 return 0; 888 else if (ir_hpet[count].iommu == NULL && free == -1) 889 free = count; 890 } 891 if (free == -1) { 892 pr_warn("Exceeded Max HPET blocks\n"); 893 return -ENOSPC; 894 } 895 896 ir_hpet[free].iommu = iommu; 897 ir_hpet[free].id = scope->enumeration_id; 898 ir_hpet[free].bus = bus; 899 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); 900 pr_info("HPET id %d under DRHD base 0x%Lx\n", 901 scope->enumeration_id, drhd->address); 902 903 return 0; 904} 905 906static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, 907 struct intel_iommu *iommu, 908 struct acpi_dmar_hardware_unit *drhd) 909{ 910 struct acpi_dmar_pci_path *path; 911 u8 bus; 912 int count, free = -1; 913 914 bus = scope->bus; 915 path = (struct acpi_dmar_pci_path *)(scope + 1); 916 count = (scope->length - sizeof(struct acpi_dmar_device_scope)) 917 / sizeof(struct acpi_dmar_pci_path); 918 919 while (--count > 0) { 920 /* 921 * Access PCI directly due to the PCI 922 * subsystem isn't initialized yet. 923 */ 924 bus = read_pci_config_byte(bus, path->device, path->function, 925 PCI_SECONDARY_BUS); 926 path++; 927 } 928 929 for (count = 0; count < MAX_IO_APICS; count++) { 930 if (ir_ioapic[count].iommu == iommu && 931 ir_ioapic[count].id == scope->enumeration_id) 932 return 0; 933 else if (ir_ioapic[count].iommu == NULL && free == -1) 934 free = count; 935 } 936 if (free == -1) { 937 pr_warn("Exceeded Max IO APICS\n"); 938 return -ENOSPC; 939 } 940 941 ir_ioapic[free].bus = bus; 942 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); 943 ir_ioapic[free].iommu = iommu; 944 ir_ioapic[free].id = scope->enumeration_id; 945 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", 946 scope->enumeration_id, drhd->address, iommu->seq_id); 947 948 return 0; 949} 950 951static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, 952 struct intel_iommu *iommu) 953{ 954 int ret = 0; 955 struct acpi_dmar_hardware_unit *drhd; 956 struct acpi_dmar_device_scope *scope; 957 void *start, *end; 958 959 drhd = (struct acpi_dmar_hardware_unit *)header; 960 start = (void *)(drhd + 1); 961 end = ((void *)drhd) + header->length; 962 963 while (start < end && ret == 0) { 964 scope = start; 965 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) 966 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); 967 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) 968 ret = ir_parse_one_hpet_scope(scope, iommu, drhd); 969 start += scope->length; 970 } 971 972 return ret; 973} 974 975static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) 976{ 977 int i; 978 979 for (i = 0; i < MAX_HPET_TBS; i++) 980 if (ir_hpet[i].iommu == iommu) 981 ir_hpet[i].iommu = NULL; 982 983 for (i = 0; i < MAX_IO_APICS; i++) 984 if (ir_ioapic[i].iommu == iommu) 985 ir_ioapic[i].iommu = NULL; 986} 987 988/* 989 * Finds the assocaition between IOAPIC's and its Interrupt-remapping 990 * hardware unit. 991 */ 992static int __init parse_ioapics_under_ir(void) 993{ 994 struct dmar_drhd_unit *drhd; 995 struct intel_iommu *iommu; 996 bool ir_supported = false; 997 int ioapic_idx; 998 999 for_each_iommu(iommu, drhd) { 1000 int ret; 1001 1002 if (!ecap_ir_support(iommu->ecap)) 1003 continue; 1004 1005 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu); 1006 if (ret) 1007 return ret; 1008 1009 ir_supported = true; 1010 } 1011 1012 if (!ir_supported) 1013 return -ENODEV; 1014 1015 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { 1016 int ioapic_id = mpc_ioapic_id(ioapic_idx); 1017 if (!map_ioapic_to_iommu(ioapic_id)) { 1018 pr_err(FW_BUG "ioapic %d has no mapping iommu, " 1019 "interrupt remapping will be disabled\n", 1020 ioapic_id); 1021 return -1; 1022 } 1023 } 1024 1025 return 0; 1026} 1027 1028static int __init ir_dev_scope_init(void) 1029{ 1030 int ret; 1031 1032 if (!irq_remapping_enabled) 1033 return 0; 1034 1035 down_write(&dmar_global_lock); 1036 ret = dmar_dev_scope_init(); 1037 up_write(&dmar_global_lock); 1038 1039 return ret; 1040} 1041rootfs_initcall(ir_dev_scope_init); 1042 1043static void disable_irq_remapping(void) 1044{ 1045 struct dmar_drhd_unit *drhd; 1046 struct intel_iommu *iommu = NULL; 1047 1048 /* 1049 * Disable Interrupt-remapping for all the DRHD's now. 1050 */ 1051 for_each_iommu(iommu, drhd) { 1052 if (!ecap_ir_support(iommu->ecap)) 1053 continue; 1054 1055 iommu_disable_irq_remapping(iommu); 1056 } 1057 1058 /* 1059 * Clear Posted-Interrupts capability. 1060 */ 1061 if (!disable_irq_post) 1062 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP); 1063} 1064 1065static int reenable_irq_remapping(int eim) 1066{ 1067 struct dmar_drhd_unit *drhd; 1068 bool setup = false; 1069 struct intel_iommu *iommu = NULL; 1070 1071 for_each_iommu(iommu, drhd) 1072 if (iommu->qi) 1073 dmar_reenable_qi(iommu); 1074 1075 /* 1076 * Setup Interrupt-remapping for all the DRHD's now. 1077 */ 1078 for_each_iommu(iommu, drhd) { 1079 if (!ecap_ir_support(iommu->ecap)) 1080 continue; 1081 1082 /* Set up interrupt remapping for iommu.*/ 1083 iommu_set_irq_remapping(iommu, eim); 1084 iommu_enable_irq_remapping(iommu); 1085 setup = true; 1086 } 1087 1088 if (!setup) 1089 goto error; 1090 1091 set_irq_posting_cap(); 1092 1093 return 0; 1094 1095error: 1096 /* 1097 * handle error condition gracefully here! 1098 */ 1099 return -1; 1100} 1101 1102/* 1103 * Store the MSI remapping domain pointer in the device if enabled. 1104 * 1105 * This is called from dmar_pci_bus_add_dev() so it works even when DMA 1106 * remapping is disabled. Only update the pointer if the device is not 1107 * already handled by a non default PCI/MSI interrupt domain. This protects 1108 * e.g. VMD devices. 1109 */ 1110void intel_irq_remap_add_device(struct dmar_pci_notify_info *info) 1111{ 1112 if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev)) 1113 return; 1114 1115 dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev)); 1116} 1117 1118static void prepare_irte(struct irte *irte, int vector, unsigned int dest) 1119{ 1120 memset(irte, 0, sizeof(*irte)); 1121 1122 irte->present = 1; 1123 irte->dst_mode = apic->irq_dest_mode; 1124 /* 1125 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the 1126 * actual level or edge trigger will be setup in the IO-APIC 1127 * RTE. This will help simplify level triggered irq migration. 1128 * For more details, see the comments (in io_apic.c) explainig IO-APIC 1129 * irq migration in the presence of interrupt-remapping. 1130 */ 1131 irte->trigger_mode = 0; 1132 irte->dlvry_mode = apic->irq_delivery_mode; 1133 irte->vector = vector; 1134 irte->dest_id = IRTE_DEST(dest); 1135 irte->redir_hint = 1; 1136} 1137 1138static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info) 1139{ 1140 if (!info) 1141 return NULL; 1142 1143 switch (info->type) { 1144 case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT: 1145 return map_ioapic_to_ir(info->devid); 1146 case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT: 1147 return map_hpet_to_ir(info->devid); 1148 default: 1149 WARN_ON_ONCE(1); 1150 return NULL; 1151 } 1152} 1153 1154struct irq_remap_ops intel_irq_remap_ops = { 1155 .prepare = intel_prepare_irq_remapping, 1156 .enable = intel_enable_irq_remapping, 1157 .disable = disable_irq_remapping, 1158 .reenable = reenable_irq_remapping, 1159 .enable_faulting = enable_drhd_fault_handling, 1160 .get_irq_domain = intel_get_irq_domain, 1161}; 1162 1163static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force) 1164{ 1165 struct intel_ir_data *ir_data = irqd->chip_data; 1166 struct irte *irte = &ir_data->irte_entry; 1167 struct irq_cfg *cfg = irqd_cfg(irqd); 1168 1169 /* 1170 * Atomically updates the IRTE with the new destination, vector 1171 * and flushes the interrupt entry cache. 1172 */ 1173 irte->vector = cfg->vector; 1174 irte->dest_id = IRTE_DEST(cfg->dest_apicid); 1175 1176 /* Update the hardware only if the interrupt is in remapped mode. */ 1177 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING) 1178 modify_irte(&ir_data->irq_2_iommu, irte); 1179} 1180 1181/* 1182 * Migrate the IO-APIC irq in the presence of intr-remapping. 1183 * 1184 * For both level and edge triggered, irq migration is a simple atomic 1185 * update(of vector and cpu destination) of IRTE and flush the hardware cache. 1186 * 1187 * For level triggered, we eliminate the io-apic RTE modification (with the 1188 * updated vector information), by using a virtual vector (io-apic pin number). 1189 * Real vector that is used for interrupting cpu will be coming from 1190 * the interrupt-remapping table entry. 1191 * 1192 * As the migration is a simple atomic update of IRTE, the same mechanism 1193 * is used to migrate MSI irq's in the presence of interrupt-remapping. 1194 */ 1195static int 1196intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, 1197 bool force) 1198{ 1199 struct irq_data *parent = data->parent_data; 1200 struct irq_cfg *cfg = irqd_cfg(data); 1201 int ret; 1202 1203 ret = parent->chip->irq_set_affinity(parent, mask, force); 1204 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 1205 return ret; 1206 1207 intel_ir_reconfigure_irte(data, false); 1208 /* 1209 * After this point, all the interrupts will start arriving 1210 * at the new destination. So, time to cleanup the previous 1211 * vector allocation. 1212 */ 1213 send_cleanup_vector(cfg); 1214 1215 return IRQ_SET_MASK_OK_DONE; 1216} 1217 1218static void intel_ir_compose_msi_msg(struct irq_data *irq_data, 1219 struct msi_msg *msg) 1220{ 1221 struct intel_ir_data *ir_data = irq_data->chip_data; 1222 1223 *msg = ir_data->msi_entry; 1224} 1225 1226static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info) 1227{ 1228 struct intel_ir_data *ir_data = data->chip_data; 1229 struct vcpu_data *vcpu_pi_info = info; 1230 1231 /* stop posting interrupts, back to remapping mode */ 1232 if (!vcpu_pi_info) { 1233 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry); 1234 } else { 1235 struct irte irte_pi; 1236 1237 /* 1238 * We are not caching the posted interrupt entry. We 1239 * copy the data from the remapped entry and modify 1240 * the fields which are relevant for posted mode. The 1241 * cached remapped entry is used for switching back to 1242 * remapped mode. 1243 */ 1244 memset(&irte_pi, 0, sizeof(irte_pi)); 1245 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry); 1246 1247 /* Update the posted mode fields */ 1248 irte_pi.p_pst = 1; 1249 irte_pi.p_urgent = 0; 1250 irte_pi.p_vector = vcpu_pi_info->vector; 1251 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >> 1252 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT); 1253 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) & 1254 ~(-1UL << PDA_HIGH_BIT); 1255 1256 modify_irte(&ir_data->irq_2_iommu, &irte_pi); 1257 } 1258 1259 return 0; 1260} 1261 1262static struct irq_chip intel_ir_chip = { 1263 .name = "INTEL-IR", 1264 .irq_ack = apic_ack_irq, 1265 .irq_set_affinity = intel_ir_set_affinity, 1266 .irq_compose_msi_msg = intel_ir_compose_msi_msg, 1267 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity, 1268}; 1269 1270static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, 1271 struct irq_cfg *irq_cfg, 1272 struct irq_alloc_info *info, 1273 int index, int sub_handle) 1274{ 1275 struct IR_IO_APIC_route_entry *entry; 1276 struct irte *irte = &data->irte_entry; 1277 struct msi_msg *msg = &data->msi_entry; 1278 1279 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); 1280 switch (info->type) { 1281 case X86_IRQ_ALLOC_TYPE_IOAPIC: 1282 /* Set source-id of interrupt request */ 1283 set_ioapic_sid(irte, info->devid); 1284 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", 1285 info->devid, irte->present, irte->fpd, 1286 irte->dst_mode, irte->redir_hint, 1287 irte->trigger_mode, irte->dlvry_mode, 1288 irte->avail, irte->vector, irte->dest_id, 1289 irte->sid, irte->sq, irte->svt); 1290 1291 entry = (struct IR_IO_APIC_route_entry *)info->ioapic.entry; 1292 info->ioapic.entry = NULL; 1293 memset(entry, 0, sizeof(*entry)); 1294 entry->index2 = (index >> 15) & 0x1; 1295 entry->zero = 0; 1296 entry->format = 1; 1297 entry->index = (index & 0x7fff); 1298 /* 1299 * IO-APIC RTE will be configured with virtual vector. 1300 * irq handler will do the explicit EOI to the io-apic. 1301 */ 1302 entry->vector = info->ioapic.pin; 1303 entry->mask = 0; /* enable IRQ */ 1304 entry->trigger = info->ioapic.trigger; 1305 entry->polarity = info->ioapic.polarity; 1306 if (info->ioapic.trigger) 1307 entry->mask = 1; /* Mask level triggered irqs. */ 1308 break; 1309 1310 case X86_IRQ_ALLOC_TYPE_HPET: 1311 case X86_IRQ_ALLOC_TYPE_PCI_MSI: 1312 case X86_IRQ_ALLOC_TYPE_PCI_MSIX: 1313 if (info->type == X86_IRQ_ALLOC_TYPE_HPET) 1314 set_hpet_sid(irte, info->devid); 1315 else 1316 set_msi_sid(irte, msi_desc_to_pci_dev(info->desc)); 1317 1318 msg->address_hi = MSI_ADDR_BASE_HI; 1319 msg->data = sub_handle; 1320 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | 1321 MSI_ADDR_IR_SHV | 1322 MSI_ADDR_IR_INDEX1(index) | 1323 MSI_ADDR_IR_INDEX2(index); 1324 break; 1325 1326 default: 1327 BUG_ON(1); 1328 break; 1329 } 1330} 1331 1332static void intel_free_irq_resources(struct irq_domain *domain, 1333 unsigned int virq, unsigned int nr_irqs) 1334{ 1335 struct irq_data *irq_data; 1336 struct intel_ir_data *data; 1337 struct irq_2_iommu *irq_iommu; 1338 unsigned long flags; 1339 int i; 1340 for (i = 0; i < nr_irqs; i++) { 1341 irq_data = irq_domain_get_irq_data(domain, virq + i); 1342 if (irq_data && irq_data->chip_data) { 1343 data = irq_data->chip_data; 1344 irq_iommu = &data->irq_2_iommu; 1345 raw_spin_lock_irqsave(&irq_2_ir_lock, flags); 1346 clear_entries(irq_iommu); 1347 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); 1348 irq_domain_reset_irq_data(irq_data); 1349 kfree(data); 1350 } 1351 } 1352} 1353 1354static int intel_irq_remapping_alloc(struct irq_domain *domain, 1355 unsigned int virq, unsigned int nr_irqs, 1356 void *arg) 1357{ 1358 struct intel_iommu *iommu = domain->host_data; 1359 struct irq_alloc_info *info = arg; 1360 struct intel_ir_data *data, *ird; 1361 struct irq_data *irq_data; 1362 struct irq_cfg *irq_cfg; 1363 int i, ret, index; 1364 1365 if (!info || !iommu) 1366 return -EINVAL; 1367 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI && 1368 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX) 1369 return -EINVAL; 1370 1371 /* 1372 * With IRQ remapping enabled, don't need contiguous CPU vectors 1373 * to support multiple MSI interrupts. 1374 */ 1375 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) 1376 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; 1377 1378 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 1379 if (ret < 0) 1380 return ret; 1381 1382 ret = -ENOMEM; 1383 data = kzalloc(sizeof(*data), GFP_KERNEL); 1384 if (!data) 1385 goto out_free_parent; 1386 1387 down_read(&dmar_global_lock); 1388 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs); 1389 up_read(&dmar_global_lock); 1390 if (index < 0) { 1391 pr_warn("Failed to allocate IRTE\n"); 1392 kfree(data); 1393 goto out_free_parent; 1394 } 1395 1396 for (i = 0; i < nr_irqs; i++) { 1397 irq_data = irq_domain_get_irq_data(domain, virq + i); 1398 irq_cfg = irqd_cfg(irq_data); 1399 if (!irq_data || !irq_cfg) { 1400 if (!i) 1401 kfree(data); 1402 ret = -EINVAL; 1403 goto out_free_data; 1404 } 1405 1406 if (i > 0) { 1407 ird = kzalloc(sizeof(*ird), GFP_KERNEL); 1408 if (!ird) 1409 goto out_free_data; 1410 /* Initialize the common data */ 1411 ird->irq_2_iommu = data->irq_2_iommu; 1412 ird->irq_2_iommu.sub_handle = i; 1413 } else { 1414 ird = data; 1415 } 1416 1417 irq_data->hwirq = (index << 16) + i; 1418 irq_data->chip_data = ird; 1419 irq_data->chip = &intel_ir_chip; 1420 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i); 1421 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); 1422 } 1423 return 0; 1424 1425out_free_data: 1426 intel_free_irq_resources(domain, virq, i); 1427out_free_parent: 1428 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1429 return ret; 1430} 1431 1432static void intel_irq_remapping_free(struct irq_domain *domain, 1433 unsigned int virq, unsigned int nr_irqs) 1434{ 1435 intel_free_irq_resources(domain, virq, nr_irqs); 1436 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1437} 1438 1439static int intel_irq_remapping_activate(struct irq_domain *domain, 1440 struct irq_data *irq_data, bool reserve) 1441{ 1442 intel_ir_reconfigure_irte(irq_data, true); 1443 return 0; 1444} 1445 1446static void intel_irq_remapping_deactivate(struct irq_domain *domain, 1447 struct irq_data *irq_data) 1448{ 1449 struct intel_ir_data *data = irq_data->chip_data; 1450 struct irte entry; 1451 1452 memset(&entry, 0, sizeof(entry)); 1453 modify_irte(&data->irq_2_iommu, &entry); 1454} 1455 1456static const struct irq_domain_ops intel_ir_domain_ops = { 1457 .alloc = intel_irq_remapping_alloc, 1458 .free = intel_irq_remapping_free, 1459 .activate = intel_irq_remapping_activate, 1460 .deactivate = intel_irq_remapping_deactivate, 1461}; 1462 1463/* 1464 * Support of Interrupt Remapping Unit Hotplug 1465 */ 1466static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) 1467{ 1468 int ret; 1469 int eim = x2apic_enabled(); 1470 1471 if (eim && !ecap_eim_support(iommu->ecap)) { 1472 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", 1473 iommu->reg_phys, iommu->ecap); 1474 return -ENODEV; 1475 } 1476 1477 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { 1478 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", 1479 iommu->reg_phys); 1480 return -ENODEV; 1481 } 1482 1483 /* TODO: check all IOAPICs are covered by IOMMU */ 1484 1485 /* Setup Interrupt-remapping now. */ 1486 ret = intel_setup_irq_remapping(iommu); 1487 if (ret) { 1488 pr_err("Failed to setup irq remapping for %s\n", 1489 iommu->name); 1490 intel_teardown_irq_remapping(iommu); 1491 ir_remove_ioapic_hpet_scope(iommu); 1492 } else { 1493 iommu_enable_irq_remapping(iommu); 1494 } 1495 1496 return ret; 1497} 1498 1499int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) 1500{ 1501 int ret = 0; 1502 struct intel_iommu *iommu = dmaru->iommu; 1503 1504 if (!irq_remapping_enabled) 1505 return 0; 1506 if (iommu == NULL) 1507 return -EINVAL; 1508 if (!ecap_ir_support(iommu->ecap)) 1509 return 0; 1510 if (irq_remapping_cap(IRQ_POSTING_CAP) && 1511 !cap_pi_support(iommu->cap)) 1512 return -EBUSY; 1513 1514 if (insert) { 1515 if (!iommu->ir_table) 1516 ret = dmar_ir_add(dmaru, iommu); 1517 } else { 1518 if (iommu->ir_table) { 1519 if (!bitmap_empty(iommu->ir_table->bitmap, 1520 INTR_REMAP_TABLE_ENTRIES)) { 1521 ret = -EBUSY; 1522 } else { 1523 iommu_disable_irq_remapping(iommu); 1524 intel_teardown_irq_remapping(iommu); 1525 ir_remove_ioapic_hpet_scope(iommu); 1526 } 1527 } 1528 } 1529 1530 return ret; 1531} 1532