1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8#define pr_fmt(fmt) "AMD-Vi: " fmt 9#define dev_fmt(fmt) pr_fmt(fmt) 10 11#include <linux/pci.h> 12#include <linux/acpi.h> 13#include <linux/list.h> 14#include <linux/bitmap.h> 15#include <linux/slab.h> 16#include <linux/syscore_ops.h> 17#include <linux/interrupt.h> 18#include <linux/msi.h> 19#include <linux/amd-iommu.h> 20#include <linux/export.h> 21#include <linux/kmemleak.h> 22#include <linux/mem_encrypt.h> 23#include <linux/iopoll.h> 24#include <asm/pci-direct.h> 25#include <asm/iommu.h> 26#include <asm/apic.h> 27#include <asm/msidef.h> 28#include <asm/gart.h> 29#include <asm/x86_init.h> 30#include <asm/iommu_table.h> 31#include <asm/io_apic.h> 32#include <asm/irq_remapping.h> 33#include <asm/set_memory.h> 34 35#include <linux/crash_dump.h> 36 37#include "amd_iommu.h" 38#include "../irq_remapping.h" 39 40/* 41 * definitions for the ACPI scanning code 42 */ 43#define IVRS_HEADER_LENGTH 48 44 45#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 46#define ACPI_IVMD_TYPE_ALL 0x20 47#define ACPI_IVMD_TYPE 0x21 48#define ACPI_IVMD_TYPE_RANGE 0x22 49 50#define IVHD_DEV_ALL 0x01 51#define IVHD_DEV_SELECT 0x02 52#define IVHD_DEV_SELECT_RANGE_START 0x03 53#define IVHD_DEV_RANGE_END 0x04 54#define IVHD_DEV_ALIAS 0x42 55#define IVHD_DEV_ALIAS_RANGE 0x43 56#define IVHD_DEV_EXT_SELECT 0x46 57#define IVHD_DEV_EXT_SELECT_RANGE 0x47 58#define IVHD_DEV_SPECIAL 0x48 59#define IVHD_DEV_ACPI_HID 0xf0 60 61#define UID_NOT_PRESENT 0 62#define UID_IS_INTEGER 1 63#define UID_IS_CHARACTER 2 64 65#define IVHD_SPECIAL_IOAPIC 1 66#define IVHD_SPECIAL_HPET 2 67 68#define IVHD_FLAG_HT_TUN_EN_MASK 0x01 69#define IVHD_FLAG_PASSPW_EN_MASK 0x02 70#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 71#define IVHD_FLAG_ISOC_EN_MASK 0x08 72 73#define IVMD_FLAG_EXCL_RANGE 0x08 74#define IVMD_FLAG_IW 0x04 75#define IVMD_FLAG_IR 0x02 76#define IVMD_FLAG_UNITY_MAP 0x01 77 78#define ACPI_DEVFLAG_INITPASS 0x01 79#define ACPI_DEVFLAG_EXTINT 0x02 80#define ACPI_DEVFLAG_NMI 0x04 81#define ACPI_DEVFLAG_SYSMGT1 0x10 82#define ACPI_DEVFLAG_SYSMGT2 0x20 83#define ACPI_DEVFLAG_LINT0 0x40 84#define ACPI_DEVFLAG_LINT1 0x80 85#define ACPI_DEVFLAG_ATSDIS 0x10000000 86 87#define LOOP_TIMEOUT 2000000 88 89#define IVRS_GET_SBDF_ID(seg, bus, dev, fd) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ 90 | ((dev & 0x1f) << 3) | (fn & 0x7)) 91 92/* 93 * ACPI table definitions 94 * 95 * These data structures are laid over the table to parse the important values 96 * out of it. 97 */ 98 99extern const struct iommu_ops amd_iommu_ops; 100 101/* 102 * structure describing one IOMMU in the ACPI table. Typically followed by one 103 * or more ivhd_entrys. 104 */ 105struct ivhd_header { 106 u8 type; 107 u8 flags; 108 u16 length; 109 u16 devid; 110 u16 cap_ptr; 111 u64 mmio_phys; 112 u16 pci_seg; 113 u16 info; 114 u32 efr_attr; 115 116 /* Following only valid on IVHD type 11h and 40h */ 117 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 118 u64 res; 119} __attribute__((packed)); 120 121/* 122 * A device entry describing which devices a specific IOMMU translates and 123 * which requestor ids they use. 124 */ 125struct ivhd_entry { 126 u8 type; 127 u16 devid; 128 u8 flags; 129 u32 ext; 130 u32 hidh; 131 u64 cid; 132 u8 uidf; 133 u8 uidl; 134 u8 uid; 135} __attribute__((packed)); 136 137/* 138 * An AMD IOMMU memory definition structure. It defines things like exclusion 139 * ranges for devices and regions that should be unity mapped. 140 */ 141struct ivmd_header { 142 u8 type; 143 u8 flags; 144 u16 length; 145 u16 devid; 146 u16 aux; 147 u64 resv; 148 u64 range_start; 149 u64 range_length; 150} __attribute__((packed)); 151 152bool amd_iommu_dump; 153bool amd_iommu_irq_remap __read_mostly; 154 155int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 156static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 157 158static bool amd_iommu_detected; 159static bool __initdata amd_iommu_disabled; 160static int amd_iommu_target_ivhd_type; 161 162u16 amd_iommu_last_bdf; /* largest PCI device id we have 163 to handle */ 164LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings 165 we find in ACPI */ 166bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ 167 168LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 169 system */ 170 171/* Array to assign indices to IOMMUs*/ 172struct amd_iommu *amd_iommus[MAX_IOMMUS]; 173 174/* Number of IOMMUs present in the system */ 175static int amd_iommus_present; 176 177/* IOMMUs have a non-present cache? */ 178bool amd_iommu_np_cache __read_mostly; 179bool amd_iommu_iotlb_sup __read_mostly = true; 180 181u32 amd_iommu_max_pasid __read_mostly = ~0; 182 183bool amd_iommu_v2_present __read_mostly; 184static bool amd_iommu_pc_present __read_mostly; 185 186bool amd_iommu_force_isolation __read_mostly; 187 188/* 189 * Pointer to the device table which is shared by all AMD IOMMUs 190 * it is indexed by the PCI device id or the HT unit id and contains 191 * information about the domain the device belongs to as well as the 192 * page table root pointer. 193 */ 194struct dev_table_entry *amd_iommu_dev_table; 195/* 196 * Pointer to a device table which the content of old device table 197 * will be copied to. It's only be used in kdump kernel. 198 */ 199static struct dev_table_entry *old_dev_tbl_cpy; 200 201/* 202 * The alias table is a driver specific data structure which contains the 203 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 204 * More than one device can share the same requestor id. 205 */ 206u16 *amd_iommu_alias_table; 207 208/* 209 * The rlookup table is used to find the IOMMU which is responsible 210 * for a specific device. It is also indexed by the PCI device id. 211 */ 212struct amd_iommu **amd_iommu_rlookup_table; 213EXPORT_SYMBOL(amd_iommu_rlookup_table); 214 215/* 216 * This table is used to find the irq remapping table for a given device id 217 * quickly. 218 */ 219struct irq_remap_table **irq_lookup_table; 220 221/* 222 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 223 * to know which ones are already in use. 224 */ 225unsigned long *amd_iommu_pd_alloc_bitmap; 226 227static u32 dev_table_size; /* size of the device table */ 228static u32 alias_table_size; /* size of the alias table */ 229static u32 rlookup_table_size; /* size if the rlookup table */ 230 231enum iommu_init_state { 232 IOMMU_START_STATE, 233 IOMMU_IVRS_DETECTED, 234 IOMMU_ACPI_FINISHED, 235 IOMMU_ENABLED, 236 IOMMU_PCI_INIT, 237 IOMMU_INTERRUPTS_EN, 238 IOMMU_DMA_OPS, 239 IOMMU_INITIALIZED, 240 IOMMU_NOT_FOUND, 241 IOMMU_INIT_ERROR, 242 IOMMU_CMDLINE_DISABLED, 243}; 244 245/* Early ioapic and hpet maps from kernel command line */ 246#define EARLY_MAP_SIZE 4 247static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 248static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 249static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 250 251static int __initdata early_ioapic_map_size; 252static int __initdata early_hpet_map_size; 253static int __initdata early_acpihid_map_size; 254 255static bool __initdata cmdline_maps; 256 257static enum iommu_init_state init_state = IOMMU_START_STATE; 258 259static int amd_iommu_enable_interrupts(void); 260static int __init iommu_go_to_state(enum iommu_init_state state); 261static void init_device_table_dma(void); 262 263static bool amd_iommu_pre_enabled = true; 264 265static u32 amd_iommu_ivinfo __initdata; 266 267bool translation_pre_enabled(struct amd_iommu *iommu) 268{ 269 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 270} 271EXPORT_SYMBOL(translation_pre_enabled); 272 273static void clear_translation_pre_enabled(struct amd_iommu *iommu) 274{ 275 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 276} 277 278static void init_translation_status(struct amd_iommu *iommu) 279{ 280 u64 ctrl; 281 282 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 283 if (ctrl & (1<<CONTROL_IOMMU_EN)) 284 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 285} 286 287static inline void update_last_devid(u16 devid) 288{ 289 if (devid > amd_iommu_last_bdf) 290 amd_iommu_last_bdf = devid; 291} 292 293static inline unsigned long tbl_size(int entry_size) 294{ 295 unsigned shift = PAGE_SHIFT + 296 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 297 298 return 1UL << shift; 299} 300 301int amd_iommu_get_num_iommus(void) 302{ 303 return amd_iommus_present; 304} 305 306#ifdef CONFIG_IRQ_REMAP 307static bool check_feature_on_all_iommus(u64 mask) 308{ 309 bool ret = false; 310 struct amd_iommu *iommu; 311 312 for_each_iommu(iommu) { 313 ret = iommu_feature(iommu, mask); 314 if (!ret) 315 return false; 316 } 317 318 return true; 319} 320#endif 321 322/* 323 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 324 * Default to IVHD EFR since it is available sooner 325 * (i.e. before PCI init). 326 */ 327static void __init early_iommu_features_init(struct amd_iommu *iommu, 328 struct ivhd_header *h) 329{ 330 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) 331 iommu->features = h->efr_reg; 332} 333 334/* Access to l1 and l2 indexed register spaces */ 335 336static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 337{ 338 u32 val; 339 340 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 341 pci_read_config_dword(iommu->dev, 0xfc, &val); 342 return val; 343} 344 345static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 346{ 347 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 348 pci_write_config_dword(iommu->dev, 0xfc, val); 349 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 350} 351 352static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 353{ 354 u32 val; 355 356 pci_write_config_dword(iommu->dev, 0xf0, address); 357 pci_read_config_dword(iommu->dev, 0xf4, &val); 358 return val; 359} 360 361static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 362{ 363 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 364 pci_write_config_dword(iommu->dev, 0xf4, val); 365} 366 367/**************************************************************************** 368 * 369 * AMD IOMMU MMIO register space handling functions 370 * 371 * These functions are used to program the IOMMU device registers in 372 * MMIO space required for that driver. 373 * 374 ****************************************************************************/ 375 376/* 377 * This function set the exclusion range in the IOMMU. DMA accesses to the 378 * exclusion range are passed through untranslated 379 */ 380static void iommu_set_exclusion_range(struct amd_iommu *iommu) 381{ 382 u64 start = iommu->exclusion_start & PAGE_MASK; 383 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 384 u64 entry; 385 386 if (!iommu->exclusion_start) 387 return; 388 389 entry = start | MMIO_EXCL_ENABLE_MASK; 390 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 391 &entry, sizeof(entry)); 392 393 entry = limit; 394 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 395 &entry, sizeof(entry)); 396} 397 398static void iommu_set_cwwb_range(struct amd_iommu *iommu) 399{ 400 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 401 u64 entry = start & PM_ADDR_MASK; 402 403 if (!iommu_feature(iommu, FEATURE_SNP)) 404 return; 405 406 /* Note: 407 * Re-purpose Exclusion base/limit registers for Completion wait 408 * write-back base/limit. 409 */ 410 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 411 &entry, sizeof(entry)); 412 413 /* Note: 414 * Default to 4 Kbytes, which can be specified by setting base 415 * address equal to the limit address. 416 */ 417 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 418 &entry, sizeof(entry)); 419} 420 421/* Programs the physical address of the device table into the IOMMU hardware */ 422static void iommu_set_device_table(struct amd_iommu *iommu) 423{ 424 u64 entry; 425 426 BUG_ON(iommu->mmio_base == NULL); 427 428 entry = iommu_virt_to_phys(amd_iommu_dev_table); 429 entry |= (dev_table_size >> 12) - 1; 430 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 431 &entry, sizeof(entry)); 432} 433 434/* Generic functions to enable/disable certain features of the IOMMU. */ 435static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 436{ 437 u64 ctrl; 438 439 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 440 ctrl |= (1ULL << bit); 441 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 442} 443 444static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 445{ 446 u64 ctrl; 447 448 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 449 ctrl &= ~(1ULL << bit); 450 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 451} 452 453static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 454{ 455 u64 ctrl; 456 457 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 458 ctrl &= ~CTRL_INV_TO_MASK; 459 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 460 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 461} 462 463/* Function to enable the hardware */ 464static void iommu_enable(struct amd_iommu *iommu) 465{ 466 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 467} 468 469static void iommu_disable(struct amd_iommu *iommu) 470{ 471 if (!iommu->mmio_base) 472 return; 473 474 /* Disable command buffer */ 475 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 476 477 /* Disable event logging and event interrupts */ 478 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 479 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 480 481 /* Disable IOMMU GA_LOG */ 482 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 483 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 484 485 /* Disable IOMMU hardware itself */ 486 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 487} 488 489/* 490 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 491 * the system has one. 492 */ 493static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 494{ 495 if (!request_mem_region(address, end, "amd_iommu")) { 496 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 497 address, end); 498 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 499 return NULL; 500 } 501 502 return (u8 __iomem *)ioremap(address, end); 503} 504 505static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 506{ 507 if (iommu->mmio_base) 508 iounmap(iommu->mmio_base); 509 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 510} 511 512static inline u32 get_ivhd_header_size(struct ivhd_header *h) 513{ 514 u32 size = 0; 515 516 switch (h->type) { 517 case 0x10: 518 size = 24; 519 break; 520 case 0x11: 521 case 0x40: 522 size = 40; 523 break; 524 } 525 return size; 526} 527 528/**************************************************************************** 529 * 530 * The functions below belong to the first pass of AMD IOMMU ACPI table 531 * parsing. In this pass we try to find out the highest device id this 532 * code has to handle. Upon this information the size of the shared data 533 * structures is determined later. 534 * 535 ****************************************************************************/ 536 537/* 538 * This function calculates the length of a given IVHD entry 539 */ 540static inline int ivhd_entry_length(u8 *ivhd) 541{ 542 u32 type = ((struct ivhd_entry *)ivhd)->type; 543 544 if (type < 0x80) { 545 return 0x04 << (*ivhd >> 6); 546 } else if (type == IVHD_DEV_ACPI_HID) { 547 /* For ACPI_HID, offset 21 is uid len */ 548 return *((u8 *)ivhd + 21) + 22; 549 } 550 return 0; 551} 552 553/* 554 * After reading the highest device id from the IOMMU PCI capability header 555 * this function looks if there is a higher device id defined in the ACPI table 556 */ 557static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 558{ 559 u8 *p = (void *)h, *end = (void *)h; 560 struct ivhd_entry *dev; 561 562 u32 ivhd_size = get_ivhd_header_size(h); 563 564 if (!ivhd_size) { 565 pr_err("Unsupported IVHD type %#x\n", h->type); 566 return -EINVAL; 567 } 568 569 p += ivhd_size; 570 end += h->length; 571 572 while (p < end) { 573 dev = (struct ivhd_entry *)p; 574 switch (dev->type) { 575 case IVHD_DEV_ALL: 576 /* Use maximum BDF value for DEV_ALL */ 577 update_last_devid(0xffff); 578 break; 579 case IVHD_DEV_SELECT: 580 case IVHD_DEV_RANGE_END: 581 case IVHD_DEV_ALIAS: 582 case IVHD_DEV_EXT_SELECT: 583 /* all the above subfield types refer to device ids */ 584 update_last_devid(dev->devid); 585 break; 586 default: 587 break; 588 } 589 p += ivhd_entry_length(p); 590 } 591 592 WARN_ON(p != end); 593 594 return 0; 595} 596 597static int __init check_ivrs_checksum(struct acpi_table_header *table) 598{ 599 int i; 600 u8 checksum = 0, *p = (u8 *)table; 601 602 for (i = 0; i < table->length; ++i) 603 checksum += p[i]; 604 if (checksum != 0) { 605 /* ACPI table corrupt */ 606 pr_err(FW_BUG "IVRS invalid checksum\n"); 607 return -ENODEV; 608 } 609 610 return 0; 611} 612 613/* 614 * Iterate over all IVHD entries in the ACPI table and find the highest device 615 * id which we need to handle. This is the first of three functions which parse 616 * the ACPI table. So we check the checksum here. 617 */ 618static int __init find_last_devid_acpi(struct acpi_table_header *table) 619{ 620 u8 *p = (u8 *)table, *end = (u8 *)table; 621 struct ivhd_header *h; 622 623 p += IVRS_HEADER_LENGTH; 624 625 end += table->length; 626 while (p < end) { 627 h = (struct ivhd_header *)p; 628 if (h->type == amd_iommu_target_ivhd_type) { 629 int ret = find_last_devid_from_ivhd(h); 630 631 if (ret) 632 return ret; 633 } 634 p += h->length; 635 } 636 WARN_ON(p != end); 637 638 return 0; 639} 640 641/**************************************************************************** 642 * 643 * The following functions belong to the code path which parses the ACPI table 644 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 645 * data structures, initialize the device/alias/rlookup table and also 646 * basically initialize the hardware. 647 * 648 ****************************************************************************/ 649 650/* 651 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 652 * write commands to that buffer later and the IOMMU will execute them 653 * asynchronously 654 */ 655static int __init alloc_command_buffer(struct amd_iommu *iommu) 656{ 657 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 658 get_order(CMD_BUFFER_SIZE)); 659 660 return iommu->cmd_buf ? 0 : -ENOMEM; 661} 662 663/* 664 * This function restarts event logging in case the IOMMU experienced 665 * an event log buffer overflow. 666 */ 667void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 668{ 669 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 670 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 671} 672 673/* 674 * This function resets the command buffer if the IOMMU stopped fetching 675 * commands from it. 676 */ 677void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 678{ 679 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 680 681 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 682 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 683 iommu->cmd_buf_head = 0; 684 iommu->cmd_buf_tail = 0; 685 686 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 687} 688 689/* 690 * This function writes the command buffer address to the hardware and 691 * enables it. 692 */ 693static void iommu_enable_command_buffer(struct amd_iommu *iommu) 694{ 695 u64 entry; 696 697 BUG_ON(iommu->cmd_buf == NULL); 698 699 entry = iommu_virt_to_phys(iommu->cmd_buf); 700 entry |= MMIO_CMD_SIZE_512; 701 702 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 703 &entry, sizeof(entry)); 704 705 amd_iommu_reset_cmd_buffer(iommu); 706} 707 708/* 709 * This function disables the command buffer 710 */ 711static void iommu_disable_command_buffer(struct amd_iommu *iommu) 712{ 713 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 714} 715 716static void __init free_command_buffer(struct amd_iommu *iommu) 717{ 718 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 719} 720 721static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 722 gfp_t gfp, size_t size) 723{ 724 int order = get_order(size); 725 void *buf = (void *)__get_free_pages(gfp, order); 726 727 if (buf && 728 iommu_feature(iommu, FEATURE_SNP) && 729 set_memory_4k((unsigned long)buf, (1 << order))) { 730 free_pages((unsigned long)buf, order); 731 buf = NULL; 732 } 733 734 return buf; 735} 736 737/* allocates the memory where the IOMMU will log its events to */ 738static int __init alloc_event_buffer(struct amd_iommu *iommu) 739{ 740 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 741 EVT_BUFFER_SIZE); 742 743 return iommu->evt_buf ? 0 : -ENOMEM; 744} 745 746static void iommu_enable_event_buffer(struct amd_iommu *iommu) 747{ 748 u64 entry; 749 750 BUG_ON(iommu->evt_buf == NULL); 751 752 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 753 754 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 755 &entry, sizeof(entry)); 756 757 /* set head and tail to zero manually */ 758 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 759 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 760 761 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 762} 763 764/* 765 * This function disables the event log buffer 766 */ 767static void iommu_disable_event_buffer(struct amd_iommu *iommu) 768{ 769 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 770} 771 772static void __init free_event_buffer(struct amd_iommu *iommu) 773{ 774 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 775} 776 777/* allocates the memory where the IOMMU will log its events to */ 778static int __init alloc_ppr_log(struct amd_iommu *iommu) 779{ 780 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 781 PPR_LOG_SIZE); 782 783 return iommu->ppr_log ? 0 : -ENOMEM; 784} 785 786static void iommu_enable_ppr_log(struct amd_iommu *iommu) 787{ 788 u64 entry; 789 790 if (iommu->ppr_log == NULL) 791 return; 792 793 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 794 795 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 796 &entry, sizeof(entry)); 797 798 /* set head and tail to zero manually */ 799 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 800 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 801 802 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 803 iommu_feature_enable(iommu, CONTROL_PPR_EN); 804} 805 806static void __init free_ppr_log(struct amd_iommu *iommu) 807{ 808 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 809} 810 811static void free_ga_log(struct amd_iommu *iommu) 812{ 813#ifdef CONFIG_IRQ_REMAP 814 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 815 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 816#endif 817} 818 819static int iommu_ga_log_enable(struct amd_iommu *iommu) 820{ 821#ifdef CONFIG_IRQ_REMAP 822 u32 status, i; 823 u64 entry; 824 825 if (!iommu->ga_log) 826 return -EINVAL; 827 828 /* Check if already running */ 829 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 830 if (WARN_ON(status & (MMIO_STATUS_GALOG_RUN_MASK))) 831 return 0; 832 833 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 834 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 835 &entry, sizeof(entry)); 836 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 837 (BIT_ULL(52)-1)) & ~7ULL; 838 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 839 &entry, sizeof(entry)); 840 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 841 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 842 843 844 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 845 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 846 847 for (i = 0; i < LOOP_TIMEOUT; ++i) { 848 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 849 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 850 break; 851 udelay(10); 852 } 853 854 if (WARN_ON(i >= LOOP_TIMEOUT)) 855 return -EINVAL; 856#endif /* CONFIG_IRQ_REMAP */ 857 return 0; 858} 859 860static int iommu_init_ga_log(struct amd_iommu *iommu) 861{ 862#ifdef CONFIG_IRQ_REMAP 863 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 864 return 0; 865 866 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 867 get_order(GA_LOG_SIZE)); 868 if (!iommu->ga_log) 869 goto err_out; 870 871 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 872 get_order(8)); 873 if (!iommu->ga_log_tail) 874 goto err_out; 875 876 return 0; 877err_out: 878 free_ga_log(iommu); 879 return -EINVAL; 880#else 881 return 0; 882#endif /* CONFIG_IRQ_REMAP */ 883} 884 885static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 886{ 887 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 888 889 return iommu->cmd_sem ? 0 : -ENOMEM; 890} 891 892static void __init free_cwwb_sem(struct amd_iommu *iommu) 893{ 894 if (iommu->cmd_sem) 895 free_page((unsigned long)iommu->cmd_sem); 896} 897 898static void iommu_enable_xt(struct amd_iommu *iommu) 899{ 900#ifdef CONFIG_IRQ_REMAP 901 /* 902 * XT mode (32-bit APIC destination ID) requires 903 * GA mode (128-bit IRTE support) as a prerequisite. 904 */ 905 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 906 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 907 iommu_feature_enable(iommu, CONTROL_XT_EN); 908#endif /* CONFIG_IRQ_REMAP */ 909} 910 911static void iommu_enable_gt(struct amd_iommu *iommu) 912{ 913 if (!iommu_feature(iommu, FEATURE_GT)) 914 return; 915 916 iommu_feature_enable(iommu, CONTROL_GT_EN); 917} 918 919/* sets a specific bit in the device table entry. */ 920static void set_dev_entry_bit(u16 devid, u8 bit) 921{ 922 int i = (bit >> 6) & 0x03; 923 int _bit = bit & 0x3f; 924 925 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); 926} 927 928static int get_dev_entry_bit(u16 devid, u8 bit) 929{ 930 int i = (bit >> 6) & 0x03; 931 int _bit = bit & 0x3f; 932 933 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 934} 935 936 937static bool copy_device_table(void) 938{ 939 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0; 940 struct dev_table_entry *old_devtb = NULL; 941 u32 lo, hi, devid, old_devtb_size; 942 phys_addr_t old_devtb_phys; 943 struct amd_iommu *iommu; 944 u16 dom_id, dte_v, irq_v; 945 gfp_t gfp_flag; 946 u64 tmp; 947 948 if (!amd_iommu_pre_enabled) 949 return false; 950 951 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 952 for_each_iommu(iommu) { 953 /* All IOMMUs should use the same device table with the same size */ 954 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 955 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 956 entry = (((u64) hi) << 32) + lo; 957 if (last_entry && last_entry != entry) { 958 pr_err("IOMMU:%d should use the same dev table as others!\n", 959 iommu->index); 960 return false; 961 } 962 last_entry = entry; 963 964 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 965 if (old_devtb_size != dev_table_size) { 966 pr_err("The device table size of IOMMU:%d is not expected!\n", 967 iommu->index); 968 return false; 969 } 970 } 971 972 /* 973 * When SME is enabled in the first kernel, the entry includes the 974 * memory encryption mask(sme_me_mask), we must remove the memory 975 * encryption mask to obtain the true physical address in kdump kernel. 976 */ 977 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 978 979 if (old_devtb_phys >= 0x100000000ULL) { 980 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 981 return false; 982 } 983 old_devtb = (sme_active() && is_kdump_kernel()) 984 ? (__force void *)ioremap_encrypted(old_devtb_phys, 985 dev_table_size) 986 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB); 987 988 if (!old_devtb) 989 return false; 990 991 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 992 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 993 get_order(dev_table_size)); 994 if (old_dev_tbl_cpy == NULL) { 995 pr_err("Failed to allocate memory for copying old device table!\n"); 996 return false; 997 } 998 999 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 1000 old_dev_tbl_cpy[devid] = old_devtb[devid]; 1001 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1002 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1003 1004 if (dte_v && dom_id) { 1005 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1006 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1007 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 1008 /* If gcr3 table existed, mask it out */ 1009 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1010 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 1011 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1012 old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1013 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 1014 tmp |= DTE_FLAG_GV; 1015 old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1016 } 1017 } 1018 1019 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1020 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1021 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK; 1022 if (irq_v && (int_ctl || int_tab_len)) { 1023 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1024 (int_tab_len != DTE_IRQ_TABLE_LEN)) { 1025 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1026 return false; 1027 } 1028 1029 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1030 } 1031 } 1032 memunmap(old_devtb); 1033 1034 return true; 1035} 1036 1037void amd_iommu_apply_erratum_63(u16 devid) 1038{ 1039 int sysmgt; 1040 1041 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | 1042 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); 1043 1044 if (sysmgt == 0x01) 1045 set_dev_entry_bit(devid, DEV_ENTRY_IW); 1046} 1047 1048/* Writes the specific IOMMU for a device into the rlookup table */ 1049static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1050{ 1051 amd_iommu_rlookup_table[devid] = iommu; 1052} 1053 1054/* 1055 * This function takes the device specific flags read from the ACPI 1056 * table and sets up the device table entry with that information 1057 */ 1058static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1059 u16 devid, u32 flags, u32 ext_flags) 1060{ 1061 if (flags & ACPI_DEVFLAG_INITPASS) 1062 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); 1063 if (flags & ACPI_DEVFLAG_EXTINT) 1064 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); 1065 if (flags & ACPI_DEVFLAG_NMI) 1066 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); 1067 if (flags & ACPI_DEVFLAG_SYSMGT1) 1068 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); 1069 if (flags & ACPI_DEVFLAG_SYSMGT2) 1070 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); 1071 if (flags & ACPI_DEVFLAG_LINT0) 1072 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); 1073 if (flags & ACPI_DEVFLAG_LINT1) 1074 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 1075 1076 amd_iommu_apply_erratum_63(devid); 1077 1078 set_iommu_for_device(iommu, devid); 1079} 1080 1081int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1082{ 1083 struct devid_map *entry; 1084 struct list_head *list; 1085 1086 if (type == IVHD_SPECIAL_IOAPIC) 1087 list = &ioapic_map; 1088 else if (type == IVHD_SPECIAL_HPET) 1089 list = &hpet_map; 1090 else 1091 return -EINVAL; 1092 1093 list_for_each_entry(entry, list, list) { 1094 if (!(entry->id == id && entry->cmd_line)) 1095 continue; 1096 1097 pr_info("Command-line override present for %s id %d - ignoring\n", 1098 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1099 1100 *devid = entry->devid; 1101 1102 return 0; 1103 } 1104 1105 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1106 if (!entry) 1107 return -ENOMEM; 1108 1109 entry->id = id; 1110 entry->devid = *devid; 1111 entry->cmd_line = cmd_line; 1112 1113 list_add_tail(&entry->list, list); 1114 1115 return 0; 1116} 1117 1118static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1119 bool cmd_line) 1120{ 1121 struct acpihid_map_entry *entry; 1122 struct list_head *list = &acpihid_map; 1123 1124 list_for_each_entry(entry, list, list) { 1125 if (strcmp(entry->hid, hid) || 1126 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1127 !entry->cmd_line) 1128 continue; 1129 1130 pr_info("Command-line override for hid:%s uid:%s\n", 1131 hid, uid); 1132 *devid = entry->devid; 1133 return 0; 1134 } 1135 1136 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1137 if (!entry) 1138 return -ENOMEM; 1139 1140 memcpy(entry->uid, uid, strlen(uid)); 1141 memcpy(entry->hid, hid, strlen(hid)); 1142 entry->devid = *devid; 1143 entry->cmd_line = cmd_line; 1144 entry->root_devid = (entry->devid & (~0x7)); 1145 1146 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1147 entry->cmd_line ? "cmd" : "ivrs", 1148 entry->hid, entry->uid, entry->root_devid); 1149 1150 list_add_tail(&entry->list, list); 1151 return 0; 1152} 1153 1154static int __init add_early_maps(void) 1155{ 1156 int i, ret; 1157 1158 for (i = 0; i < early_ioapic_map_size; ++i) { 1159 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1160 early_ioapic_map[i].id, 1161 &early_ioapic_map[i].devid, 1162 early_ioapic_map[i].cmd_line); 1163 if (ret) 1164 return ret; 1165 } 1166 1167 for (i = 0; i < early_hpet_map_size; ++i) { 1168 ret = add_special_device(IVHD_SPECIAL_HPET, 1169 early_hpet_map[i].id, 1170 &early_hpet_map[i].devid, 1171 early_hpet_map[i].cmd_line); 1172 if (ret) 1173 return ret; 1174 } 1175 1176 for (i = 0; i < early_acpihid_map_size; ++i) { 1177 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1178 early_acpihid_map[i].uid, 1179 &early_acpihid_map[i].devid, 1180 early_acpihid_map[i].cmd_line); 1181 if (ret) 1182 return ret; 1183 } 1184 1185 return 0; 1186} 1187 1188/* 1189 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1190 * initializes the hardware and our data structures with it. 1191 */ 1192static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1193 struct ivhd_header *h) 1194{ 1195 u8 *p = (u8 *)h; 1196 u8 *end = p, flags = 0; 1197 u16 devid = 0, devid_start = 0, devid_to = 0; 1198 u32 dev_i, ext_flags = 0; 1199 bool alias = false; 1200 struct ivhd_entry *e; 1201 u32 ivhd_size; 1202 int ret; 1203 1204 1205 ret = add_early_maps(); 1206 if (ret) 1207 return ret; 1208 1209 amd_iommu_apply_ivrs_quirks(); 1210 1211 /* 1212 * First save the recommended feature enable bits from ACPI 1213 */ 1214 iommu->acpi_flags = h->flags; 1215 1216 /* 1217 * Done. Now parse the device entries 1218 */ 1219 ivhd_size = get_ivhd_header_size(h); 1220 if (!ivhd_size) { 1221 pr_err("Unsupported IVHD type %#x\n", h->type); 1222 return -EINVAL; 1223 } 1224 1225 p += ivhd_size; 1226 1227 end += h->length; 1228 1229 1230 while (p < end) { 1231 e = (struct ivhd_entry *)p; 1232 switch (e->type) { 1233 case IVHD_DEV_ALL: 1234 1235 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1236 1237 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1238 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1239 break; 1240 case IVHD_DEV_SELECT: 1241 1242 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1243 "flags: %02x\n", 1244 PCI_BUS_NUM(e->devid), 1245 PCI_SLOT(e->devid), 1246 PCI_FUNC(e->devid), 1247 e->flags); 1248 1249 devid = e->devid; 1250 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1251 break; 1252 case IVHD_DEV_SELECT_RANGE_START: 1253 1254 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1255 "devid: %02x:%02x.%x flags: %02x\n", 1256 PCI_BUS_NUM(e->devid), 1257 PCI_SLOT(e->devid), 1258 PCI_FUNC(e->devid), 1259 e->flags); 1260 1261 devid_start = e->devid; 1262 flags = e->flags; 1263 ext_flags = 0; 1264 alias = false; 1265 break; 1266 case IVHD_DEV_ALIAS: 1267 1268 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1269 "flags: %02x devid_to: %02x:%02x.%x\n", 1270 PCI_BUS_NUM(e->devid), 1271 PCI_SLOT(e->devid), 1272 PCI_FUNC(e->devid), 1273 e->flags, 1274 PCI_BUS_NUM(e->ext >> 8), 1275 PCI_SLOT(e->ext >> 8), 1276 PCI_FUNC(e->ext >> 8)); 1277 1278 devid = e->devid; 1279 devid_to = e->ext >> 8; 1280 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1281 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1282 amd_iommu_alias_table[devid] = devid_to; 1283 break; 1284 case IVHD_DEV_ALIAS_RANGE: 1285 1286 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1287 "devid: %02x:%02x.%x flags: %02x " 1288 "devid_to: %02x:%02x.%x\n", 1289 PCI_BUS_NUM(e->devid), 1290 PCI_SLOT(e->devid), 1291 PCI_FUNC(e->devid), 1292 e->flags, 1293 PCI_BUS_NUM(e->ext >> 8), 1294 PCI_SLOT(e->ext >> 8), 1295 PCI_FUNC(e->ext >> 8)); 1296 1297 devid_start = e->devid; 1298 flags = e->flags; 1299 devid_to = e->ext >> 8; 1300 ext_flags = 0; 1301 alias = true; 1302 break; 1303 case IVHD_DEV_EXT_SELECT: 1304 1305 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1306 "flags: %02x ext: %08x\n", 1307 PCI_BUS_NUM(e->devid), 1308 PCI_SLOT(e->devid), 1309 PCI_FUNC(e->devid), 1310 e->flags, e->ext); 1311 1312 devid = e->devid; 1313 set_dev_entry_from_acpi(iommu, devid, e->flags, 1314 e->ext); 1315 break; 1316 case IVHD_DEV_EXT_SELECT_RANGE: 1317 1318 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1319 "%02x:%02x.%x flags: %02x ext: %08x\n", 1320 PCI_BUS_NUM(e->devid), 1321 PCI_SLOT(e->devid), 1322 PCI_FUNC(e->devid), 1323 e->flags, e->ext); 1324 1325 devid_start = e->devid; 1326 flags = e->flags; 1327 ext_flags = e->ext; 1328 alias = false; 1329 break; 1330 case IVHD_DEV_RANGE_END: 1331 1332 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1333 PCI_BUS_NUM(e->devid), 1334 PCI_SLOT(e->devid), 1335 PCI_FUNC(e->devid)); 1336 1337 devid = e->devid; 1338 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1339 if (alias) { 1340 amd_iommu_alias_table[dev_i] = devid_to; 1341 set_dev_entry_from_acpi(iommu, 1342 devid_to, flags, ext_flags); 1343 } 1344 set_dev_entry_from_acpi(iommu, dev_i, 1345 flags, ext_flags); 1346 } 1347 break; 1348 case IVHD_DEV_SPECIAL: { 1349 u8 handle, type; 1350 const char *var; 1351 u16 devid; 1352 int ret; 1353 1354 handle = e->ext & 0xff; 1355 devid = (e->ext >> 8) & 0xffff; 1356 type = (e->ext >> 24) & 0xff; 1357 1358 if (type == IVHD_SPECIAL_IOAPIC) 1359 var = "IOAPIC"; 1360 else if (type == IVHD_SPECIAL_HPET) 1361 var = "HPET"; 1362 else 1363 var = "UNKNOWN"; 1364 1365 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1366 var, (int)handle, 1367 PCI_BUS_NUM(devid), 1368 PCI_SLOT(devid), 1369 PCI_FUNC(devid)); 1370 1371 ret = add_special_device(type, handle, &devid, false); 1372 if (ret) 1373 return ret; 1374 1375 /* 1376 * add_special_device might update the devid in case a 1377 * command-line override is present. So call 1378 * set_dev_entry_from_acpi after add_special_device. 1379 */ 1380 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1381 1382 break; 1383 } 1384 case IVHD_DEV_ACPI_HID: { 1385 u16 devid; 1386 u8 hid[ACPIHID_HID_LEN]; 1387 u8 uid[ACPIHID_UID_LEN]; 1388 int ret; 1389 1390 if (h->type != 0x40) { 1391 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1392 e->type); 1393 break; 1394 } 1395 1396 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1); 1397 hid[ACPIHID_HID_LEN - 1] = '\0'; 1398 1399 if (!(*hid)) { 1400 pr_err(FW_BUG "Invalid HID.\n"); 1401 break; 1402 } 1403 1404 uid[0] = '\0'; 1405 switch (e->uidf) { 1406 case UID_NOT_PRESENT: 1407 1408 if (e->uidl != 0) 1409 pr_warn(FW_BUG "Invalid UID length.\n"); 1410 1411 break; 1412 case UID_IS_INTEGER: 1413 1414 sprintf(uid, "%d", e->uid); 1415 1416 break; 1417 case UID_IS_CHARACTER: 1418 1419 memcpy(uid, &e->uid, e->uidl); 1420 uid[e->uidl] = '\0'; 1421 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 devid = e->devid; 1428 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1429 hid, uid, 1430 PCI_BUS_NUM(devid), 1431 PCI_SLOT(devid), 1432 PCI_FUNC(devid)); 1433 1434 flags = e->flags; 1435 1436 ret = add_acpi_hid_device(hid, uid, &devid, false); 1437 if (ret) 1438 return ret; 1439 1440 /* 1441 * add_special_device might update the devid in case a 1442 * command-line override is present. So call 1443 * set_dev_entry_from_acpi after add_special_device. 1444 */ 1445 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1446 1447 break; 1448 } 1449 default: 1450 break; 1451 } 1452 1453 p += ivhd_entry_length(p); 1454 } 1455 1456 return 0; 1457} 1458 1459static void __init free_iommu_one(struct amd_iommu *iommu) 1460{ 1461 free_cwwb_sem(iommu); 1462 free_command_buffer(iommu); 1463 free_event_buffer(iommu); 1464 free_ppr_log(iommu); 1465 free_ga_log(iommu); 1466 iommu_unmap_mmio_space(iommu); 1467} 1468 1469static void __init free_iommu_all(void) 1470{ 1471 struct amd_iommu *iommu, *next; 1472 1473 for_each_iommu_safe(iommu, next) { 1474 list_del(&iommu->list); 1475 free_iommu_one(iommu); 1476 kfree(iommu); 1477 } 1478} 1479 1480/* 1481 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1482 * Workaround: 1483 * BIOS should disable L2B micellaneous clock gating by setting 1484 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1485 */ 1486static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1487{ 1488 u32 value; 1489 1490 if ((boot_cpu_data.x86 != 0x15) || 1491 (boot_cpu_data.x86_model < 0x10) || 1492 (boot_cpu_data.x86_model > 0x1f)) 1493 return; 1494 1495 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1496 pci_read_config_dword(iommu->dev, 0xf4, &value); 1497 1498 if (value & BIT(2)) 1499 return; 1500 1501 /* Select NB indirect register 0x90 and enable writing */ 1502 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1503 1504 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1505 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1506 1507 /* Clear the enable writing bit */ 1508 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1509} 1510 1511/* 1512 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1513 * Workaround: 1514 * BIOS should enable ATS write permission check by setting 1515 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1516 */ 1517static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1518{ 1519 u32 value; 1520 1521 if ((boot_cpu_data.x86 != 0x15) || 1522 (boot_cpu_data.x86_model < 0x30) || 1523 (boot_cpu_data.x86_model > 0x3f)) 1524 return; 1525 1526 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1527 value = iommu_read_l2(iommu, 0x47); 1528 1529 if (value & BIT(0)) 1530 return; 1531 1532 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1533 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1534 1535 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1536} 1537 1538/* 1539 * This function clues the initialization function for one IOMMU 1540 * together and also allocates the command buffer and programs the 1541 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1542 */ 1543static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) 1544{ 1545 int ret; 1546 1547 raw_spin_lock_init(&iommu->lock); 1548 iommu->cmd_sem_val = 0; 1549 1550 /* Add IOMMU to internal data structures */ 1551 list_add_tail(&iommu->list, &amd_iommu_list); 1552 iommu->index = amd_iommus_present++; 1553 1554 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1555 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1556 return -ENOSYS; 1557 } 1558 1559 /* Index is fine - add IOMMU to the array */ 1560 amd_iommus[iommu->index] = iommu; 1561 1562 /* 1563 * Copy data from ACPI table entry to the iommu struct 1564 */ 1565 iommu->devid = h->devid; 1566 iommu->cap_ptr = h->cap_ptr; 1567 iommu->pci_seg = h->pci_seg; 1568 iommu->mmio_phys = h->mmio_phys; 1569 1570 switch (h->type) { 1571 case 0x10: 1572 /* Check if IVHD EFR contains proper max banks/counters */ 1573 if ((h->efr_attr != 0) && 1574 ((h->efr_attr & (0xF << 13)) != 0) && 1575 ((h->efr_attr & (0x3F << 17)) != 0)) 1576 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1577 else 1578 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1579 1580 /* 1581 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1582 * GAM also requires GA mode. Therefore, we need to 1583 * check cmpxchg16b support before enabling it. 1584 */ 1585 if (!boot_cpu_has(X86_FEATURE_CX16) || 1586 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1587 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1588 break; 1589 case 0x11: 1590 case 0x40: 1591 if (h->efr_reg & (1 << 9)) 1592 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1593 else 1594 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1595 1596 /* 1597 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1598 * XT, GAM also requires GA mode. Therefore, we need to 1599 * check cmpxchg16b support before enabling them. 1600 */ 1601 if (!boot_cpu_has(X86_FEATURE_CX16) || 1602 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1603 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1604 break; 1605 } 1606 1607 /* 1608 * Note: Since iommu_update_intcapxt() leverages 1609 * the IOMMU MMIO access to MSI capability block registers 1610 * for MSI address lo/hi/data, we need to check both 1611 * EFR[XtSup] and EFR[MsiCapMmioSup] for x2APIC support. 1612 */ 1613 if ((h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) && 1614 (h->efr_reg & BIT(IOMMU_EFR_MSICAPMMIOSUP_SHIFT))) 1615 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1616 1617 early_iommu_features_init(iommu, h); 1618 1619 break; 1620 default: 1621 return -EINVAL; 1622 } 1623 1624 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1625 iommu->mmio_phys_end); 1626 if (!iommu->mmio_base) 1627 return -ENOMEM; 1628 1629 if (alloc_cwwb_sem(iommu)) 1630 return -ENOMEM; 1631 1632 if (alloc_command_buffer(iommu)) 1633 return -ENOMEM; 1634 1635 if (alloc_event_buffer(iommu)) 1636 return -ENOMEM; 1637 1638 iommu->int_enabled = false; 1639 1640 init_translation_status(iommu); 1641 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1642 iommu_disable(iommu); 1643 clear_translation_pre_enabled(iommu); 1644 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1645 iommu->index); 1646 } 1647 if (amd_iommu_pre_enabled) 1648 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1649 1650 ret = init_iommu_from_acpi(iommu, h); 1651 if (ret) 1652 return ret; 1653 1654 ret = amd_iommu_create_irq_domain(iommu); 1655 if (ret) 1656 return ret; 1657 1658 /* 1659 * Make sure IOMMU is not considered to translate itself. The IVRS 1660 * table tells us so, but this is a lie! 1661 */ 1662 amd_iommu_rlookup_table[iommu->devid] = NULL; 1663 1664 return 0; 1665} 1666 1667/** 1668 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1669 * @ivrs: Pointer to the IVRS header 1670 * 1671 * This function search through all IVDB of the maximum supported IVHD 1672 */ 1673static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1674{ 1675 u8 *base = (u8 *)ivrs; 1676 struct ivhd_header *ivhd = (struct ivhd_header *) 1677 (base + IVRS_HEADER_LENGTH); 1678 u8 last_type = ivhd->type; 1679 u16 devid = ivhd->devid; 1680 1681 while (((u8 *)ivhd - base < ivrs->length) && 1682 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1683 u8 *p = (u8 *) ivhd; 1684 1685 if (ivhd->devid == devid) 1686 last_type = ivhd->type; 1687 ivhd = (struct ivhd_header *)(p + ivhd->length); 1688 } 1689 1690 return last_type; 1691} 1692 1693/* 1694 * Iterates over all IOMMU entries in the ACPI table, allocates the 1695 * IOMMU structure and initializes it with init_iommu_one() 1696 */ 1697static int __init init_iommu_all(struct acpi_table_header *table) 1698{ 1699 u8 *p = (u8 *)table, *end = (u8 *)table; 1700 struct ivhd_header *h; 1701 struct amd_iommu *iommu; 1702 int ret; 1703 1704 end += table->length; 1705 p += IVRS_HEADER_LENGTH; 1706 1707 while (p < end) { 1708 h = (struct ivhd_header *)p; 1709 if (*p == amd_iommu_target_ivhd_type) { 1710 1711 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1712 "seg: %d flags: %01x info %04x\n", 1713 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1714 PCI_FUNC(h->devid), h->cap_ptr, 1715 h->pci_seg, h->flags, h->info); 1716 DUMP_printk(" mmio-addr: %016llx\n", 1717 h->mmio_phys); 1718 1719 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1720 if (iommu == NULL) 1721 return -ENOMEM; 1722 1723 ret = init_iommu_one(iommu, h); 1724 if (ret) 1725 return ret; 1726 } 1727 p += h->length; 1728 1729 } 1730 WARN_ON(p != end); 1731 1732 return 0; 1733} 1734 1735static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1736{ 1737 u64 val; 1738 struct pci_dev *pdev = iommu->dev; 1739 1740 if (!iommu_feature(iommu, FEATURE_PC)) 1741 return; 1742 1743 amd_iommu_pc_present = true; 1744 1745 pci_info(pdev, "IOMMU performance counters supported\n"); 1746 1747 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1748 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1749 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1750 1751 return; 1752} 1753 1754static ssize_t amd_iommu_show_cap(struct device *dev, 1755 struct device_attribute *attr, 1756 char *buf) 1757{ 1758 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1759 return sprintf(buf, "%x\n", iommu->cap); 1760} 1761static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1762 1763static ssize_t amd_iommu_show_features(struct device *dev, 1764 struct device_attribute *attr, 1765 char *buf) 1766{ 1767 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1768 return sprintf(buf, "%llx\n", iommu->features); 1769} 1770static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1771 1772static struct attribute *amd_iommu_attrs[] = { 1773 &dev_attr_cap.attr, 1774 &dev_attr_features.attr, 1775 NULL, 1776}; 1777 1778static struct attribute_group amd_iommu_group = { 1779 .name = "amd-iommu", 1780 .attrs = amd_iommu_attrs, 1781}; 1782 1783static const struct attribute_group *amd_iommu_groups[] = { 1784 &amd_iommu_group, 1785 NULL, 1786}; 1787 1788/* 1789 * Note: IVHD 0x11 and 0x40 also contains exact copy 1790 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1791 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1792 */ 1793static void __init late_iommu_features_init(struct amd_iommu *iommu) 1794{ 1795 u64 features; 1796 1797 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1798 return; 1799 1800 /* read extended feature bits */ 1801 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1802 1803 if (!iommu->features) { 1804 iommu->features = features; 1805 return; 1806 } 1807 1808 /* 1809 * Sanity check and warn if EFR values from 1810 * IVHD and MMIO conflict. 1811 */ 1812 if (features != iommu->features) 1813 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n", 1814 features, iommu->features); 1815} 1816 1817static int __init iommu_init_pci(struct amd_iommu *iommu) 1818{ 1819 int cap_ptr = iommu->cap_ptr; 1820 int ret; 1821 1822 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1823 iommu->devid & 0xff); 1824 if (!iommu->dev) 1825 return -ENODEV; 1826 1827 /* Prevent binding other PCI device drivers to IOMMU devices */ 1828 iommu->dev->match_driver = false; 1829 1830 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 1831 &iommu->cap); 1832 1833 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 1834 amd_iommu_iotlb_sup = false; 1835 1836 late_iommu_features_init(iommu); 1837 1838 if (iommu_feature(iommu, FEATURE_GT)) { 1839 int glxval; 1840 u32 max_pasid; 1841 u64 pasmax; 1842 1843 pasmax = iommu->features & FEATURE_PASID_MASK; 1844 pasmax >>= FEATURE_PASID_SHIFT; 1845 max_pasid = (1 << (pasmax + 1)) - 1; 1846 1847 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 1848 1849 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 1850 1851 glxval = iommu->features & FEATURE_GLXVAL_MASK; 1852 glxval >>= FEATURE_GLXVAL_SHIFT; 1853 1854 if (amd_iommu_max_glx_val == -1) 1855 amd_iommu_max_glx_val = glxval; 1856 else 1857 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 1858 } 1859 1860 if (iommu_feature(iommu, FEATURE_GT) && 1861 iommu_feature(iommu, FEATURE_PPR)) { 1862 iommu->is_iommu_v2 = true; 1863 amd_iommu_v2_present = true; 1864 } 1865 1866 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 1867 return -ENOMEM; 1868 1869 ret = iommu_init_ga_log(iommu); 1870 if (ret) 1871 return ret; 1872 1873 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) 1874 amd_iommu_np_cache = true; 1875 1876 init_iommu_perf_ctr(iommu); 1877 1878 if (is_rd890_iommu(iommu->dev)) { 1879 int i, j; 1880 1881 iommu->root_pdev = 1882 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 1883 PCI_DEVFN(0, 0)); 1884 1885 /* 1886 * Some rd890 systems may not be fully reconfigured by the 1887 * BIOS, so it's necessary for us to store this information so 1888 * it can be reprogrammed on resume 1889 */ 1890 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 1891 &iommu->stored_addr_lo); 1892 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 1893 &iommu->stored_addr_hi); 1894 1895 /* Low bit locks writes to configuration space */ 1896 iommu->stored_addr_lo &= ~1; 1897 1898 for (i = 0; i < 6; i++) 1899 for (j = 0; j < 0x12; j++) 1900 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 1901 1902 for (i = 0; i < 0x83; i++) 1903 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 1904 } 1905 1906 amd_iommu_erratum_746_workaround(iommu); 1907 amd_iommu_ats_write_check_workaround(iommu); 1908 1909 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 1910 amd_iommu_groups, "ivhd%d", iommu->index); 1911 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops); 1912 iommu_device_register(&iommu->iommu); 1913 1914 return pci_enable_device(iommu->dev); 1915} 1916 1917static void print_iommu_info(void) 1918{ 1919 static const char * const feat_str[] = { 1920 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 1921 "IA", "GA", "HE", "PC" 1922 }; 1923 struct amd_iommu *iommu; 1924 1925 for_each_iommu(iommu) { 1926 struct pci_dev *pdev = iommu->dev; 1927 int i; 1928 1929 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); 1930 1931 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 1932 pr_info("Extended features (%#llx):", iommu->features); 1933 1934 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 1935 if (iommu_feature(iommu, (1ULL << i))) 1936 pr_cont(" %s", feat_str[i]); 1937 } 1938 1939 if (iommu->features & FEATURE_GAM_VAPIC) 1940 pr_cont(" GA_vAPIC"); 1941 1942 pr_cont("\n"); 1943 } 1944 } 1945 if (irq_remapping_enabled) { 1946 pr_info("Interrupt remapping enabled\n"); 1947 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 1948 pr_info("Virtual APIC enabled\n"); 1949 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 1950 pr_info("X2APIC enabled\n"); 1951 } 1952} 1953 1954static int __init amd_iommu_init_pci(void) 1955{ 1956 struct amd_iommu *iommu; 1957 int ret = 0; 1958 1959 for_each_iommu(iommu) { 1960 ret = iommu_init_pci(iommu); 1961 if (ret) 1962 break; 1963 1964 /* Need to setup range after PCI init */ 1965 iommu_set_cwwb_range(iommu); 1966 } 1967 1968 /* 1969 * Order is important here to make sure any unity map requirements are 1970 * fulfilled. The unity mappings are created and written to the device 1971 * table during the amd_iommu_init_api() call. 1972 * 1973 * After that we call init_device_table_dma() to make sure any 1974 * uninitialized DTE will block DMA, and in the end we flush the caches 1975 * of all IOMMUs to make sure the changes to the device table are 1976 * active. 1977 */ 1978 ret = amd_iommu_init_api(); 1979 1980 init_device_table_dma(); 1981 1982 for_each_iommu(iommu) 1983 iommu_flush_all_caches(iommu); 1984 1985 if (!ret) 1986 print_iommu_info(); 1987 1988 return ret; 1989} 1990 1991/**************************************************************************** 1992 * 1993 * The following functions initialize the MSI interrupts for all IOMMUs 1994 * in the system. It's a bit challenging because there could be multiple 1995 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 1996 * pci_dev. 1997 * 1998 ****************************************************************************/ 1999 2000static int iommu_setup_msi(struct amd_iommu *iommu) 2001{ 2002 int r; 2003 2004 r = pci_enable_msi(iommu->dev); 2005 if (r) 2006 return r; 2007 2008 r = request_threaded_irq(iommu->dev->irq, 2009 amd_iommu_int_handler, 2010 amd_iommu_int_thread, 2011 0, "AMD-Vi", 2012 iommu); 2013 2014 if (r) { 2015 pci_disable_msi(iommu->dev); 2016 return r; 2017 } 2018 2019 iommu->int_enabled = true; 2020 2021 return 0; 2022} 2023 2024#define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2) 2025#define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8) 2026#define XT_INT_VEC(x) (((x) & 0xFFULL) << 32) 2027#define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56) 2028 2029/* 2030 * Setup the IntCapXT registers with interrupt routing information 2031 * based on the PCI MSI capability block registers, accessed via 2032 * MMIO MSI address low/hi and MSI data registers. 2033 */ 2034static void iommu_update_intcapxt(struct amd_iommu *iommu) 2035{ 2036 u64 val; 2037 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); 2038 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET); 2039 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET); 2040 bool dm = (addr_lo >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 2041 u32 dest = ((addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xFF); 2042 2043 if (x2apic_enabled()) 2044 dest |= MSI_ADDR_EXT_DEST_ID(addr_hi); 2045 2046 val = XT_INT_VEC(data & 0xFF) | 2047 XT_INT_DEST_MODE(dm) | 2048 XT_INT_DEST_LO(dest) | 2049 XT_INT_DEST_HI(dest); 2050 2051 /** 2052 * Current IOMMU implemtation uses the same IRQ for all 2053 * 3 IOMMU interrupts. 2054 */ 2055 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2056 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2057 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2058} 2059 2060static void _irq_notifier_notify(struct irq_affinity_notify *notify, 2061 const cpumask_t *mask) 2062{ 2063 struct amd_iommu *iommu; 2064 2065 for_each_iommu(iommu) { 2066 if (iommu->dev->irq == notify->irq) { 2067 iommu_update_intcapxt(iommu); 2068 break; 2069 } 2070 } 2071} 2072 2073static void _irq_notifier_release(struct kref *ref) 2074{ 2075} 2076 2077static int iommu_init_intcapxt(struct amd_iommu *iommu) 2078{ 2079 int ret; 2080 struct irq_affinity_notify *notify = &iommu->intcapxt_notify; 2081 2082 /** 2083 * IntCapXT requires XTSup=1 and MsiCapMmioSup=1, 2084 * which can be inferred from amd_iommu_xt_mode. 2085 */ 2086 if (amd_iommu_xt_mode != IRQ_REMAP_X2APIC_MODE) 2087 return 0; 2088 2089 /** 2090 * Also, we need to setup notifier to update the IntCapXT registers 2091 * whenever the irq affinity is changed from user-space. 2092 */ 2093 notify->irq = iommu->dev->irq; 2094 notify->notify = _irq_notifier_notify, 2095 notify->release = _irq_notifier_release, 2096 ret = irq_set_affinity_notifier(iommu->dev->irq, notify); 2097 if (ret) { 2098 pr_err("Failed to register irq affinity notifier (devid=%#x, irq %d)\n", 2099 iommu->devid, iommu->dev->irq); 2100 return ret; 2101 } 2102 2103 iommu_update_intcapxt(iommu); 2104 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2105 return ret; 2106} 2107 2108static int iommu_init_msi(struct amd_iommu *iommu) 2109{ 2110 int ret; 2111 2112 if (iommu->int_enabled) 2113 goto enable_faults; 2114 2115 if (iommu->dev->msi_cap) 2116 ret = iommu_setup_msi(iommu); 2117 else 2118 ret = -ENODEV; 2119 2120 if (ret) 2121 return ret; 2122 2123enable_faults: 2124 ret = iommu_init_intcapxt(iommu); 2125 if (ret) 2126 return ret; 2127 2128 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2129 2130 if (iommu->ppr_log != NULL) 2131 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2132 2133 iommu_ga_log_enable(iommu); 2134 2135 return 0; 2136} 2137 2138/**************************************************************************** 2139 * 2140 * The next functions belong to the third pass of parsing the ACPI 2141 * table. In this last pass the memory mapping requirements are 2142 * gathered (like exclusion and unity mapping ranges). 2143 * 2144 ****************************************************************************/ 2145 2146static void __init free_unity_maps(void) 2147{ 2148 struct unity_map_entry *entry, *next; 2149 2150 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { 2151 list_del(&entry->list); 2152 kfree(entry); 2153 } 2154} 2155 2156/* called for unity map ACPI definition */ 2157static int __init init_unity_map_range(struct ivmd_header *m) 2158{ 2159 struct unity_map_entry *e = NULL; 2160 char *s; 2161 2162 e = kzalloc(sizeof(*e), GFP_KERNEL); 2163 if (e == NULL) 2164 return -ENOMEM; 2165 2166 switch (m->type) { 2167 default: 2168 kfree(e); 2169 return 0; 2170 case ACPI_IVMD_TYPE: 2171 s = "IVMD_TYPEi\t\t\t"; 2172 e->devid_start = e->devid_end = m->devid; 2173 break; 2174 case ACPI_IVMD_TYPE_ALL: 2175 s = "IVMD_TYPE_ALL\t\t"; 2176 e->devid_start = 0; 2177 e->devid_end = amd_iommu_last_bdf; 2178 break; 2179 case ACPI_IVMD_TYPE_RANGE: 2180 s = "IVMD_TYPE_RANGE\t\t"; 2181 e->devid_start = m->devid; 2182 e->devid_end = m->aux; 2183 break; 2184 } 2185 e->address_start = PAGE_ALIGN(m->range_start); 2186 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2187 e->prot = m->flags >> 1; 2188 2189 /* 2190 * Treat per-device exclusion ranges as r/w unity-mapped regions 2191 * since some buggy BIOSes might lead to the overwritten exclusion 2192 * range (exclusion_start and exclusion_length members). This 2193 * happens when there are multiple exclusion ranges (IVMD entries) 2194 * defined in ACPI table. 2195 */ 2196 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2197 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2198 2199 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" 2200 " range_start: %016llx range_end: %016llx flags: %x\n", s, 2201 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2202 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end), 2203 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2204 e->address_start, e->address_end, m->flags); 2205 2206 list_add_tail(&e->list, &amd_iommu_unity_map); 2207 2208 return 0; 2209} 2210 2211/* iterates over all memory definitions we find in the ACPI table */ 2212static int __init init_memory_definitions(struct acpi_table_header *table) 2213{ 2214 u8 *p = (u8 *)table, *end = (u8 *)table; 2215 struct ivmd_header *m; 2216 2217 end += table->length; 2218 p += IVRS_HEADER_LENGTH; 2219 2220 while (p < end) { 2221 m = (struct ivmd_header *)p; 2222 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2223 init_unity_map_range(m); 2224 2225 p += m->length; 2226 } 2227 2228 return 0; 2229} 2230 2231/* 2232 * Init the device table to not allow DMA access for devices 2233 */ 2234static void init_device_table_dma(void) 2235{ 2236 u32 devid; 2237 2238 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2239 set_dev_entry_bit(devid, DEV_ENTRY_VALID); 2240 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); 2241 } 2242} 2243 2244static void __init uninit_device_table_dma(void) 2245{ 2246 u32 devid; 2247 2248 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2249 amd_iommu_dev_table[devid].data[0] = 0ULL; 2250 amd_iommu_dev_table[devid].data[1] = 0ULL; 2251 } 2252} 2253 2254static void init_device_table(void) 2255{ 2256 u32 devid; 2257 2258 if (!amd_iommu_irq_remap) 2259 return; 2260 2261 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2262 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); 2263} 2264 2265static void iommu_init_flags(struct amd_iommu *iommu) 2266{ 2267 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2268 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2269 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2270 2271 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2272 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2273 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2274 2275 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2276 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2277 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2278 2279 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2280 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2281 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2282 2283 /* 2284 * make IOMMU memory accesses cache coherent 2285 */ 2286 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2287 2288 /* Set IOTLB invalidation timeout to 1s */ 2289 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2290} 2291 2292static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2293{ 2294 int i, j; 2295 u32 ioc_feature_control; 2296 struct pci_dev *pdev = iommu->root_pdev; 2297 2298 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2299 if (!is_rd890_iommu(iommu->dev) || !pdev) 2300 return; 2301 2302 /* 2303 * First, we need to ensure that the iommu is enabled. This is 2304 * controlled by a register in the northbridge 2305 */ 2306 2307 /* Select Northbridge indirect register 0x75 and enable writing */ 2308 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2309 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2310 2311 /* Enable the iommu */ 2312 if (!(ioc_feature_control & 0x1)) 2313 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2314 2315 /* Restore the iommu BAR */ 2316 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2317 iommu->stored_addr_lo); 2318 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2319 iommu->stored_addr_hi); 2320 2321 /* Restore the l1 indirect regs for each of the 6 l1s */ 2322 for (i = 0; i < 6; i++) 2323 for (j = 0; j < 0x12; j++) 2324 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2325 2326 /* Restore the l2 indirect regs */ 2327 for (i = 0; i < 0x83; i++) 2328 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2329 2330 /* Lock PCI setup registers */ 2331 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2332 iommu->stored_addr_lo | 1); 2333} 2334 2335static void iommu_enable_ga(struct amd_iommu *iommu) 2336{ 2337#ifdef CONFIG_IRQ_REMAP 2338 switch (amd_iommu_guest_ir) { 2339 case AMD_IOMMU_GUEST_IR_VAPIC: 2340 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2341 fallthrough; 2342 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2343 iommu_feature_enable(iommu, CONTROL_GA_EN); 2344 iommu->irte_ops = &irte_128_ops; 2345 break; 2346 default: 2347 iommu->irte_ops = &irte_32_ops; 2348 break; 2349 } 2350#endif 2351} 2352 2353static void early_enable_iommu(struct amd_iommu *iommu) 2354{ 2355 iommu_disable(iommu); 2356 iommu_init_flags(iommu); 2357 iommu_set_device_table(iommu); 2358 iommu_enable_command_buffer(iommu); 2359 iommu_enable_event_buffer(iommu); 2360 iommu_set_exclusion_range(iommu); 2361 iommu_enable_ga(iommu); 2362 iommu_enable_xt(iommu); 2363 iommu_enable(iommu); 2364 iommu_flush_all_caches(iommu); 2365} 2366 2367/* 2368 * This function finally enables all IOMMUs found in the system after 2369 * they have been initialized. 2370 * 2371 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2372 * the old content of device table entries. Not this case or copy failed, 2373 * just continue as normal kernel does. 2374 */ 2375static void early_enable_iommus(void) 2376{ 2377 struct amd_iommu *iommu; 2378 2379 2380 if (!copy_device_table()) { 2381 /* 2382 * If come here because of failure in copying device table from old 2383 * kernel with all IOMMUs enabled, print error message and try to 2384 * free allocated old_dev_tbl_cpy. 2385 */ 2386 if (amd_iommu_pre_enabled) 2387 pr_err("Failed to copy DEV table from previous kernel.\n"); 2388 if (old_dev_tbl_cpy != NULL) 2389 free_pages((unsigned long)old_dev_tbl_cpy, 2390 get_order(dev_table_size)); 2391 2392 for_each_iommu(iommu) { 2393 clear_translation_pre_enabled(iommu); 2394 early_enable_iommu(iommu); 2395 } 2396 } else { 2397 pr_info("Copied DEV table from previous kernel.\n"); 2398 free_pages((unsigned long)amd_iommu_dev_table, 2399 get_order(dev_table_size)); 2400 amd_iommu_dev_table = old_dev_tbl_cpy; 2401 for_each_iommu(iommu) { 2402 iommu_disable_command_buffer(iommu); 2403 iommu_disable_event_buffer(iommu); 2404 iommu_enable_command_buffer(iommu); 2405 iommu_enable_event_buffer(iommu); 2406 iommu_enable_ga(iommu); 2407 iommu_enable_xt(iommu); 2408 iommu_set_device_table(iommu); 2409 iommu_flush_all_caches(iommu); 2410 } 2411 } 2412 2413#ifdef CONFIG_IRQ_REMAP 2414 /* 2415 * Note: We have already checked GASup from IVRS table. 2416 * Now, we need to make sure that GAMSup is set. 2417 */ 2418 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2419 !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) 2420 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2421 2422 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2423 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2424#endif 2425} 2426 2427static void enable_iommus_v2(void) 2428{ 2429 struct amd_iommu *iommu; 2430 2431 for_each_iommu(iommu) { 2432 iommu_enable_ppr_log(iommu); 2433 iommu_enable_gt(iommu); 2434 } 2435} 2436 2437static void enable_iommus(void) 2438{ 2439 early_enable_iommus(); 2440 2441 enable_iommus_v2(); 2442} 2443 2444static void disable_iommus(void) 2445{ 2446 struct amd_iommu *iommu; 2447 2448 for_each_iommu(iommu) 2449 iommu_disable(iommu); 2450 2451#ifdef CONFIG_IRQ_REMAP 2452 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2453 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2454#endif 2455} 2456 2457/* 2458 * Suspend/Resume support 2459 * disable suspend until real resume implemented 2460 */ 2461 2462static void amd_iommu_resume(void) 2463{ 2464 struct amd_iommu *iommu; 2465 2466 for_each_iommu(iommu) 2467 iommu_apply_resume_quirks(iommu); 2468 2469 /* re-load the hardware */ 2470 enable_iommus(); 2471 2472 amd_iommu_enable_interrupts(); 2473} 2474 2475static int amd_iommu_suspend(void) 2476{ 2477 /* disable IOMMUs to go out of the way for BIOS */ 2478 disable_iommus(); 2479 2480 return 0; 2481} 2482 2483static struct syscore_ops amd_iommu_syscore_ops = { 2484 .suspend = amd_iommu_suspend, 2485 .resume = amd_iommu_resume, 2486}; 2487 2488static void __init free_iommu_resources(void) 2489{ 2490 kmemleak_free(irq_lookup_table); 2491 free_pages((unsigned long)irq_lookup_table, 2492 get_order(rlookup_table_size)); 2493 irq_lookup_table = NULL; 2494 2495 kmem_cache_destroy(amd_iommu_irq_cache); 2496 amd_iommu_irq_cache = NULL; 2497 2498 free_pages((unsigned long)amd_iommu_rlookup_table, 2499 get_order(rlookup_table_size)); 2500 amd_iommu_rlookup_table = NULL; 2501 2502 free_pages((unsigned long)amd_iommu_alias_table, 2503 get_order(alias_table_size)); 2504 amd_iommu_alias_table = NULL; 2505 2506 free_pages((unsigned long)amd_iommu_dev_table, 2507 get_order(dev_table_size)); 2508 amd_iommu_dev_table = NULL; 2509 2510 free_iommu_all(); 2511} 2512 2513/* SB IOAPIC is always on this device in AMD systems */ 2514#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2515 2516static bool __init check_ioapic_information(void) 2517{ 2518 const char *fw_bug = FW_BUG; 2519 bool ret, has_sb_ioapic; 2520 int idx; 2521 2522 has_sb_ioapic = false; 2523 ret = false; 2524 2525 /* 2526 * If we have map overrides on the kernel command line the 2527 * messages in this function might not describe firmware bugs 2528 * anymore - so be careful 2529 */ 2530 if (cmdline_maps) 2531 fw_bug = ""; 2532 2533 for (idx = 0; idx < nr_ioapics; idx++) { 2534 int devid, id = mpc_ioapic_id(idx); 2535 2536 devid = get_ioapic_devid(id); 2537 if (devid < 0) { 2538 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2539 fw_bug, id); 2540 ret = false; 2541 } else if (devid == IOAPIC_SB_DEVID) { 2542 has_sb_ioapic = true; 2543 ret = true; 2544 } 2545 } 2546 2547 if (!has_sb_ioapic) { 2548 /* 2549 * We expect the SB IOAPIC to be listed in the IVRS 2550 * table. The system timer is connected to the SB IOAPIC 2551 * and if we don't have it in the list the system will 2552 * panic at boot time. This situation usually happens 2553 * when the BIOS is buggy and provides us the wrong 2554 * device id for the IOAPIC in the system. 2555 */ 2556 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2557 } 2558 2559 if (!ret) 2560 pr_err("Disabling interrupt remapping\n"); 2561 2562 return ret; 2563} 2564 2565static void __init free_dma_resources(void) 2566{ 2567 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2568 get_order(MAX_DOMAIN_ID/8)); 2569 amd_iommu_pd_alloc_bitmap = NULL; 2570 2571 free_unity_maps(); 2572} 2573 2574static void __init ivinfo_init(void *ivrs) 2575{ 2576 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2577} 2578 2579/* 2580 * This is the hardware init function for AMD IOMMU in the system. 2581 * This function is called either from amd_iommu_init or from the interrupt 2582 * remapping setup code. 2583 * 2584 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2585 * four times: 2586 * 2587 * 1 pass) Discover the most comprehensive IVHD type to use. 2588 * 2589 * 2 pass) Find the highest PCI device id the driver has to handle. 2590 * Upon this information the size of the data structures is 2591 * determined that needs to be allocated. 2592 * 2593 * 3 pass) Initialize the data structures just allocated with the 2594 * information in the ACPI table about available AMD IOMMUs 2595 * in the system. It also maps the PCI devices in the 2596 * system to specific IOMMUs 2597 * 2598 * 4 pass) After the basic data structures are allocated and 2599 * initialized we update them with information about memory 2600 * remapping requirements parsed out of the ACPI table in 2601 * this last pass. 2602 * 2603 * After everything is set up the IOMMUs are enabled and the necessary 2604 * hotplug and suspend notifiers are registered. 2605 */ 2606static int __init early_amd_iommu_init(void) 2607{ 2608 struct acpi_table_header *ivrs_base; 2609 acpi_status status; 2610 int i, remap_cache_sz, ret = 0; 2611 u32 pci_id; 2612 2613 if (!amd_iommu_detected) 2614 return -ENODEV; 2615 2616 status = acpi_get_table("IVRS", 0, &ivrs_base); 2617 if (status == AE_NOT_FOUND) 2618 return -ENODEV; 2619 else if (ACPI_FAILURE(status)) { 2620 const char *err = acpi_format_exception(status); 2621 pr_err("IVRS table error: %s\n", err); 2622 return -EINVAL; 2623 } 2624 2625 /* 2626 * Validate checksum here so we don't need to do it when 2627 * we actually parse the table 2628 */ 2629 ret = check_ivrs_checksum(ivrs_base); 2630 if (ret) 2631 goto out; 2632 2633 ivinfo_init(ivrs_base); 2634 2635 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2636 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2637 2638 /* 2639 * First parse ACPI tables to find the largest Bus/Dev/Func 2640 * we need to handle. Upon this information the shared data 2641 * structures for the IOMMUs in the system will be allocated 2642 */ 2643 ret = find_last_devid_acpi(ivrs_base); 2644 if (ret) 2645 goto out; 2646 2647 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2648 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2649 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 2650 2651 /* Device table - directly used by all IOMMUs */ 2652 ret = -ENOMEM; 2653 amd_iommu_dev_table = (void *)__get_free_pages( 2654 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2655 get_order(dev_table_size)); 2656 if (amd_iommu_dev_table == NULL) 2657 goto out; 2658 2659 /* 2660 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2661 * IOMMU see for that device 2662 */ 2663 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2664 get_order(alias_table_size)); 2665 if (amd_iommu_alias_table == NULL) 2666 goto out; 2667 2668 /* IOMMU rlookup table - find the IOMMU for a specific device */ 2669 amd_iommu_rlookup_table = (void *)__get_free_pages( 2670 GFP_KERNEL | __GFP_ZERO, 2671 get_order(rlookup_table_size)); 2672 if (amd_iommu_rlookup_table == NULL) 2673 goto out; 2674 2675 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2676 GFP_KERNEL | __GFP_ZERO, 2677 get_order(MAX_DOMAIN_ID/8)); 2678 if (amd_iommu_pd_alloc_bitmap == NULL) 2679 goto out; 2680 2681 /* 2682 * let all alias entries point to itself 2683 */ 2684 for (i = 0; i <= amd_iommu_last_bdf; ++i) 2685 amd_iommu_alias_table[i] = i; 2686 2687 /* 2688 * never allocate domain 0 because its used as the non-allocated and 2689 * error value placeholder 2690 */ 2691 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2692 2693 /* 2694 * now the data structures are allocated and basically initialized 2695 * start the real acpi table scan 2696 */ 2697 ret = init_iommu_all(ivrs_base); 2698 if (ret) 2699 goto out; 2700 2701 /* Disable IOMMU if there's Stoney Ridge graphics */ 2702 for (i = 0; i < 32; i++) { 2703 pci_id = read_pci_config(0, i, 0, 0); 2704 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 2705 pr_info("Disable IOMMU on Stoney Ridge\n"); 2706 amd_iommu_disabled = true; 2707 break; 2708 } 2709 } 2710 2711 /* Disable any previously enabled IOMMUs */ 2712 if (!is_kdump_kernel() || amd_iommu_disabled) 2713 disable_iommus(); 2714 2715 if (amd_iommu_irq_remap) 2716 amd_iommu_irq_remap = check_ioapic_information(); 2717 2718 if (amd_iommu_irq_remap) { 2719 /* 2720 * Interrupt remapping enabled, create kmem_cache for the 2721 * remapping tables. 2722 */ 2723 ret = -ENOMEM; 2724 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2725 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 2726 else 2727 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 2728 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 2729 remap_cache_sz, 2730 IRQ_TABLE_ALIGNMENT, 2731 0, NULL); 2732 if (!amd_iommu_irq_cache) 2733 goto out; 2734 2735 irq_lookup_table = (void *)__get_free_pages( 2736 GFP_KERNEL | __GFP_ZERO, 2737 get_order(rlookup_table_size)); 2738 kmemleak_alloc(irq_lookup_table, rlookup_table_size, 2739 1, GFP_KERNEL); 2740 if (!irq_lookup_table) 2741 goto out; 2742 } 2743 2744 ret = init_memory_definitions(ivrs_base); 2745 if (ret) 2746 goto out; 2747 2748 /* init the device table */ 2749 init_device_table(); 2750 2751out: 2752 /* Don't leak any ACPI memory */ 2753 acpi_put_table(ivrs_base); 2754 ivrs_base = NULL; 2755 2756 return ret; 2757} 2758 2759static int amd_iommu_enable_interrupts(void) 2760{ 2761 struct amd_iommu *iommu; 2762 int ret = 0; 2763 2764 for_each_iommu(iommu) { 2765 ret = iommu_init_msi(iommu); 2766 if (ret) 2767 goto out; 2768 } 2769 2770out: 2771 return ret; 2772} 2773 2774static bool detect_ivrs(void) 2775{ 2776 struct acpi_table_header *ivrs_base; 2777 acpi_status status; 2778 2779 status = acpi_get_table("IVRS", 0, &ivrs_base); 2780 if (status == AE_NOT_FOUND) 2781 return false; 2782 else if (ACPI_FAILURE(status)) { 2783 const char *err = acpi_format_exception(status); 2784 pr_err("IVRS table error: %s\n", err); 2785 return false; 2786 } 2787 2788 acpi_put_table(ivrs_base); 2789 2790 /* Make sure ACS will be enabled during PCI probe */ 2791 pci_request_acs(); 2792 2793 return true; 2794} 2795 2796/**************************************************************************** 2797 * 2798 * AMD IOMMU Initialization State Machine 2799 * 2800 ****************************************************************************/ 2801 2802static int __init state_next(void) 2803{ 2804 int ret = 0; 2805 2806 switch (init_state) { 2807 case IOMMU_START_STATE: 2808 if (!detect_ivrs()) { 2809 init_state = IOMMU_NOT_FOUND; 2810 ret = -ENODEV; 2811 } else { 2812 init_state = IOMMU_IVRS_DETECTED; 2813 } 2814 break; 2815 case IOMMU_IVRS_DETECTED: 2816 ret = early_amd_iommu_init(); 2817 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 2818 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) { 2819 pr_info("AMD IOMMU disabled\n"); 2820 init_state = IOMMU_CMDLINE_DISABLED; 2821 ret = -EINVAL; 2822 } 2823 break; 2824 case IOMMU_ACPI_FINISHED: 2825 early_enable_iommus(); 2826 x86_platform.iommu_shutdown = disable_iommus; 2827 init_state = IOMMU_ENABLED; 2828 break; 2829 case IOMMU_ENABLED: 2830 register_syscore_ops(&amd_iommu_syscore_ops); 2831 ret = amd_iommu_init_pci(); 2832 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 2833 enable_iommus_v2(); 2834 break; 2835 case IOMMU_PCI_INIT: 2836 ret = amd_iommu_enable_interrupts(); 2837 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 2838 break; 2839 case IOMMU_INTERRUPTS_EN: 2840 ret = amd_iommu_init_dma_ops(); 2841 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS; 2842 break; 2843 case IOMMU_DMA_OPS: 2844 init_state = IOMMU_INITIALIZED; 2845 break; 2846 case IOMMU_INITIALIZED: 2847 /* Nothing to do */ 2848 break; 2849 case IOMMU_NOT_FOUND: 2850 case IOMMU_INIT_ERROR: 2851 case IOMMU_CMDLINE_DISABLED: 2852 /* Error states => do nothing */ 2853 ret = -EINVAL; 2854 break; 2855 default: 2856 /* Unknown state */ 2857 BUG(); 2858 } 2859 2860 if (ret) { 2861 free_dma_resources(); 2862 if (!irq_remapping_enabled) { 2863 disable_iommus(); 2864 free_iommu_resources(); 2865 } else { 2866 struct amd_iommu *iommu; 2867 2868 uninit_device_table_dma(); 2869 for_each_iommu(iommu) 2870 iommu_flush_all_caches(iommu); 2871 } 2872 } 2873 return ret; 2874} 2875 2876static int __init iommu_go_to_state(enum iommu_init_state state) 2877{ 2878 int ret = -EINVAL; 2879 2880 while (init_state != state) { 2881 if (init_state == IOMMU_NOT_FOUND || 2882 init_state == IOMMU_INIT_ERROR || 2883 init_state == IOMMU_CMDLINE_DISABLED) 2884 break; 2885 ret = state_next(); 2886 } 2887 2888 return ret; 2889} 2890 2891#ifdef CONFIG_IRQ_REMAP 2892int __init amd_iommu_prepare(void) 2893{ 2894 int ret; 2895 2896 amd_iommu_irq_remap = true; 2897 2898 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 2899 if (ret) 2900 return ret; 2901 return amd_iommu_irq_remap ? 0 : -ENODEV; 2902} 2903 2904int __init amd_iommu_enable(void) 2905{ 2906 int ret; 2907 2908 ret = iommu_go_to_state(IOMMU_ENABLED); 2909 if (ret) 2910 return ret; 2911 2912 irq_remapping_enabled = 1; 2913 return amd_iommu_xt_mode; 2914} 2915 2916void amd_iommu_disable(void) 2917{ 2918 amd_iommu_suspend(); 2919} 2920 2921int amd_iommu_reenable(int mode) 2922{ 2923 amd_iommu_resume(); 2924 2925 return 0; 2926} 2927 2928int __init amd_iommu_enable_faulting(void) 2929{ 2930 /* We enable MSI later when PCI is initialized */ 2931 return 0; 2932} 2933#endif 2934 2935/* 2936 * This is the core init function for AMD IOMMU hardware in the system. 2937 * This function is called from the generic x86 DMA layer initialization 2938 * code. 2939 */ 2940static int __init amd_iommu_init(void) 2941{ 2942 struct amd_iommu *iommu; 2943 int ret; 2944 2945 ret = iommu_go_to_state(IOMMU_INITIALIZED); 2946#ifdef CONFIG_GART_IOMMU 2947 if (ret && list_empty(&amd_iommu_list)) { 2948 /* 2949 * We failed to initialize the AMD IOMMU - try fallback 2950 * to GART if possible. 2951 */ 2952 gart_iommu_init(); 2953 } 2954#endif 2955 2956 for_each_iommu(iommu) 2957 amd_iommu_debugfs_setup(iommu); 2958 2959 return ret; 2960} 2961 2962static bool amd_iommu_sme_check(void) 2963{ 2964 if (!sme_active() || (boot_cpu_data.x86 != 0x17)) 2965 return true; 2966 2967 /* For Fam17h, a specific level of support is required */ 2968 if (boot_cpu_data.microcode >= 0x08001205) 2969 return true; 2970 2971 if ((boot_cpu_data.microcode >= 0x08001126) && 2972 (boot_cpu_data.microcode <= 0x080011ff)) 2973 return true; 2974 2975 pr_notice("IOMMU not currently supported when SME is active\n"); 2976 2977 return false; 2978} 2979 2980/**************************************************************************** 2981 * 2982 * Early detect code. This code runs at IOMMU detection time in the DMA 2983 * layer. It just looks if there is an IVRS ACPI table to detect AMD 2984 * IOMMUs 2985 * 2986 ****************************************************************************/ 2987int __init amd_iommu_detect(void) 2988{ 2989 int ret; 2990 2991 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 2992 return -ENODEV; 2993 2994 if (!amd_iommu_sme_check()) 2995 return -ENODEV; 2996 2997 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 2998 if (ret) 2999 return ret; 3000 3001 amd_iommu_detected = true; 3002 iommu_detected = 1; 3003 x86_init.iommu.iommu_init = amd_iommu_init; 3004 3005 return 1; 3006} 3007 3008/**************************************************************************** 3009 * 3010 * Parsing functions for the AMD IOMMU specific kernel command line 3011 * options. 3012 * 3013 ****************************************************************************/ 3014 3015static int __init parse_amd_iommu_dump(char *str) 3016{ 3017 amd_iommu_dump = true; 3018 3019 return 1; 3020} 3021 3022static int __init parse_amd_iommu_intr(char *str) 3023{ 3024 for (; *str; ++str) { 3025 if (strncmp(str, "legacy", 6) == 0) { 3026 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3027 break; 3028 } 3029 if (strncmp(str, "vapic", 5) == 0) { 3030 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3031 break; 3032 } 3033 } 3034 return 1; 3035} 3036 3037static int __init parse_amd_iommu_options(char *str) 3038{ 3039 for (; *str; ++str) { 3040 if (strncmp(str, "fullflush", 9) == 0) 3041 amd_iommu_unmap_flush = true; 3042 if (strncmp(str, "off", 3) == 0) 3043 amd_iommu_disabled = true; 3044 if (strncmp(str, "force_isolation", 15) == 0) 3045 amd_iommu_force_isolation = true; 3046 } 3047 3048 return 1; 3049} 3050 3051static int __init parse_ivrs_ioapic(char *str) 3052{ 3053 u32 seg = 0, bus, dev, fn; 3054 int id, i; 3055 u32 devid; 3056 3057 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3058 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3059 goto found; 3060 3061 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3062 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3063 pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", 3064 str, id, seg, bus, dev, fn); 3065 goto found; 3066 } 3067 3068 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3069 return 1; 3070 3071found: 3072 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3073 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3074 str); 3075 return 1; 3076 } 3077 3078 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3079 3080 cmdline_maps = true; 3081 i = early_ioapic_map_size++; 3082 early_ioapic_map[i].id = id; 3083 early_ioapic_map[i].devid = devid; 3084 early_ioapic_map[i].cmd_line = true; 3085 3086 return 1; 3087} 3088 3089static int __init parse_ivrs_hpet(char *str) 3090{ 3091 u32 seg = 0, bus, dev, fn; 3092 int id, i; 3093 u32 devid; 3094 3095 if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3096 sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) 3097 goto found; 3098 3099 if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || 3100 sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { 3101 pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", 3102 str, id, seg, bus, dev, fn); 3103 goto found; 3104 } 3105 3106 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3107 return 1; 3108 3109found: 3110 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3111 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3112 str); 3113 return 1; 3114 } 3115 3116 devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3117 3118 cmdline_maps = true; 3119 i = early_hpet_map_size++; 3120 early_hpet_map[i].id = id; 3121 early_hpet_map[i].devid = devid; 3122 early_hpet_map[i].cmd_line = true; 3123 3124 return 1; 3125} 3126 3127#define ACPIID_LEN (ACPIHID_UID_LEN + ACPIHID_HID_LEN) 3128 3129static int __init parse_ivrs_acpihid(char *str) 3130{ 3131 u32 seg = 0, bus, dev, fn; 3132 char *hid, *uid, *p, *addr; 3133 char acpiid[ACPIID_LEN] = {0}; 3134 int i; 3135 3136 addr = strchr(str, '@'); 3137 if (!addr) { 3138 addr = strchr(str, '='); 3139 if (!addr) 3140 goto not_found; 3141 3142 ++addr; 3143 3144 if (strlen(addr) > ACPIID_LEN) 3145 goto not_found; 3146 3147 if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || 3148 sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { 3149 pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", 3150 str, acpiid, seg, bus, dev, fn); 3151 goto found; 3152 } 3153 goto not_found; 3154 } 3155 3156 /* We have the '@', make it the terminator to get just the acpiid */ 3157 *addr++ = 0; 3158 3159 if (strlen(str) > ACPIID_LEN + 1) 3160 goto not_found; 3161 3162 if (sscanf(str, "=%s", acpiid) != 1) 3163 goto not_found; 3164 3165 if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || 3166 sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) 3167 goto found; 3168 3169not_found: 3170 pr_err("Invalid command line: ivrs_acpihid%s\n", str); 3171 return 1; 3172 3173found: 3174 p = acpiid; 3175 hid = strsep(&p, ":"); 3176 uid = p; 3177 3178 if (!hid || !(*hid) || !uid) { 3179 pr_err("Invalid command line: hid or uid\n"); 3180 return 1; 3181 } 3182 3183 /* 3184 * Ignore leading zeroes after ':', so e.g., AMDI0095:00 3185 * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match 3186 */ 3187 while (*uid == '0' && *(uid + 1)) 3188 uid++; 3189 3190 i = early_acpihid_map_size++; 3191 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3192 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3193 early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); 3194 early_acpihid_map[i].cmd_line = true; 3195 3196 return 1; 3197} 3198 3199__setup("amd_iommu_dump", parse_amd_iommu_dump); 3200__setup("amd_iommu=", parse_amd_iommu_options); 3201__setup("amd_iommu_intr=", parse_amd_iommu_intr); 3202__setup("ivrs_ioapic", parse_ivrs_ioapic); 3203__setup("ivrs_hpet", parse_ivrs_hpet); 3204__setup("ivrs_acpihid", parse_ivrs_acpihid); 3205 3206IOMMU_INIT_FINISH(amd_iommu_detect, 3207 gart_iommu_hole_init, 3208 NULL, 3209 NULL); 3210 3211bool amd_iommu_v2_supported(void) 3212{ 3213 return amd_iommu_v2_present; 3214} 3215EXPORT_SYMBOL(amd_iommu_v2_supported); 3216 3217struct amd_iommu *get_amd_iommu(unsigned int idx) 3218{ 3219 unsigned int i = 0; 3220 struct amd_iommu *iommu; 3221 3222 for_each_iommu(iommu) 3223 if (i++ == idx) 3224 return iommu; 3225 return NULL; 3226} 3227EXPORT_SYMBOL(get_amd_iommu); 3228 3229/**************************************************************************** 3230 * 3231 * IOMMU EFR Performance Counter support functionality. This code allows 3232 * access to the IOMMU PC functionality. 3233 * 3234 ****************************************************************************/ 3235 3236u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3237{ 3238 struct amd_iommu *iommu = get_amd_iommu(idx); 3239 3240 if (iommu) 3241 return iommu->max_banks; 3242 3243 return 0; 3244} 3245EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3246 3247bool amd_iommu_pc_supported(void) 3248{ 3249 return amd_iommu_pc_present; 3250} 3251EXPORT_SYMBOL(amd_iommu_pc_supported); 3252 3253u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3254{ 3255 struct amd_iommu *iommu = get_amd_iommu(idx); 3256 3257 if (iommu) 3258 return iommu->max_counters; 3259 3260 return 0; 3261} 3262EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3263 3264static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3265 u8 fxn, u64 *value, bool is_write) 3266{ 3267 u32 offset; 3268 u32 max_offset_lim; 3269 3270 /* Make sure the IOMMU PC resource is available */ 3271 if (!amd_iommu_pc_present) 3272 return -ENODEV; 3273 3274 /* Check for valid iommu and pc register indexing */ 3275 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3276 return -ENODEV; 3277 3278 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3279 3280 /* Limit the offset to the hw defined mmio region aperture */ 3281 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3282 (iommu->max_counters << 8) | 0x28); 3283 if ((offset < MMIO_CNTR_REG_OFFSET) || 3284 (offset > max_offset_lim)) 3285 return -EINVAL; 3286 3287 if (is_write) { 3288 u64 val = *value & GENMASK_ULL(47, 0); 3289 3290 writel((u32)val, iommu->mmio_base + offset); 3291 writel((val >> 32), iommu->mmio_base + offset + 4); 3292 } else { 3293 *value = readl(iommu->mmio_base + offset + 4); 3294 *value <<= 32; 3295 *value |= readl(iommu->mmio_base + offset); 3296 *value &= GENMASK_ULL(47, 0); 3297 } 3298 3299 return 0; 3300} 3301 3302int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3303{ 3304 if (!iommu) 3305 return -EINVAL; 3306 3307 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3308} 3309EXPORT_SYMBOL(amd_iommu_pc_get_reg); 3310 3311int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3312{ 3313 if (!iommu) 3314 return -EINVAL; 3315 3316 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3317} 3318EXPORT_SYMBOL(amd_iommu_pc_set_reg); 3319