1/* 2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#include <linux/spinlock.h> 34#include <linux/pci.h> 35#include <linux/io.h> 36#include <linux/delay.h> 37#include <linux/netdevice.h> 38#include <linux/vmalloc.h> 39#include <linux/moduleparam.h> 40 41#include "qib.h" 42 43static unsigned qib_hol_timeout_ms = 3000; 44module_param_named(hol_timeout_ms, qib_hol_timeout_ms, uint, S_IRUGO); 45MODULE_PARM_DESC(hol_timeout_ms, 46 "duration of user app suspension after link failure"); 47 48unsigned qib_sdma_fetch_arb = 1; 49module_param_named(fetch_arb, qib_sdma_fetch_arb, uint, S_IRUGO); 50MODULE_PARM_DESC(fetch_arb, "IBA7220: change SDMA descriptor arbitration"); 51 52/** 53 * qib_disarm_piobufs - cancel a range of PIO buffers 54 * @dd: the qlogic_ib device 55 * @first: the first PIO buffer to cancel 56 * @cnt: the number of PIO buffers to cancel 57 * 58 * Cancel a range of PIO buffers. Used at user process close, 59 * in case it died while writing to a PIO buffer. 60 */ 61void qib_disarm_piobufs(struct qib_devdata *dd, unsigned first, unsigned cnt) 62{ 63 unsigned long flags; 64 unsigned i; 65 unsigned last; 66 67 last = first + cnt; 68 spin_lock_irqsave(&dd->pioavail_lock, flags); 69 for (i = first; i < last; i++) { 70 __clear_bit(i, dd->pio_need_disarm); 71 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i)); 72 } 73 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 74} 75 76/* 77 * This is called by a user process when it sees the DISARM_BUFS event 78 * bit is set. 79 */ 80int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *rcd) 81{ 82 struct qib_devdata *dd = rcd->dd; 83 unsigned i; 84 unsigned last; 85 unsigned n = 0; 86 87 last = rcd->pio_base + rcd->piocnt; 88 /* 89 * Don't need uctxt_lock here, since user has called in to us. 90 * Clear at start in case more interrupts set bits while we 91 * are disarming 92 */ 93 if (rcd->user_event_mask) { 94 /* 95 * subctxt_cnt is 0 if not shared, so do base 96 * separately, first, then remaining subctxt, if any 97 */ 98 clear_bit(_QIB_EVENT_DISARM_BUFS_BIT, &rcd->user_event_mask[0]); 99 for (i = 1; i < rcd->subctxt_cnt; i++) 100 clear_bit(_QIB_EVENT_DISARM_BUFS_BIT, 101 &rcd->user_event_mask[i]); 102 } 103 spin_lock_irq(&dd->pioavail_lock); 104 for (i = rcd->pio_base; i < last; i++) { 105 if (__test_and_clear_bit(i, dd->pio_need_disarm)) { 106 n++; 107 dd->f_sendctrl(rcd->ppd, QIB_SENDCTRL_DISARM_BUF(i)); 108 } 109 } 110 spin_unlock_irq(&dd->pioavail_lock); 111 return 0; 112} 113 114static struct qib_pportdata *is_sdma_buf(struct qib_devdata *dd, unsigned i) 115{ 116 struct qib_pportdata *ppd; 117 unsigned pidx; 118 119 for (pidx = 0; pidx < dd->num_pports; pidx++) { 120 ppd = dd->pport + pidx; 121 if (i >= ppd->sdma_state.first_sendbuf && 122 i < ppd->sdma_state.last_sendbuf) 123 return ppd; 124 } 125 return NULL; 126} 127 128/* 129 * Return true if send buffer is being used by a user context. 130 * Sets _QIB_EVENT_DISARM_BUFS_BIT in user_event_mask as a side effect 131 */ 132static int find_ctxt(struct qib_devdata *dd, unsigned bufn) 133{ 134 struct qib_ctxtdata *rcd; 135 unsigned ctxt; 136 int ret = 0; 137 138 spin_lock(&dd->uctxt_lock); 139 for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts; ctxt++) { 140 rcd = dd->rcd[ctxt]; 141 if (!rcd || bufn < rcd->pio_base || 142 bufn >= rcd->pio_base + rcd->piocnt) 143 continue; 144 if (rcd->user_event_mask) { 145 int i; 146 /* 147 * subctxt_cnt is 0 if not shared, so do base 148 * separately, first, then remaining subctxt, if any 149 */ 150 set_bit(_QIB_EVENT_DISARM_BUFS_BIT, 151 &rcd->user_event_mask[0]); 152 for (i = 1; i < rcd->subctxt_cnt; i++) 153 set_bit(_QIB_EVENT_DISARM_BUFS_BIT, 154 &rcd->user_event_mask[i]); 155 } 156 ret = 1; 157 break; 158 } 159 spin_unlock(&dd->uctxt_lock); 160 161 return ret; 162} 163 164/* 165 * Disarm a set of send buffers. If the buffer might be actively being 166 * written to, mark the buffer to be disarmed later when it is not being 167 * written to. 168 * 169 * This should only be called from the IRQ error handler. 170 */ 171void qib_disarm_piobufs_set(struct qib_devdata *dd, unsigned long *mask, 172 unsigned cnt) 173{ 174 struct qib_pportdata *ppd, *pppd[QIB_MAX_IB_PORTS]; 175 unsigned i; 176 unsigned long flags; 177 178 for (i = 0; i < dd->num_pports; i++) 179 pppd[i] = NULL; 180 181 for (i = 0; i < cnt; i++) { 182 if (!test_bit(i, mask)) 183 continue; 184 /* 185 * If the buffer is owned by the DMA hardware, 186 * reset the DMA engine. 187 */ 188 ppd = is_sdma_buf(dd, i); 189 if (ppd) { 190 pppd[ppd->port] = ppd; 191 continue; 192 } 193 /* 194 * If the kernel is writing the buffer or the buffer is 195 * owned by a user process, we can't clear it yet. 196 */ 197 spin_lock_irqsave(&dd->pioavail_lock, flags); 198 if (test_bit(i, dd->pio_writing) || 199 (!test_bit(i << 1, dd->pioavailkernel) && 200 find_ctxt(dd, i))) { 201 __set_bit(i, dd->pio_need_disarm); 202 } else { 203 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i)); 204 } 205 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 206 } 207 208 /* do cancel_sends once per port that had sdma piobufs in error */ 209 for (i = 0; i < dd->num_pports; i++) 210 if (pppd[i]) 211 qib_cancel_sends(pppd[i]); 212} 213 214/** 215 * update_send_bufs - update shadow copy of the PIO availability map 216 * @dd: the qlogic_ib device 217 * 218 * called whenever our local copy indicates we have run out of send buffers 219 */ 220static void update_send_bufs(struct qib_devdata *dd) 221{ 222 unsigned long flags; 223 unsigned i; 224 const unsigned piobregs = dd->pioavregs; 225 226 /* 227 * If the generation (check) bits have changed, then we update the 228 * busy bit for the corresponding PIO buffer. This algorithm will 229 * modify positions to the value they already have in some cases 230 * (i.e., no change), but it's faster than changing only the bits 231 * that have changed. 232 * 233 * We would like to do this atomicly, to avoid spinlocks in the 234 * critical send path, but that's not really possible, given the 235 * type of changes, and that this routine could be called on 236 * multiple cpu's simultaneously, so we lock in this routine only, 237 * to avoid conflicting updates; all we change is the shadow, and 238 * it's a single 64 bit memory location, so by definition the update 239 * is atomic in terms of what other cpu's can see in testing the 240 * bits. The spin_lock overhead isn't too bad, since it only 241 * happens when all buffers are in use, so only cpu overhead, not 242 * latency or bandwidth is affected. 243 */ 244 if (!dd->pioavailregs_dma) 245 return; 246 spin_lock_irqsave(&dd->pioavail_lock, flags); 247 for (i = 0; i < piobregs; i++) { 248 u64 pchbusy, pchg, piov, pnew; 249 250 piov = le64_to_cpu(dd->pioavailregs_dma[i]); 251 pchg = dd->pioavailkernel[i] & 252 ~(dd->pioavailshadow[i] ^ piov); 253 pchbusy = pchg << QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT; 254 if (pchg && (pchbusy & dd->pioavailshadow[i])) { 255 pnew = dd->pioavailshadow[i] & ~pchbusy; 256 pnew |= piov & pchbusy; 257 dd->pioavailshadow[i] = pnew; 258 } 259 } 260 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 261} 262 263/* 264 * Debugging code and stats updates if no pio buffers available. 265 */ 266static noinline void no_send_bufs(struct qib_devdata *dd) 267{ 268 dd->upd_pio_shadow = 1; 269 270 /* not atomic, but if we lose a stat count in a while, that's OK */ 271 qib_stats.sps_nopiobufs++; 272} 273 274/* 275 * Common code for normal driver send buffer allocation, and reserved 276 * allocation. 277 * 278 * Do appropriate marking as busy, etc. 279 * Returns buffer pointer if one is found, otherwise NULL. 280 */ 281u32 __iomem *qib_getsendbuf_range(struct qib_devdata *dd, u32 *pbufnum, 282 u32 first, u32 last) 283{ 284 unsigned i, j, updated = 0; 285 unsigned nbufs; 286 unsigned long flags; 287 unsigned long *shadow = dd->pioavailshadow; 288 u32 __iomem *buf; 289 290 if (!(dd->flags & QIB_PRESENT)) 291 return NULL; 292 293 nbufs = last - first + 1; /* number in range to check */ 294 if (dd->upd_pio_shadow) { 295update_shadow: 296 /* 297 * Minor optimization. If we had no buffers on last call, 298 * start out by doing the update; continue and do scan even 299 * if no buffers were updated, to be paranoid. 300 */ 301 update_send_bufs(dd); 302 updated++; 303 } 304 i = first; 305 /* 306 * While test_and_set_bit() is atomic, we do that and then the 307 * change_bit(), and the pair is not. See if this is the cause 308 * of the remaining armlaunch errors. 309 */ 310 spin_lock_irqsave(&dd->pioavail_lock, flags); 311 if (dd->last_pio >= first && dd->last_pio <= last) 312 i = dd->last_pio + 1; 313 if (!first) 314 /* adjust to min possible */ 315 nbufs = last - dd->min_kernel_pio + 1; 316 for (j = 0; j < nbufs; j++, i++) { 317 if (i > last) 318 i = !first ? dd->min_kernel_pio : first; 319 if (__test_and_set_bit((2 * i) + 1, shadow)) 320 continue; 321 /* flip generation bit */ 322 __change_bit(2 * i, shadow); 323 /* remember that the buffer can be written to now */ 324 __set_bit(i, dd->pio_writing); 325 if (!first && first != last) /* first == last on VL15, avoid */ 326 dd->last_pio = i; 327 break; 328 } 329 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 330 331 if (j == nbufs) { 332 if (!updated) 333 /* 334 * First time through; shadow exhausted, but may be 335 * buffers available, try an update and then rescan. 336 */ 337 goto update_shadow; 338 no_send_bufs(dd); 339 buf = NULL; 340 } else { 341 if (i < dd->piobcnt2k) 342 buf = (u32 __iomem *)(dd->pio2kbase + 343 i * dd->palign); 344 else if (i < dd->piobcnt2k + dd->piobcnt4k || !dd->piovl15base) 345 buf = (u32 __iomem *)(dd->pio4kbase + 346 (i - dd->piobcnt2k) * dd->align4k); 347 else 348 buf = (u32 __iomem *)(dd->piovl15base + 349 (i - (dd->piobcnt2k + dd->piobcnt4k)) * 350 dd->align4k); 351 if (pbufnum) 352 *pbufnum = i; 353 dd->upd_pio_shadow = 0; 354 } 355 356 return buf; 357} 358 359/* 360 * Record that the caller is finished writing to the buffer so we don't 361 * disarm it while it is being written and disarm it now if needed. 362 */ 363void qib_sendbuf_done(struct qib_devdata *dd, unsigned n) 364{ 365 unsigned long flags; 366 367 spin_lock_irqsave(&dd->pioavail_lock, flags); 368 __clear_bit(n, dd->pio_writing); 369 if (__test_and_clear_bit(n, dd->pio_need_disarm)) 370 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(n)); 371 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 372} 373 374/** 375 * qib_chg_pioavailkernel - change which send buffers are available for kernel 376 * @dd: the qlogic_ib device 377 * @start: the starting send buffer number 378 * @len: the number of send buffers 379 * @avail: true if the buffers are available for kernel use, false otherwise 380 */ 381void qib_chg_pioavailkernel(struct qib_devdata *dd, unsigned start, 382 unsigned len, u32 avail, struct qib_ctxtdata *rcd) 383{ 384 unsigned long flags; 385 unsigned end; 386 unsigned ostart = start; 387 388 /* There are two bits per send buffer (busy and generation) */ 389 start *= 2; 390 end = start + len * 2; 391 392 spin_lock_irqsave(&dd->pioavail_lock, flags); 393 /* Set or clear the busy bit in the shadow. */ 394 while (start < end) { 395 if (avail) { 396 unsigned long dma; 397 int i; 398 399 /* 400 * The BUSY bit will never be set, because we disarm 401 * the user buffers before we hand them back to the 402 * kernel. We do have to make sure the generation 403 * bit is set correctly in shadow, since it could 404 * have changed many times while allocated to user. 405 * We can't use the bitmap functions on the full 406 * dma array because it is always little-endian, so 407 * we have to flip to host-order first. 408 * BITS_PER_LONG is slightly wrong, since it's 409 * always 64 bits per register in chip... 410 * We only work on 64 bit kernels, so that's OK. 411 */ 412 i = start / BITS_PER_LONG; 413 __clear_bit(QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT + start, 414 dd->pioavailshadow); 415 dma = (unsigned long) 416 le64_to_cpu(dd->pioavailregs_dma[i]); 417 if (test_bit((QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT + 418 start) % BITS_PER_LONG, &dma)) 419 __set_bit(QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT + 420 start, dd->pioavailshadow); 421 else 422 __clear_bit(QLOGIC_IB_SENDPIOAVAIL_CHECK_SHIFT 423 + start, dd->pioavailshadow); 424 __set_bit(start, dd->pioavailkernel); 425 if ((start >> 1) < dd->min_kernel_pio) 426 dd->min_kernel_pio = start >> 1; 427 } else { 428 __set_bit(start + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT, 429 dd->pioavailshadow); 430 __clear_bit(start, dd->pioavailkernel); 431 if ((start >> 1) > dd->min_kernel_pio) 432 dd->min_kernel_pio = start >> 1; 433 } 434 start += 2; 435 } 436 437 if (dd->min_kernel_pio > 0 && dd->last_pio < dd->min_kernel_pio - 1) 438 dd->last_pio = dd->min_kernel_pio - 1; 439 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 440 441 dd->f_txchk_change(dd, ostart, len, avail, rcd); 442} 443 444/* 445 * Flush all sends that might be in the ready to send state, as well as any 446 * that are in the process of being sent. Used whenever we need to be 447 * sure the send side is idle. Cleans up all buffer state by canceling 448 * all pio buffers, and issuing an abort, which cleans up anything in the 449 * launch fifo. The cancel is superfluous on some chip versions, but 450 * it's safer to always do it. 451 * PIOAvail bits are updated by the chip as if a normal send had happened. 452 */ 453void qib_cancel_sends(struct qib_pportdata *ppd) 454{ 455 struct qib_devdata *dd = ppd->dd; 456 struct qib_ctxtdata *rcd; 457 unsigned long flags; 458 unsigned ctxt; 459 unsigned i; 460 unsigned last; 461 462 /* 463 * Tell PSM to disarm buffers again before trying to reuse them. 464 * We need to be sure the rcd doesn't change out from under us 465 * while we do so. We hold the two locks sequentially. We might 466 * needlessly set some need_disarm bits as a result, if the 467 * context is closed after we release the uctxt_lock, but that's 468 * fairly benign, and safer than nesting the locks. 469 */ 470 for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts; ctxt++) { 471 spin_lock_irqsave(&dd->uctxt_lock, flags); 472 rcd = dd->rcd[ctxt]; 473 if (rcd && rcd->ppd == ppd) { 474 last = rcd->pio_base + rcd->piocnt; 475 if (rcd->user_event_mask) { 476 /* 477 * subctxt_cnt is 0 if not shared, so do base 478 * separately, first, then remaining subctxt, 479 * if any 480 */ 481 set_bit(_QIB_EVENT_DISARM_BUFS_BIT, 482 &rcd->user_event_mask[0]); 483 for (i = 1; i < rcd->subctxt_cnt; i++) 484 set_bit(_QIB_EVENT_DISARM_BUFS_BIT, 485 &rcd->user_event_mask[i]); 486 } 487 i = rcd->pio_base; 488 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 489 spin_lock_irqsave(&dd->pioavail_lock, flags); 490 for (; i < last; i++) 491 __set_bit(i, dd->pio_need_disarm); 492 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 493 } else 494 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 495 } 496 497 if (!(dd->flags & QIB_HAS_SEND_DMA)) 498 dd->f_sendctrl(ppd, QIB_SENDCTRL_DISARM_ALL | 499 QIB_SENDCTRL_FLUSH); 500} 501 502/* 503 * Force an update of in-memory copy of the pioavail registers, when 504 * needed for any of a variety of reasons. 505 * If already off, this routine is a nop, on the assumption that the 506 * caller (or set of callers) will "do the right thing". 507 * This is a per-device operation, so just the first port. 508 */ 509void qib_force_pio_avail_update(struct qib_devdata *dd) 510{ 511 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 512} 513 514void qib_hol_down(struct qib_pportdata *ppd) 515{ 516 /* 517 * Cancel sends when the link goes DOWN so that we aren't doing it 518 * at INIT when we might be trying to send SMI packets. 519 */ 520 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 521 qib_cancel_sends(ppd); 522} 523 524/* 525 * Link is at INIT. 526 * We start the HoL timer so we can detect stuck packets blocking SMP replies. 527 * Timer may already be running, so use mod_timer, not add_timer. 528 */ 529void qib_hol_init(struct qib_pportdata *ppd) 530{ 531 if (ppd->hol_state != QIB_HOL_INIT) { 532 ppd->hol_state = QIB_HOL_INIT; 533 mod_timer(&ppd->hol_timer, 534 jiffies + msecs_to_jiffies(qib_hol_timeout_ms)); 535 } 536} 537 538/* 539 * Link is up, continue any user processes, and ensure timer 540 * is a nop, if running. Let timer keep running, if set; it 541 * will nop when it sees the link is up. 542 */ 543void qib_hol_up(struct qib_pportdata *ppd) 544{ 545 ppd->hol_state = QIB_HOL_UP; 546} 547 548/* 549 * This is only called via the timer. 550 */ 551void qib_hol_event(struct timer_list *t) 552{ 553 struct qib_pportdata *ppd = from_timer(ppd, t, hol_timer); 554 555 /* If hardware error, etc, skip. */ 556 if (!(ppd->dd->flags & QIB_INITTED)) 557 return; 558 559 if (ppd->hol_state != QIB_HOL_UP) { 560 /* 561 * Try to flush sends in case a stuck packet is blocking 562 * SMP replies. 563 */ 564 qib_hol_down(ppd); 565 mod_timer(&ppd->hol_timer, 566 jiffies + msecs_to_jiffies(qib_hol_timeout_ms)); 567 } 568} 569