1/* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#include <linux/module.h> 33#include <rdma/ib_verbs.h> 34#include <rdma/ib_addr.h> 35#include <rdma/ib_user_verbs.h> 36#include <rdma/iw_cm.h> 37#include <rdma/ib_mad.h> 38#include <linux/netdevice.h> 39#include <linux/iommu.h> 40#include <linux/pci.h> 41#include <net/addrconf.h> 42 43#include <linux/qed/qed_chain.h> 44#include <linux/qed/qed_if.h> 45#include "qedr.h" 46#include "verbs.h" 47#include <rdma/qedr-abi.h> 48#include "qedr_iw_cm.h" 49 50MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver"); 51MODULE_AUTHOR("QLogic Corporation"); 52MODULE_LICENSE("Dual BSD/GPL"); 53 54#define QEDR_WQ_MULTIPLIER_DFT (3) 55 56static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num, 57 enum ib_event_type type) 58{ 59 struct ib_event ibev; 60 61 ibev.device = &dev->ibdev; 62 ibev.element.port_num = port_num; 63 ibev.event = type; 64 65 ib_dispatch_event(&ibev); 66} 67 68static enum rdma_link_layer qedr_link_layer(struct ib_device *device, 69 u8 port_num) 70{ 71 return IB_LINK_LAYER_ETHERNET; 72} 73 74static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str) 75{ 76 struct qedr_dev *qedr = get_qedr_dev(ibdev); 77 u32 fw_ver = (u32)qedr->attr.fw_ver; 78 79 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 80 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF, 81 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); 82} 83 84static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num, 85 struct ib_port_immutable *immutable) 86{ 87 struct ib_port_attr attr; 88 int err; 89 90 err = qedr_query_port(ibdev, port_num, &attr); 91 if (err) 92 return err; 93 94 immutable->pkey_tbl_len = attr.pkey_tbl_len; 95 immutable->gid_tbl_len = attr.gid_tbl_len; 96 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 97 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 98 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 99 100 return 0; 101} 102 103static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num, 104 struct ib_port_immutable *immutable) 105{ 106 struct ib_port_attr attr; 107 int err; 108 109 err = qedr_query_port(ibdev, port_num, &attr); 110 if (err) 111 return err; 112 113 immutable->gid_tbl_len = 1; 114 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 115 immutable->max_mad_size = 0; 116 117 return 0; 118} 119 120/* QEDR sysfs interface */ 121static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 122 char *buf) 123{ 124 struct qedr_dev *dev = 125 rdma_device_to_drv_device(device, struct qedr_dev, ibdev); 126 127 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->attr.hw_ver); 128} 129static DEVICE_ATTR_RO(hw_rev); 130 131static ssize_t hca_type_show(struct device *device, 132 struct device_attribute *attr, char *buf) 133{ 134 struct qedr_dev *dev = 135 rdma_device_to_drv_device(device, struct qedr_dev, ibdev); 136 137 return scnprintf(buf, PAGE_SIZE, "FastLinQ QL%x %s\n", 138 dev->pdev->device, 139 rdma_protocol_iwarp(&dev->ibdev, 1) ? 140 "iWARP" : "RoCE"); 141} 142static DEVICE_ATTR_RO(hca_type); 143 144static struct attribute *qedr_attributes[] = { 145 &dev_attr_hw_rev.attr, 146 &dev_attr_hca_type.attr, 147 NULL 148}; 149 150static const struct attribute_group qedr_attr_group = { 151 .attrs = qedr_attributes, 152}; 153 154static const struct ib_device_ops qedr_iw_dev_ops = { 155 .get_port_immutable = qedr_iw_port_immutable, 156 .iw_accept = qedr_iw_accept, 157 .iw_add_ref = qedr_iw_qp_add_ref, 158 .iw_connect = qedr_iw_connect, 159 .iw_create_listen = qedr_iw_create_listen, 160 .iw_destroy_listen = qedr_iw_destroy_listen, 161 .iw_get_qp = qedr_iw_get_qp, 162 .iw_reject = qedr_iw_reject, 163 .iw_rem_ref = qedr_iw_qp_rem_ref, 164 .query_gid = qedr_iw_query_gid, 165}; 166 167static int qedr_iw_register_device(struct qedr_dev *dev) 168{ 169 dev->ibdev.node_type = RDMA_NODE_RNIC; 170 171 ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops); 172 173 memcpy(dev->ibdev.iw_ifname, 174 dev->ndev->name, sizeof(dev->ibdev.iw_ifname)); 175 176 return 0; 177} 178 179static const struct ib_device_ops qedr_roce_dev_ops = { 180 .alloc_xrcd = qedr_alloc_xrcd, 181 .dealloc_xrcd = qedr_dealloc_xrcd, 182 .get_port_immutable = qedr_roce_port_immutable, 183 .query_pkey = qedr_query_pkey, 184}; 185 186static void qedr_roce_register_device(struct qedr_dev *dev) 187{ 188 dev->ibdev.node_type = RDMA_NODE_IB_CA; 189 190 ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops); 191 192 dev->ibdev.uverbs_cmd_mask |= QEDR_UVERBS(OPEN_XRCD) | 193 QEDR_UVERBS(CLOSE_XRCD) | 194 QEDR_UVERBS(CREATE_XSRQ); 195} 196 197static const struct ib_device_ops qedr_dev_ops = { 198 .owner = THIS_MODULE, 199 .driver_id = RDMA_DRIVER_QEDR, 200 .uverbs_abi_ver = QEDR_ABI_VERSION, 201 202 .alloc_mr = qedr_alloc_mr, 203 .alloc_pd = qedr_alloc_pd, 204 .alloc_ucontext = qedr_alloc_ucontext, 205 .create_ah = qedr_create_ah, 206 .create_cq = qedr_create_cq, 207 .create_qp = qedr_create_qp, 208 .create_srq = qedr_create_srq, 209 .dealloc_pd = qedr_dealloc_pd, 210 .dealloc_ucontext = qedr_dealloc_ucontext, 211 .dereg_mr = qedr_dereg_mr, 212 .destroy_ah = qedr_destroy_ah, 213 .destroy_cq = qedr_destroy_cq, 214 .destroy_qp = qedr_destroy_qp, 215 .destroy_srq = qedr_destroy_srq, 216 .get_dev_fw_str = qedr_get_dev_fw_str, 217 .get_dma_mr = qedr_get_dma_mr, 218 .get_link_layer = qedr_link_layer, 219 .map_mr_sg = qedr_map_mr_sg, 220 .mmap = qedr_mmap, 221 .mmap_free = qedr_mmap_free, 222 .modify_qp = qedr_modify_qp, 223 .modify_srq = qedr_modify_srq, 224 .poll_cq = qedr_poll_cq, 225 .post_recv = qedr_post_recv, 226 .post_send = qedr_post_send, 227 .post_srq_recv = qedr_post_srq_recv, 228 .process_mad = qedr_process_mad, 229 .query_device = qedr_query_device, 230 .query_port = qedr_query_port, 231 .query_qp = qedr_query_qp, 232 .query_srq = qedr_query_srq, 233 .reg_user_mr = qedr_reg_user_mr, 234 .req_notify_cq = qedr_arm_cq, 235 .resize_cq = qedr_resize_cq, 236 237 INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah), 238 INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq), 239 INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd), 240 INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq), 241 INIT_RDMA_OBJ_SIZE(ib_xrcd, qedr_xrcd, ibxrcd), 242 INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext), 243}; 244 245static int qedr_register_device(struct qedr_dev *dev) 246{ 247 int rc; 248 249 dev->ibdev.node_guid = dev->attr.node_guid; 250 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC)); 251 252 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) | 253 QEDR_UVERBS(QUERY_DEVICE) | 254 QEDR_UVERBS(QUERY_PORT) | 255 QEDR_UVERBS(ALLOC_PD) | 256 QEDR_UVERBS(DEALLOC_PD) | 257 QEDR_UVERBS(CREATE_COMP_CHANNEL) | 258 QEDR_UVERBS(CREATE_CQ) | 259 QEDR_UVERBS(RESIZE_CQ) | 260 QEDR_UVERBS(DESTROY_CQ) | 261 QEDR_UVERBS(REQ_NOTIFY_CQ) | 262 QEDR_UVERBS(CREATE_QP) | 263 QEDR_UVERBS(MODIFY_QP) | 264 QEDR_UVERBS(QUERY_QP) | 265 QEDR_UVERBS(DESTROY_QP) | 266 QEDR_UVERBS(CREATE_SRQ) | 267 QEDR_UVERBS(DESTROY_SRQ) | 268 QEDR_UVERBS(QUERY_SRQ) | 269 QEDR_UVERBS(MODIFY_SRQ) | 270 QEDR_UVERBS(POST_SRQ_RECV) | 271 QEDR_UVERBS(REG_MR) | 272 QEDR_UVERBS(DEREG_MR) | 273 QEDR_UVERBS(POLL_CQ) | 274 QEDR_UVERBS(POST_SEND) | 275 QEDR_UVERBS(POST_RECV); 276 277 if (IS_IWARP(dev)) { 278 rc = qedr_iw_register_device(dev); 279 if (rc) 280 return rc; 281 } else { 282 qedr_roce_register_device(dev); 283 } 284 285 dev->ibdev.phys_port_cnt = 1; 286 dev->ibdev.num_comp_vectors = dev->num_cnq; 287 dev->ibdev.dev.parent = &dev->pdev->dev; 288 289 rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group); 290 ib_set_device_ops(&dev->ibdev, &qedr_dev_ops); 291 292 rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1); 293 if (rc) 294 return rc; 295 296 dma_set_max_seg_size(&dev->pdev->dev, UINT_MAX); 297 return ib_register_device(&dev->ibdev, "qedr%d", &dev->pdev->dev); 298} 299 300/* This function allocates fast-path status block memory */ 301static int qedr_alloc_mem_sb(struct qedr_dev *dev, 302 struct qed_sb_info *sb_info, u16 sb_id) 303{ 304 struct status_block_e4 *sb_virt; 305 dma_addr_t sb_phys; 306 int rc; 307 308 sb_virt = dma_alloc_coherent(&dev->pdev->dev, 309 sizeof(*sb_virt), &sb_phys, GFP_KERNEL); 310 if (!sb_virt) 311 return -ENOMEM; 312 313 rc = dev->ops->common->sb_init(dev->cdev, sb_info, 314 sb_virt, sb_phys, sb_id, 315 QED_SB_TYPE_CNQ); 316 if (rc) { 317 pr_err("Status block initialization failed\n"); 318 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt), 319 sb_virt, sb_phys); 320 return rc; 321 } 322 323 return 0; 324} 325 326static void qedr_free_mem_sb(struct qedr_dev *dev, 327 struct qed_sb_info *sb_info, int sb_id) 328{ 329 if (sb_info->sb_virt) { 330 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id, 331 QED_SB_TYPE_CNQ); 332 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt), 333 (void *)sb_info->sb_virt, sb_info->sb_phys); 334 } 335} 336 337static void qedr_free_resources(struct qedr_dev *dev) 338{ 339 int i; 340 341 if (IS_IWARP(dev)) 342 destroy_workqueue(dev->iwarp_wq); 343 344 for (i = 0; i < dev->num_cnq; i++) { 345 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 346 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 347 } 348 349 kfree(dev->cnq_array); 350 kfree(dev->sb_array); 351 kfree(dev->sgid_tbl); 352} 353 354static int qedr_alloc_resources(struct qedr_dev *dev) 355{ 356 struct qed_chain_init_params params = { 357 .mode = QED_CHAIN_MODE_PBL, 358 .intended_use = QED_CHAIN_USE_TO_CONSUME, 359 .cnt_type = QED_CHAIN_CNT_TYPE_U16, 360 .elem_size = sizeof(struct regpair *), 361 }; 362 struct qedr_cnq *cnq; 363 __le16 *cons_pi; 364 int i, rc; 365 366 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid), 367 GFP_KERNEL); 368 if (!dev->sgid_tbl) 369 return -ENOMEM; 370 371 spin_lock_init(&dev->sgid_lock); 372 xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ); 373 374 if (IS_IWARP(dev)) { 375 xa_init(&dev->qps); 376 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq"); 377 if (!dev->iwarp_wq) { 378 rc = -ENOMEM; 379 goto err1; 380 } 381 } 382 383 /* Allocate Status blocks for CNQ */ 384 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array), 385 GFP_KERNEL); 386 if (!dev->sb_array) { 387 rc = -ENOMEM; 388 goto err_destroy_wq; 389 } 390 391 dev->cnq_array = kcalloc(dev->num_cnq, 392 sizeof(*dev->cnq_array), GFP_KERNEL); 393 if (!dev->cnq_array) { 394 rc = -ENOMEM; 395 goto err2; 396 } 397 398 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev); 399 400 /* Allocate CNQ PBLs */ 401 params.num_elems = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, 402 QEDR_ROCE_MAX_CNQ_SIZE); 403 404 for (i = 0; i < dev->num_cnq; i++) { 405 cnq = &dev->cnq_array[i]; 406 407 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i], 408 dev->sb_start + i); 409 if (rc) 410 goto err3; 411 412 rc = dev->ops->common->chain_alloc(dev->cdev, &cnq->pbl, 413 ¶ms); 414 if (rc) 415 goto err4; 416 417 cnq->dev = dev; 418 cnq->sb = &dev->sb_array[i]; 419 cons_pi = dev->sb_array[i].sb_virt->pi_array; 420 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX]; 421 cnq->index = i; 422 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev)); 423 424 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n", 425 i, qed_chain_get_cons_idx(&cnq->pbl)); 426 } 427 428 return 0; 429err4: 430 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 431err3: 432 for (--i; i >= 0; i--) { 433 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 434 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 435 } 436 kfree(dev->cnq_array); 437err2: 438 kfree(dev->sb_array); 439err_destroy_wq: 440 if (IS_IWARP(dev)) 441 destroy_workqueue(dev->iwarp_wq); 442err1: 443 kfree(dev->sgid_tbl); 444 return rc; 445} 446 447static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev) 448{ 449 int rc = pci_enable_atomic_ops_to_root(pdev, 450 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 451 452 if (rc) { 453 dev->atomic_cap = IB_ATOMIC_NONE; 454 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n"); 455 } else { 456 dev->atomic_cap = IB_ATOMIC_GLOB; 457 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n"); 458 } 459} 460 461static const struct qed_rdma_ops *qed_ops; 462 463#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 464 465static irqreturn_t qedr_irq_handler(int irq, void *handle) 466{ 467 u16 hw_comp_cons, sw_comp_cons; 468 struct qedr_cnq *cnq = handle; 469 struct regpair *cq_handle; 470 struct qedr_cq *cq; 471 472 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0); 473 474 qed_sb_update_sb_idx(cnq->sb); 475 476 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 477 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 478 479 /* Align protocol-index and chain reads */ 480 rmb(); 481 482 while (sw_comp_cons != hw_comp_cons) { 483 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl); 484 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 485 cq_handle->lo); 486 487 if (cq == NULL) { 488 DP_ERR(cnq->dev, 489 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n", 490 cq_handle->hi, cq_handle->lo, sw_comp_cons, 491 hw_comp_cons); 492 493 break; 494 } 495 496 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) { 497 DP_ERR(cnq->dev, 498 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n", 499 cq_handle->hi, cq_handle->lo, cq); 500 break; 501 } 502 503 cq->arm_flags = 0; 504 505 if (!cq->destroyed && cq->ibcq.comp_handler) 506 (*cq->ibcq.comp_handler) 507 (&cq->ibcq, cq->ibcq.cq_context); 508 509 /* The CQ's CNQ notification counter is checked before 510 * destroying the CQ in a busy-wait loop that waits for all of 511 * the CQ's CNQ interrupts to be processed. It is increased 512 * here, only after the completion handler, to ensure that the 513 * the handler is not running when the CQ is destroyed. 514 */ 515 cq->cnq_notif++; 516 517 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl); 518 519 cnq->n_comp++; 520 } 521 522 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, 523 sw_comp_cons); 524 525 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1); 526 527 return IRQ_HANDLED; 528} 529 530static void qedr_sync_free_irqs(struct qedr_dev *dev) 531{ 532 u32 vector; 533 u16 idx; 534 int i; 535 536 for (i = 0; i < dev->int_info.used_cnt; i++) { 537 if (dev->int_info.msix_cnt) { 538 idx = i * dev->num_hwfns + dev->affin_hwfn_idx; 539 vector = dev->int_info.msix[idx].vector; 540 synchronize_irq(vector); 541 free_irq(vector, &dev->cnq_array[i]); 542 } 543 } 544 545 dev->int_info.used_cnt = 0; 546} 547 548static int qedr_req_msix_irqs(struct qedr_dev *dev) 549{ 550 int i, rc = 0; 551 u16 idx; 552 553 if (dev->num_cnq > dev->int_info.msix_cnt) { 554 DP_ERR(dev, 555 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n", 556 dev->num_cnq, dev->int_info.msix_cnt); 557 return -EINVAL; 558 } 559 560 for (i = 0; i < dev->num_cnq; i++) { 561 idx = i * dev->num_hwfns + dev->affin_hwfn_idx; 562 rc = request_irq(dev->int_info.msix[idx].vector, 563 qedr_irq_handler, 0, dev->cnq_array[i].name, 564 &dev->cnq_array[i]); 565 if (rc) { 566 DP_ERR(dev, "Request cnq %d irq failed\n", i); 567 qedr_sync_free_irqs(dev); 568 } else { 569 DP_DEBUG(dev, QEDR_MSG_INIT, 570 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n", 571 dev->cnq_array[i].name, i, 572 &dev->cnq_array[i]); 573 dev->int_info.used_cnt++; 574 } 575 } 576 577 return rc; 578} 579 580static int qedr_setup_irqs(struct qedr_dev *dev) 581{ 582 int rc; 583 584 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n"); 585 586 /* Learn Interrupt configuration */ 587 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq); 588 if (rc < 0) 589 return rc; 590 591 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info); 592 if (rc) { 593 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n"); 594 return rc; 595 } 596 597 if (dev->int_info.msix_cnt) { 598 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n", 599 dev->int_info.msix_cnt); 600 rc = qedr_req_msix_irqs(dev); 601 if (rc) 602 return rc; 603 } 604 605 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n"); 606 607 return 0; 608} 609 610static int qedr_set_device_attr(struct qedr_dev *dev) 611{ 612 struct qed_rdma_device *qed_attr; 613 struct qedr_device_attr *attr; 614 u32 page_size; 615 616 /* Part 1 - query core capabilities */ 617 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx); 618 619 /* Part 2 - check capabilities */ 620 page_size = ~qed_attr->page_size_caps + 1; 621 if (page_size > PAGE_SIZE) { 622 DP_ERR(dev, 623 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n", 624 PAGE_SIZE, page_size); 625 return -ENODEV; 626 } 627 628 /* Part 3 - copy and update capabilities */ 629 attr = &dev->attr; 630 attr->vendor_id = qed_attr->vendor_id; 631 attr->vendor_part_id = qed_attr->vendor_part_id; 632 attr->hw_ver = qed_attr->hw_ver; 633 attr->fw_ver = qed_attr->fw_ver; 634 attr->node_guid = qed_attr->node_guid; 635 attr->sys_image_guid = qed_attr->sys_image_guid; 636 attr->max_cnq = qed_attr->max_cnq; 637 attr->max_sge = qed_attr->max_sge; 638 attr->max_inline = qed_attr->max_inline; 639 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE); 640 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE); 641 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc; 642 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc; 643 attr->max_dev_resp_rd_atomic_resc = 644 qed_attr->max_dev_resp_rd_atomic_resc; 645 attr->max_cq = qed_attr->max_cq; 646 attr->max_qp = qed_attr->max_qp; 647 attr->max_mr = qed_attr->max_mr; 648 attr->max_mr_size = qed_attr->max_mr_size; 649 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES); 650 attr->max_mw = qed_attr->max_mw; 651 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl; 652 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size; 653 attr->max_pd = qed_attr->max_pd; 654 attr->max_ah = qed_attr->max_ah; 655 attr->max_pkey = qed_attr->max_pkey; 656 attr->max_srq = qed_attr->max_srq; 657 attr->max_srq_wr = qed_attr->max_srq_wr; 658 attr->dev_caps = qed_attr->dev_caps; 659 attr->page_size_caps = qed_attr->page_size_caps; 660 attr->dev_ack_delay = qed_attr->dev_ack_delay; 661 attr->reserved_lkey = qed_attr->reserved_lkey; 662 attr->bad_pkey_counter = qed_attr->bad_pkey_counter; 663 attr->max_stats_queues = qed_attr->max_stats_queues; 664 665 return 0; 666} 667 668static void qedr_unaffiliated_event(void *context, u8 event_code) 669{ 670 pr_err("unaffiliated event not implemented yet\n"); 671} 672 673static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle) 674{ 675#define EVENT_TYPE_NOT_DEFINED 0 676#define EVENT_TYPE_CQ 1 677#define EVENT_TYPE_QP 2 678#define EVENT_TYPE_SRQ 3 679 struct qedr_dev *dev = (struct qedr_dev *)context; 680 struct regpair *async_handle = (struct regpair *)fw_handle; 681 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo; 682 u8 event_type = EVENT_TYPE_NOT_DEFINED; 683 struct ib_event event; 684 struct ib_srq *ibsrq; 685 struct qedr_srq *srq; 686 unsigned long flags; 687 struct ib_cq *ibcq; 688 struct ib_qp *ibqp; 689 struct qedr_cq *cq; 690 struct qedr_qp *qp; 691 u16 srq_id; 692 693 if (IS_ROCE(dev)) { 694 switch (e_code) { 695 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 696 event.event = IB_EVENT_CQ_ERR; 697 event_type = EVENT_TYPE_CQ; 698 break; 699 case ROCE_ASYNC_EVENT_SQ_DRAINED: 700 event.event = IB_EVENT_SQ_DRAINED; 701 event_type = EVENT_TYPE_QP; 702 break; 703 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 704 event.event = IB_EVENT_QP_FATAL; 705 event_type = EVENT_TYPE_QP; 706 break; 707 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 708 event.event = IB_EVENT_QP_REQ_ERR; 709 event_type = EVENT_TYPE_QP; 710 break; 711 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 712 event.event = IB_EVENT_QP_ACCESS_ERR; 713 event_type = EVENT_TYPE_QP; 714 break; 715 case ROCE_ASYNC_EVENT_SRQ_LIMIT: 716 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 717 event_type = EVENT_TYPE_SRQ; 718 break; 719 case ROCE_ASYNC_EVENT_SRQ_EMPTY: 720 event.event = IB_EVENT_SRQ_ERR; 721 event_type = EVENT_TYPE_SRQ; 722 break; 723 case ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR: 724 event.event = IB_EVENT_QP_ACCESS_ERR; 725 event_type = EVENT_TYPE_QP; 726 break; 727 case ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR: 728 event.event = IB_EVENT_QP_ACCESS_ERR; 729 event_type = EVENT_TYPE_QP; 730 break; 731 case ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR: 732 event.event = IB_EVENT_CQ_ERR; 733 event_type = EVENT_TYPE_CQ; 734 break; 735 default: 736 DP_ERR(dev, "unsupported event %d on handle=%llx\n", 737 e_code, roce_handle64); 738 } 739 } else { 740 switch (e_code) { 741 case QED_IWARP_EVENT_SRQ_LIMIT: 742 event.event = IB_EVENT_SRQ_LIMIT_REACHED; 743 event_type = EVENT_TYPE_SRQ; 744 break; 745 case QED_IWARP_EVENT_SRQ_EMPTY: 746 event.event = IB_EVENT_SRQ_ERR; 747 event_type = EVENT_TYPE_SRQ; 748 break; 749 default: 750 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code, 751 roce_handle64); 752 } 753 } 754 switch (event_type) { 755 case EVENT_TYPE_CQ: 756 cq = (struct qedr_cq *)(uintptr_t)roce_handle64; 757 if (cq) { 758 ibcq = &cq->ibcq; 759 if (ibcq->event_handler) { 760 event.device = ibcq->device; 761 event.element.cq = ibcq; 762 ibcq->event_handler(&event, ibcq->cq_context); 763 } 764 } else { 765 WARN(1, 766 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n", 767 roce_handle64); 768 } 769 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq); 770 break; 771 case EVENT_TYPE_QP: 772 qp = (struct qedr_qp *)(uintptr_t)roce_handle64; 773 if (qp) { 774 ibqp = &qp->ibqp; 775 if (ibqp->event_handler) { 776 event.device = ibqp->device; 777 event.element.qp = ibqp; 778 ibqp->event_handler(&event, ibqp->qp_context); 779 } 780 } else { 781 WARN(1, 782 "Error: QP event with NULL pointer ibqp. Handle=%llx\n", 783 roce_handle64); 784 } 785 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp); 786 break; 787 case EVENT_TYPE_SRQ: 788 srq_id = (u16)roce_handle64; 789 xa_lock_irqsave(&dev->srqs, flags); 790 srq = xa_load(&dev->srqs, srq_id); 791 if (srq) { 792 ibsrq = &srq->ibsrq; 793 if (ibsrq->event_handler) { 794 event.device = ibsrq->device; 795 event.element.srq = ibsrq; 796 ibsrq->event_handler(&event, 797 ibsrq->srq_context); 798 } 799 } else { 800 DP_NOTICE(dev, 801 "SRQ event with NULL pointer ibsrq. Handle=%llx\n", 802 roce_handle64); 803 } 804 xa_unlock_irqrestore(&dev->srqs, flags); 805 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq); 806 default: 807 break; 808 } 809} 810 811static int qedr_init_hw(struct qedr_dev *dev) 812{ 813 struct qed_rdma_add_user_out_params out_params; 814 struct qed_rdma_start_in_params *in_params; 815 struct qed_rdma_cnq_params *cur_pbl; 816 struct qed_rdma_events events; 817 dma_addr_t p_phys_table; 818 u32 page_cnt; 819 int rc = 0; 820 int i; 821 822 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 823 if (!in_params) { 824 rc = -ENOMEM; 825 goto out; 826 } 827 828 in_params->desired_cnq = dev->num_cnq; 829 for (i = 0; i < dev->num_cnq; i++) { 830 cur_pbl = &in_params->cnq_pbl_list[i]; 831 832 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl); 833 cur_pbl->num_pbl_pages = page_cnt; 834 835 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 836 cur_pbl->pbl_ptr = (u64)p_phys_table; 837 } 838 839 events.affiliated_event = qedr_affiliated_event; 840 events.unaffiliated_event = qedr_unaffiliated_event; 841 events.context = dev; 842 843 in_params->events = &events; 844 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS; 845 in_params->max_mtu = dev->ndev->mtu; 846 dev->iwarp_max_mtu = dev->ndev->mtu; 847 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr); 848 849 rc = dev->ops->rdma_init(dev->cdev, in_params); 850 if (rc) 851 goto out; 852 853 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params); 854 if (rc) 855 goto out; 856 857 dev->db_addr = out_params.dpi_addr; 858 dev->db_phys_addr = out_params.dpi_phys_addr; 859 dev->db_size = out_params.dpi_size; 860 dev->dpi = out_params.dpi; 861 862 rc = qedr_set_device_attr(dev); 863out: 864 kfree(in_params); 865 if (rc) 866 DP_ERR(dev, "Init HW Failed rc = %d\n", rc); 867 868 return rc; 869} 870 871static void qedr_stop_hw(struct qedr_dev *dev) 872{ 873 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi); 874 dev->ops->rdma_stop(dev->rdma_ctx); 875} 876 877static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev, 878 struct net_device *ndev) 879{ 880 struct qed_dev_rdma_info dev_info; 881 struct qedr_dev *dev; 882 int rc = 0; 883 884 dev = ib_alloc_device(qedr_dev, ibdev); 885 if (!dev) { 886 pr_err("Unable to allocate ib device\n"); 887 return NULL; 888 } 889 890 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n"); 891 892 dev->pdev = pdev; 893 dev->ndev = ndev; 894 dev->cdev = cdev; 895 896 qed_ops = qed_get_rdma_ops(); 897 if (!qed_ops) { 898 DP_ERR(dev, "Failed to get qed roce operations\n"); 899 goto init_err; 900 } 901 902 dev->ops = qed_ops; 903 rc = qed_ops->fill_dev_info(cdev, &dev_info); 904 if (rc) 905 goto init_err; 906 907 dev->user_dpm_enabled = dev_info.user_dpm_enabled; 908 dev->rdma_type = dev_info.rdma_type; 909 dev->num_hwfns = dev_info.common.num_hwfns; 910 911 if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) { 912 rc = dev->ops->iwarp_set_engine_affin(cdev, false); 913 if (rc) { 914 DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n"); 915 goto init_err; 916 } 917 } 918 dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev); 919 920 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev); 921 922 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev); 923 if (!dev->num_cnq) { 924 DP_ERR(dev, "Failed. At least one CNQ is required.\n"); 925 rc = -ENOMEM; 926 goto init_err; 927 } 928 929 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT; 930 931 qedr_pci_set_atomic(dev, pdev); 932 933 rc = qedr_alloc_resources(dev); 934 if (rc) 935 goto init_err; 936 937 rc = qedr_init_hw(dev); 938 if (rc) 939 goto alloc_err; 940 941 rc = qedr_setup_irqs(dev); 942 if (rc) 943 goto irq_err; 944 945 rc = qedr_register_device(dev); 946 if (rc) { 947 DP_ERR(dev, "Unable to allocate register device\n"); 948 goto reg_err; 949 } 950 951 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 952 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 953 954 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n"); 955 return dev; 956 957reg_err: 958 qedr_sync_free_irqs(dev); 959irq_err: 960 qedr_stop_hw(dev); 961alloc_err: 962 qedr_free_resources(dev); 963init_err: 964 ib_dealloc_device(&dev->ibdev); 965 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc); 966 967 return NULL; 968} 969 970static void qedr_remove(struct qedr_dev *dev) 971{ 972 /* First unregister with stack to stop all the active traffic 973 * of the registered clients. 974 */ 975 ib_unregister_device(&dev->ibdev); 976 977 qedr_stop_hw(dev); 978 qedr_sync_free_irqs(dev); 979 qedr_free_resources(dev); 980 981 if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) 982 dev->ops->iwarp_set_engine_affin(dev->cdev, true); 983 984 ib_dealloc_device(&dev->ibdev); 985} 986 987static void qedr_close(struct qedr_dev *dev) 988{ 989 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 990 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR); 991} 992 993static void qedr_shutdown(struct qedr_dev *dev) 994{ 995 qedr_close(dev); 996 qedr_remove(dev); 997} 998 999static void qedr_open(struct qedr_dev *dev) 1000{ 1001 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state)) 1002 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE); 1003} 1004 1005static void qedr_mac_address_change(struct qedr_dev *dev) 1006{ 1007 union ib_gid *sgid = &dev->sgid_tbl[0]; 1008 u8 guid[8], mac_addr[6]; 1009 int rc; 1010 1011 /* Update SGID */ 1012 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr); 1013 guid[0] = mac_addr[0] ^ 2; 1014 guid[1] = mac_addr[1]; 1015 guid[2] = mac_addr[2]; 1016 guid[3] = 0xff; 1017 guid[4] = 0xfe; 1018 guid[5] = mac_addr[3]; 1019 guid[6] = mac_addr[4]; 1020 guid[7] = mac_addr[5]; 1021 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL); 1022 memcpy(&sgid->raw[8], guid, sizeof(guid)); 1023 1024 /* Update LL2 */ 1025 rc = dev->ops->ll2_set_mac_filter(dev->cdev, 1026 dev->gsi_ll2_mac_address, 1027 dev->ndev->dev_addr); 1028 1029 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr); 1030 1031 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE); 1032 1033 if (rc) 1034 DP_ERR(dev, "Error updating mac filter\n"); 1035} 1036 1037/* event handling via NIC driver ensures that all the NIC specific 1038 * initialization done before RoCE driver notifies 1039 * event to stack. 1040 */ 1041static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event) 1042{ 1043 switch (event) { 1044 case QEDE_UP: 1045 qedr_open(dev); 1046 break; 1047 case QEDE_DOWN: 1048 qedr_close(dev); 1049 break; 1050 case QEDE_CLOSE: 1051 qedr_shutdown(dev); 1052 break; 1053 case QEDE_CHANGE_ADDR: 1054 qedr_mac_address_change(dev); 1055 break; 1056 case QEDE_CHANGE_MTU: 1057 if (rdma_protocol_iwarp(&dev->ibdev, 1)) 1058 if (dev->ndev->mtu != dev->iwarp_max_mtu) 1059 DP_NOTICE(dev, 1060 "Mtu was changed from %d to %d. This will not take affect for iWARP until qedr is reloaded\n", 1061 dev->iwarp_max_mtu, dev->ndev->mtu); 1062 break; 1063 default: 1064 pr_err("Event not supported\n"); 1065 } 1066} 1067 1068static struct qedr_driver qedr_drv = { 1069 .name = "qedr_driver", 1070 .add = qedr_add, 1071 .remove = qedr_remove, 1072 .notify = qedr_notify, 1073}; 1074 1075static int __init qedr_init_module(void) 1076{ 1077 return qede_rdma_register_driver(&qedr_drv); 1078} 1079 1080static void __exit qedr_exit_module(void) 1081{ 1082 qede_rdma_unregister_driver(&qedr_drv); 1083} 1084 1085module_init(qedr_init_module); 1086module_exit(qedr_exit_module); 1087