1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2/* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 */ 5 6#include <linux/debugfs.h> 7#include <linux/highmem.h> 8#include <linux/module.h> 9#include <linux/init.h> 10#include <linux/errno.h> 11#include <linux/pci.h> 12#include <linux/dma-mapping.h> 13#include <linux/slab.h> 14#include <linux/bitmap.h> 15#include <linux/sched.h> 16#include <linux/sched/mm.h> 17#include <linux/sched/task.h> 18#include <linux/delay.h> 19#include <rdma/ib_user_verbs.h> 20#include <rdma/ib_addr.h> 21#include <rdma/ib_cache.h> 22#include <linux/mlx5/port.h> 23#include <linux/mlx5/vport.h> 24#include <linux/mlx5/fs.h> 25#include <linux/mlx5/eswitch.h> 26#include <linux/list.h> 27#include <rdma/ib_smi.h> 28#include <rdma/ib_umem.h> 29#include <rdma/lag.h> 30#include <linux/in.h> 31#include <linux/etherdevice.h> 32#include "mlx5_ib.h" 33#include "ib_rep.h" 34#include "cmd.h" 35#include "devx.h" 36#include "fs.h" 37#include "srq.h" 38#include "qp.h" 39#include "wr.h" 40#include "restrack.h" 41#include "counters.h" 42#include <linux/mlx5/accel.h> 43#include <rdma/uverbs_std_types.h> 44#include <rdma/mlx5_user_ioctl_verbs.h> 45#include <rdma/mlx5_user_ioctl_cmds.h> 46#include <rdma/ib_umem_odp.h> 47 48#define UVERBS_MODULE_NAME mlx5_ib 49#include <rdma/uverbs_named_ioctl.h> 50 51MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 52MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 53MODULE_LICENSE("Dual BSD/GPL"); 54 55struct mlx5_ib_event_work { 56 struct work_struct work; 57 union { 58 struct mlx5_ib_dev *dev; 59 struct mlx5_ib_multiport_info *mpi; 60 }; 61 bool is_slave; 62 unsigned int event; 63 void *param; 64}; 65 66enum { 67 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 68}; 69 70static struct workqueue_struct *mlx5_ib_event_wq; 71static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 72static LIST_HEAD(mlx5_ib_dev_list); 73/* 74 * This mutex should be held when accessing either of the above lists 75 */ 76static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 77 78/* We can't use an array for xlt_emergency_page because dma_map_single 79 * doesn't work on kernel modules memory 80 */ 81static unsigned long xlt_emergency_page; 82static struct mutex xlt_emergency_page_mutex; 83 84struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 85{ 86 struct mlx5_ib_dev *dev; 87 88 mutex_lock(&mlx5_ib_multiport_mutex); 89 dev = mpi->ibdev; 90 mutex_unlock(&mlx5_ib_multiport_mutex); 91 return dev; 92} 93 94static enum rdma_link_layer 95mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 96{ 97 switch (port_type_cap) { 98 case MLX5_CAP_PORT_TYPE_IB: 99 return IB_LINK_LAYER_INFINIBAND; 100 case MLX5_CAP_PORT_TYPE_ETH: 101 return IB_LINK_LAYER_ETHERNET; 102 default: 103 return IB_LINK_LAYER_UNSPECIFIED; 104 } 105} 106 107static enum rdma_link_layer 108mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 109{ 110 struct mlx5_ib_dev *dev = to_mdev(device); 111 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 112 113 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 114} 115 116static int get_port_state(struct ib_device *ibdev, 117 u8 port_num, 118 enum ib_port_state *state) 119{ 120 struct ib_port_attr attr; 121 int ret; 122 123 memset(&attr, 0, sizeof(attr)); 124 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 125 if (!ret) 126 *state = attr.state; 127 return ret; 128} 129 130static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 131 struct net_device *ndev, 132 u8 *port_num) 133{ 134 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 135 struct net_device *rep_ndev; 136 struct mlx5_ib_port *port; 137 int i; 138 139 for (i = 0; i < dev->num_ports; i++) { 140 port = &dev->port[i]; 141 if (!port->rep) 142 continue; 143 144 read_lock(&port->roce.netdev_lock); 145 rep_ndev = mlx5_ib_get_rep_netdev(esw, 146 port->rep->vport); 147 if (rep_ndev == ndev) { 148 read_unlock(&port->roce.netdev_lock); 149 *port_num = i + 1; 150 return &port->roce; 151 } 152 read_unlock(&port->roce.netdev_lock); 153 } 154 155 return NULL; 156} 157 158static int mlx5_netdev_event(struct notifier_block *this, 159 unsigned long event, void *ptr) 160{ 161 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 162 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 163 u8 port_num = roce->native_port_num; 164 struct mlx5_core_dev *mdev; 165 struct mlx5_ib_dev *ibdev; 166 167 ibdev = roce->dev; 168 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 169 if (!mdev) 170 return NOTIFY_DONE; 171 172 switch (event) { 173 case NETDEV_REGISTER: 174 /* Should already be registered during the load */ 175 if (ibdev->is_rep) 176 break; 177 write_lock(&roce->netdev_lock); 178 if (ndev->dev.parent == mdev->device) 179 roce->netdev = ndev; 180 write_unlock(&roce->netdev_lock); 181 break; 182 183 case NETDEV_UNREGISTER: 184 /* In case of reps, ib device goes away before the netdevs */ 185 write_lock(&roce->netdev_lock); 186 if (roce->netdev == ndev) 187 roce->netdev = NULL; 188 write_unlock(&roce->netdev_lock); 189 break; 190 191 case NETDEV_CHANGE: 192 case NETDEV_UP: 193 case NETDEV_DOWN: { 194 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 195 struct net_device *upper = NULL; 196 197 if (lag_ndev) { 198 upper = netdev_master_upper_dev_get(lag_ndev); 199 dev_put(lag_ndev); 200 } 201 202 if (ibdev->is_rep) 203 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 204 if (!roce) 205 return NOTIFY_DONE; 206 if ((upper == ndev || (!upper && ndev == roce->netdev)) 207 && ibdev->ib_active) { 208 struct ib_event ibev = { }; 209 enum ib_port_state port_state; 210 211 if (get_port_state(&ibdev->ib_dev, port_num, 212 &port_state)) 213 goto done; 214 215 if (roce->last_port_state == port_state) 216 goto done; 217 218 roce->last_port_state = port_state; 219 ibev.device = &ibdev->ib_dev; 220 if (port_state == IB_PORT_DOWN) 221 ibev.event = IB_EVENT_PORT_ERR; 222 else if (port_state == IB_PORT_ACTIVE) 223 ibev.event = IB_EVENT_PORT_ACTIVE; 224 else 225 goto done; 226 227 ibev.element.port_num = port_num; 228 ib_dispatch_event(&ibev); 229 } 230 break; 231 } 232 233 default: 234 break; 235 } 236done: 237 mlx5_ib_put_native_port_mdev(ibdev, port_num); 238 return NOTIFY_DONE; 239} 240 241static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 242 u8 port_num) 243{ 244 struct mlx5_ib_dev *ibdev = to_mdev(device); 245 struct net_device *ndev; 246 struct mlx5_core_dev *mdev; 247 248 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 249 if (!mdev) 250 return NULL; 251 252 ndev = mlx5_lag_get_roce_netdev(mdev); 253 if (ndev) 254 goto out; 255 256 /* Ensure ndev does not disappear before we invoke dev_hold() 257 */ 258 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 259 ndev = ibdev->port[port_num - 1].roce.netdev; 260 if (ndev) 261 dev_hold(ndev); 262 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 263 264out: 265 mlx5_ib_put_native_port_mdev(ibdev, port_num); 266 return ndev; 267} 268 269struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 270 u8 ib_port_num, 271 u8 *native_port_num) 272{ 273 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 274 ib_port_num); 275 struct mlx5_core_dev *mdev = NULL; 276 struct mlx5_ib_multiport_info *mpi; 277 struct mlx5_ib_port *port; 278 279 if (!mlx5_core_mp_enabled(ibdev->mdev) || 280 ll != IB_LINK_LAYER_ETHERNET) { 281 if (native_port_num) 282 *native_port_num = ib_port_num; 283 return ibdev->mdev; 284 } 285 286 if (native_port_num) 287 *native_port_num = 1; 288 289 port = &ibdev->port[ib_port_num - 1]; 290 spin_lock(&port->mp.mpi_lock); 291 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 292 if (mpi && !mpi->unaffiliate) { 293 mdev = mpi->mdev; 294 /* If it's the master no need to refcount, it'll exist 295 * as long as the ib_dev exists. 296 */ 297 if (!mpi->is_master) 298 mpi->mdev_refcnt++; 299 } 300 spin_unlock(&port->mp.mpi_lock); 301 302 return mdev; 303} 304 305void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 306{ 307 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 308 port_num); 309 struct mlx5_ib_multiport_info *mpi; 310 struct mlx5_ib_port *port; 311 312 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 313 return; 314 315 port = &ibdev->port[port_num - 1]; 316 317 spin_lock(&port->mp.mpi_lock); 318 mpi = ibdev->port[port_num - 1].mp.mpi; 319 if (mpi->is_master) 320 goto out; 321 322 mpi->mdev_refcnt--; 323 if (mpi->unaffiliate) 324 complete(&mpi->unref_comp); 325out: 326 spin_unlock(&port->mp.mpi_lock); 327} 328 329static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 330 u16 *active_speed, u8 *active_width) 331{ 332 switch (eth_proto_oper) { 333 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 334 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 335 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 336 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 337 *active_width = IB_WIDTH_1X; 338 *active_speed = IB_SPEED_SDR; 339 break; 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 344 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 345 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 347 *active_width = IB_WIDTH_1X; 348 *active_speed = IB_SPEED_QDR; 349 break; 350 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 351 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 352 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 353 *active_width = IB_WIDTH_1X; 354 *active_speed = IB_SPEED_EDR; 355 break; 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 357 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 358 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 359 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 360 *active_width = IB_WIDTH_4X; 361 *active_speed = IB_SPEED_QDR; 362 break; 363 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 364 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 365 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 366 *active_width = IB_WIDTH_1X; 367 *active_speed = IB_SPEED_HDR; 368 break; 369 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 370 *active_width = IB_WIDTH_4X; 371 *active_speed = IB_SPEED_FDR; 372 break; 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 374 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 375 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 376 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 377 *active_width = IB_WIDTH_4X; 378 *active_speed = IB_SPEED_EDR; 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 return 0; 385} 386 387static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 388 u8 *active_width) 389{ 390 switch (eth_proto_oper) { 391 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 392 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 393 *active_width = IB_WIDTH_1X; 394 *active_speed = IB_SPEED_SDR; 395 break; 396 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 397 *active_width = IB_WIDTH_1X; 398 *active_speed = IB_SPEED_DDR; 399 break; 400 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 401 *active_width = IB_WIDTH_1X; 402 *active_speed = IB_SPEED_QDR; 403 break; 404 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 405 *active_width = IB_WIDTH_4X; 406 *active_speed = IB_SPEED_QDR; 407 break; 408 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 409 *active_width = IB_WIDTH_1X; 410 *active_speed = IB_SPEED_EDR; 411 break; 412 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 413 *active_width = IB_WIDTH_2X; 414 *active_speed = IB_SPEED_EDR; 415 break; 416 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 417 *active_width = IB_WIDTH_1X; 418 *active_speed = IB_SPEED_HDR; 419 break; 420 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 421 *active_width = IB_WIDTH_4X; 422 *active_speed = IB_SPEED_EDR; 423 break; 424 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 425 *active_width = IB_WIDTH_2X; 426 *active_speed = IB_SPEED_HDR; 427 break; 428 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 429 *active_width = IB_WIDTH_1X; 430 *active_speed = IB_SPEED_NDR; 431 break; 432 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 433 *active_width = IB_WIDTH_4X; 434 *active_speed = IB_SPEED_HDR; 435 break; 436 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 437 *active_width = IB_WIDTH_2X; 438 *active_speed = IB_SPEED_NDR; 439 break; 440 case MLX5E_PROT_MASK(MLX5E_400GAUI_8): 441 *active_width = IB_WIDTH_8X; 442 *active_speed = IB_SPEED_HDR; 443 break; 444 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 445 *active_width = IB_WIDTH_4X; 446 *active_speed = IB_SPEED_NDR; 447 break; 448 default: 449 return -EINVAL; 450 } 451 452 return 0; 453} 454 455static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 456 u8 *active_width, bool ext) 457{ 458 return ext ? 459 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 460 active_width) : 461 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 462 active_width); 463} 464 465static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 466 struct ib_port_attr *props) 467{ 468 struct mlx5_ib_dev *dev = to_mdev(device); 469 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 470 struct mlx5_core_dev *mdev; 471 struct net_device *ndev, *upper; 472 enum ib_mtu ndev_ib_mtu; 473 bool put_mdev = true; 474 u16 qkey_viol_cntr; 475 u32 eth_prot_oper; 476 u8 mdev_port_num; 477 bool ext; 478 int err; 479 480 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 481 if (!mdev) { 482 /* This means the port isn't affiliated yet. Get the 483 * info for the master port instead. 484 */ 485 put_mdev = false; 486 mdev = dev->mdev; 487 mdev_port_num = 1; 488 port_num = 1; 489 } 490 491 /* Possible bad flows are checked before filling out props so in case 492 * of an error it will still be zeroed out. 493 * Use native port in case of reps 494 */ 495 if (dev->is_rep) 496 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 497 1); 498 else 499 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 500 mdev_port_num); 501 if (err) 502 goto out; 503 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 504 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 505 506 props->active_width = IB_WIDTH_4X; 507 props->active_speed = IB_SPEED_QDR; 508 509 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 510 &props->active_width, ext); 511 512 props->port_cap_flags |= IB_PORT_CM_SUP; 513 props->ip_gids = true; 514 515 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 516 roce_address_table_size); 517 props->max_mtu = IB_MTU_4096; 518 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 519 props->pkey_tbl_len = 1; 520 props->state = IB_PORT_DOWN; 521 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 522 523 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 524 props->qkey_viol_cntr = qkey_viol_cntr; 525 526 /* If this is a stub query for an unaffiliated port stop here */ 527 if (!put_mdev) 528 goto out; 529 530 ndev = mlx5_ib_get_netdev(device, port_num); 531 if (!ndev) 532 goto out; 533 534 if (dev->lag_active) { 535 rcu_read_lock(); 536 upper = netdev_master_upper_dev_get_rcu(ndev); 537 if (upper) { 538 dev_put(ndev); 539 ndev = upper; 540 dev_hold(ndev); 541 } 542 rcu_read_unlock(); 543 } 544 545 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 546 props->state = IB_PORT_ACTIVE; 547 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 548 } 549 550 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 551 552 dev_put(ndev); 553 554 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 555out: 556 if (put_mdev) 557 mlx5_ib_put_native_port_mdev(dev, port_num); 558 return err; 559} 560 561static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 562 unsigned int index, const union ib_gid *gid, 563 const struct ib_gid_attr *attr) 564{ 565 enum ib_gid_type gid_type = IB_GID_TYPE_ROCE; 566 u16 vlan_id = 0xffff; 567 u8 roce_version = 0; 568 u8 roce_l3_type = 0; 569 u8 mac[ETH_ALEN]; 570 int ret; 571 572 if (gid) { 573 gid_type = attr->gid_type; 574 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 575 if (ret) 576 return ret; 577 } 578 579 switch (gid_type) { 580 case IB_GID_TYPE_ROCE: 581 roce_version = MLX5_ROCE_VERSION_1; 582 break; 583 case IB_GID_TYPE_ROCE_UDP_ENCAP: 584 roce_version = MLX5_ROCE_VERSION_2; 585 if (ipv6_addr_v4mapped((void *)gid)) 586 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 587 else 588 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 589 break; 590 591 default: 592 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 593 } 594 595 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 596 roce_l3_type, gid->raw, mac, 597 vlan_id < VLAN_CFI_MASK, vlan_id, 598 port_num); 599} 600 601static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 602 __always_unused void **context) 603{ 604 return set_roce_addr(to_mdev(attr->device), attr->port_num, 605 attr->index, &attr->gid, attr); 606} 607 608static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 609 __always_unused void **context) 610{ 611 return set_roce_addr(to_mdev(attr->device), attr->port_num, 612 attr->index, NULL, NULL); 613} 614 615__be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 616 const struct ib_gid_attr *attr) 617{ 618 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 619 return 0; 620 621 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 622} 623 624static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 625{ 626 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 627 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 628 return 0; 629} 630 631enum { 632 MLX5_VPORT_ACCESS_METHOD_MAD, 633 MLX5_VPORT_ACCESS_METHOD_HCA, 634 MLX5_VPORT_ACCESS_METHOD_NIC, 635}; 636 637static int mlx5_get_vport_access_method(struct ib_device *ibdev) 638{ 639 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 640 return MLX5_VPORT_ACCESS_METHOD_MAD; 641 642 if (mlx5_ib_port_link_layer(ibdev, 1) == 643 IB_LINK_LAYER_ETHERNET) 644 return MLX5_VPORT_ACCESS_METHOD_NIC; 645 646 return MLX5_VPORT_ACCESS_METHOD_HCA; 647} 648 649static void get_atomic_caps(struct mlx5_ib_dev *dev, 650 u8 atomic_size_qp, 651 struct ib_device_attr *props) 652{ 653 u8 tmp; 654 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 655 u8 atomic_req_8B_endianness_mode = 656 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 657 658 /* Check if HW supports 8 bytes standard atomic operations and capable 659 * of host endianness respond 660 */ 661 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 662 if (((atomic_operations & tmp) == tmp) && 663 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 664 (atomic_req_8B_endianness_mode)) { 665 props->atomic_cap = IB_ATOMIC_HCA; 666 } else { 667 props->atomic_cap = IB_ATOMIC_NONE; 668 } 669} 670 671static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 672 struct ib_device_attr *props) 673{ 674 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 675 676 get_atomic_caps(dev, atomic_size_qp, props); 677} 678 679static int mlx5_query_system_image_guid(struct ib_device *ibdev, 680 __be64 *sys_image_guid) 681{ 682 struct mlx5_ib_dev *dev = to_mdev(ibdev); 683 struct mlx5_core_dev *mdev = dev->mdev; 684 u64 tmp; 685 int err; 686 687 switch (mlx5_get_vport_access_method(ibdev)) { 688 case MLX5_VPORT_ACCESS_METHOD_MAD: 689 return mlx5_query_mad_ifc_system_image_guid(ibdev, 690 sys_image_guid); 691 692 case MLX5_VPORT_ACCESS_METHOD_HCA: 693 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 694 break; 695 696 case MLX5_VPORT_ACCESS_METHOD_NIC: 697 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 698 break; 699 700 default: 701 return -EINVAL; 702 } 703 704 if (!err) 705 *sys_image_guid = cpu_to_be64(tmp); 706 707 return err; 708 709} 710 711static int mlx5_query_max_pkeys(struct ib_device *ibdev, 712 u16 *max_pkeys) 713{ 714 struct mlx5_ib_dev *dev = to_mdev(ibdev); 715 struct mlx5_core_dev *mdev = dev->mdev; 716 717 switch (mlx5_get_vport_access_method(ibdev)) { 718 case MLX5_VPORT_ACCESS_METHOD_MAD: 719 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 720 721 case MLX5_VPORT_ACCESS_METHOD_HCA: 722 case MLX5_VPORT_ACCESS_METHOD_NIC: 723 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 724 pkey_table_size)); 725 return 0; 726 727 default: 728 return -EINVAL; 729 } 730} 731 732static int mlx5_query_vendor_id(struct ib_device *ibdev, 733 u32 *vendor_id) 734{ 735 struct mlx5_ib_dev *dev = to_mdev(ibdev); 736 737 switch (mlx5_get_vport_access_method(ibdev)) { 738 case MLX5_VPORT_ACCESS_METHOD_MAD: 739 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 740 741 case MLX5_VPORT_ACCESS_METHOD_HCA: 742 case MLX5_VPORT_ACCESS_METHOD_NIC: 743 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 744 745 default: 746 return -EINVAL; 747 } 748} 749 750static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 751 __be64 *node_guid) 752{ 753 u64 tmp; 754 int err; 755 756 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 757 case MLX5_VPORT_ACCESS_METHOD_MAD: 758 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 759 760 case MLX5_VPORT_ACCESS_METHOD_HCA: 761 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 762 break; 763 764 case MLX5_VPORT_ACCESS_METHOD_NIC: 765 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 766 break; 767 768 default: 769 return -EINVAL; 770 } 771 772 if (!err) 773 *node_guid = cpu_to_be64(tmp); 774 775 return err; 776} 777 778struct mlx5_reg_node_desc { 779 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 780}; 781 782static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 783{ 784 struct mlx5_reg_node_desc in; 785 786 if (mlx5_use_mad_ifc(dev)) 787 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 788 789 memset(&in, 0, sizeof(in)); 790 791 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 792 sizeof(struct mlx5_reg_node_desc), 793 MLX5_REG_NODE_DESC, 0, 0); 794} 795 796static int mlx5_ib_query_device(struct ib_device *ibdev, 797 struct ib_device_attr *props, 798 struct ib_udata *uhw) 799{ 800 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 801 struct mlx5_ib_dev *dev = to_mdev(ibdev); 802 struct mlx5_core_dev *mdev = dev->mdev; 803 int err = -ENOMEM; 804 int max_sq_desc; 805 int max_rq_sg; 806 int max_sq_sg; 807 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 808 bool raw_support = !mlx5_core_mp_enabled(mdev); 809 struct mlx5_ib_query_device_resp resp = {}; 810 size_t resp_len; 811 u64 max_tso; 812 813 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 814 if (uhw_outlen && uhw_outlen < resp_len) 815 return -EINVAL; 816 817 resp.response_length = resp_len; 818 819 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 820 return -EINVAL; 821 822 memset(props, 0, sizeof(*props)); 823 err = mlx5_query_system_image_guid(ibdev, 824 &props->sys_image_guid); 825 if (err) 826 return err; 827 828 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 829 if (err) 830 return err; 831 832 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 833 if (err) 834 return err; 835 836 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 837 (fw_rev_min(dev->mdev) << 16) | 838 fw_rev_sub(dev->mdev); 839 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 840 IB_DEVICE_PORT_ACTIVE_EVENT | 841 IB_DEVICE_SYS_IMAGE_GUID | 842 IB_DEVICE_RC_RNR_NAK_GEN; 843 844 if (MLX5_CAP_GEN(mdev, pkv)) 845 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 846 if (MLX5_CAP_GEN(mdev, qkv)) 847 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 848 if (MLX5_CAP_GEN(mdev, apm)) 849 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 850 if (MLX5_CAP_GEN(mdev, xrc)) 851 props->device_cap_flags |= IB_DEVICE_XRC; 852 if (MLX5_CAP_GEN(mdev, imaicl)) { 853 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 854 IB_DEVICE_MEM_WINDOW_TYPE_2B; 855 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 856 /* We support 'Gappy' memory registration too */ 857 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 858 } 859 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 860 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 861 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 862 if (MLX5_CAP_GEN(mdev, sho)) { 863 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 864 /* At this stage no support for signature handover */ 865 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 866 IB_PROT_T10DIF_TYPE_2 | 867 IB_PROT_T10DIF_TYPE_3; 868 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 869 IB_GUARD_T10DIF_CSUM; 870 } 871 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 872 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 873 874 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 875 if (MLX5_CAP_ETH(mdev, csum_cap)) { 876 /* Legacy bit to support old userspace libraries */ 877 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 878 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 879 } 880 881 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 882 props->raw_packet_caps |= 883 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 884 885 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 886 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 887 if (max_tso) { 888 resp.tso_caps.max_tso = 1 << max_tso; 889 resp.tso_caps.supported_qpts |= 890 1 << IB_QPT_RAW_PACKET; 891 resp.response_length += sizeof(resp.tso_caps); 892 } 893 } 894 895 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 896 resp.rss_caps.rx_hash_function = 897 MLX5_RX_HASH_FUNC_TOEPLITZ; 898 resp.rss_caps.rx_hash_fields_mask = 899 MLX5_RX_HASH_SRC_IPV4 | 900 MLX5_RX_HASH_DST_IPV4 | 901 MLX5_RX_HASH_SRC_IPV6 | 902 MLX5_RX_HASH_DST_IPV6 | 903 MLX5_RX_HASH_SRC_PORT_TCP | 904 MLX5_RX_HASH_DST_PORT_TCP | 905 MLX5_RX_HASH_SRC_PORT_UDP | 906 MLX5_RX_HASH_DST_PORT_UDP | 907 MLX5_RX_HASH_INNER; 908 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 909 MLX5_ACCEL_IPSEC_CAP_DEVICE) 910 resp.rss_caps.rx_hash_fields_mask |= 911 MLX5_RX_HASH_IPSEC_SPI; 912 resp.response_length += sizeof(resp.rss_caps); 913 } 914 } else { 915 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 916 resp.response_length += sizeof(resp.tso_caps); 917 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 918 resp.response_length += sizeof(resp.rss_caps); 919 } 920 921 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 922 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 923 props->device_cap_flags |= IB_DEVICE_UD_TSO; 924 } 925 926 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 927 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 928 raw_support) 929 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 930 931 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 932 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 933 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 934 935 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 936 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 937 raw_support) { 938 /* Legacy bit to support old userspace libraries */ 939 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 940 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 941 } 942 943 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 944 props->max_dm_size = 945 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 946 } 947 948 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 949 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 950 951 if (MLX5_CAP_GEN(mdev, end_pad)) 952 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 953 954 props->vendor_part_id = mdev->pdev->device; 955 props->hw_ver = mdev->pdev->revision; 956 957 props->max_mr_size = ~0ull; 958 props->page_size_cap = ~(min_page_size - 1); 959 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 960 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 961 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 962 sizeof(struct mlx5_wqe_data_seg); 963 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 964 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 965 sizeof(struct mlx5_wqe_raddr_seg)) / 966 sizeof(struct mlx5_wqe_data_seg); 967 props->max_send_sge = max_sq_sg; 968 props->max_recv_sge = max_rq_sg; 969 props->max_sge_rd = MLX5_MAX_SGE_RD; 970 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 971 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 972 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 973 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 974 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 975 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 976 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 977 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 978 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 979 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 980 props->max_srq_sge = max_rq_sg - 1; 981 props->max_fast_reg_page_list_len = 982 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 983 props->max_pi_fast_reg_page_list_len = 984 props->max_fast_reg_page_list_len / 2; 985 props->max_sgl_rd = 986 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 987 get_atomic_caps_qp(dev, props); 988 props->masked_atomic_cap = IB_ATOMIC_NONE; 989 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 990 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 991 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 992 props->max_mcast_grp; 993 props->max_ah = INT_MAX; 994 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 995 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 996 997 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 998 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 999 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 1000 props->odp_caps = dev->odp_caps; 1001 if (!uhw) { 1002 /* ODP for kernel QPs is not implemented for receive 1003 * WQEs and SRQ WQEs 1004 */ 1005 props->odp_caps.per_transport_caps.rc_odp_caps &= 1006 ~(IB_ODP_SUPPORT_READ | 1007 IB_ODP_SUPPORT_SRQ_RECV); 1008 props->odp_caps.per_transport_caps.uc_odp_caps &= 1009 ~(IB_ODP_SUPPORT_READ | 1010 IB_ODP_SUPPORT_SRQ_RECV); 1011 props->odp_caps.per_transport_caps.ud_odp_caps &= 1012 ~(IB_ODP_SUPPORT_READ | 1013 IB_ODP_SUPPORT_SRQ_RECV); 1014 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1015 ~(IB_ODP_SUPPORT_READ | 1016 IB_ODP_SUPPORT_SRQ_RECV); 1017 } 1018 } 1019 1020 if (MLX5_CAP_GEN(mdev, cd)) 1021 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1022 1023 if (mlx5_core_is_vf(mdev)) 1024 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1025 1026 if (mlx5_ib_port_link_layer(ibdev, 1) == 1027 IB_LINK_LAYER_ETHERNET && raw_support) { 1028 props->rss_caps.max_rwq_indirection_tables = 1029 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1030 props->rss_caps.max_rwq_indirection_table_size = 1031 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1032 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1033 props->max_wq_type_rq = 1034 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1035 } 1036 1037 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1038 props->tm_caps.max_num_tags = 1039 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1040 props->tm_caps.max_ops = 1041 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1042 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1043 } 1044 1045 if (MLX5_CAP_GEN(mdev, tag_matching) && 1046 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1047 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1048 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1049 } 1050 1051 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1052 props->cq_caps.max_cq_moderation_count = 1053 MLX5_MAX_CQ_COUNT; 1054 props->cq_caps.max_cq_moderation_period = 1055 MLX5_MAX_CQ_PERIOD; 1056 } 1057 1058 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1059 resp.response_length += sizeof(resp.cqe_comp_caps); 1060 1061 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1062 resp.cqe_comp_caps.max_num = 1063 MLX5_CAP_GEN(dev->mdev, 1064 cqe_compression_max_num); 1065 1066 resp.cqe_comp_caps.supported_format = 1067 MLX5_IB_CQE_RES_FORMAT_HASH | 1068 MLX5_IB_CQE_RES_FORMAT_CSUM; 1069 1070 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1071 resp.cqe_comp_caps.supported_format |= 1072 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1073 } 1074 } 1075 1076 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1077 raw_support) { 1078 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1079 MLX5_CAP_GEN(mdev, qos)) { 1080 resp.packet_pacing_caps.qp_rate_limit_max = 1081 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1082 resp.packet_pacing_caps.qp_rate_limit_min = 1083 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1084 resp.packet_pacing_caps.supported_qpts |= 1085 1 << IB_QPT_RAW_PACKET; 1086 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1087 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1088 resp.packet_pacing_caps.cap_flags |= 1089 MLX5_IB_PP_SUPPORT_BURST; 1090 } 1091 resp.response_length += sizeof(resp.packet_pacing_caps); 1092 } 1093 1094 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1095 uhw_outlen) { 1096 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1097 resp.mlx5_ib_support_multi_pkt_send_wqes = 1098 MLX5_IB_ALLOW_MPW; 1099 1100 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1101 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1102 MLX5_IB_SUPPORT_EMPW; 1103 1104 resp.response_length += 1105 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1106 } 1107 1108 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1109 resp.response_length += sizeof(resp.flags); 1110 1111 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1112 resp.flags |= 1113 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1114 1115 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1116 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1117 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1118 resp.flags |= 1119 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1120 1121 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1122 } 1123 1124 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1125 resp.response_length += sizeof(resp.sw_parsing_caps); 1126 if (MLX5_CAP_ETH(mdev, swp)) { 1127 resp.sw_parsing_caps.sw_parsing_offloads |= 1128 MLX5_IB_SW_PARSING; 1129 1130 if (MLX5_CAP_ETH(mdev, swp_csum)) 1131 resp.sw_parsing_caps.sw_parsing_offloads |= 1132 MLX5_IB_SW_PARSING_CSUM; 1133 1134 if (MLX5_CAP_ETH(mdev, swp_lso)) 1135 resp.sw_parsing_caps.sw_parsing_offloads |= 1136 MLX5_IB_SW_PARSING_LSO; 1137 1138 if (resp.sw_parsing_caps.sw_parsing_offloads) 1139 resp.sw_parsing_caps.supported_qpts = 1140 BIT(IB_QPT_RAW_PACKET); 1141 } 1142 } 1143 1144 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1145 raw_support) { 1146 resp.response_length += sizeof(resp.striding_rq_caps); 1147 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1148 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1149 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1150 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1151 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1152 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1153 resp.striding_rq_caps 1154 .min_single_wqe_log_num_of_strides = 1155 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1156 else 1157 resp.striding_rq_caps 1158 .min_single_wqe_log_num_of_strides = 1159 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1160 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1161 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1162 resp.striding_rq_caps.supported_qpts = 1163 BIT(IB_QPT_RAW_PACKET); 1164 } 1165 } 1166 1167 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1168 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1170 resp.tunnel_offloads_caps |= 1171 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1173 resp.tunnel_offloads_caps |= 1174 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1175 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1176 resp.tunnel_offloads_caps |= 1177 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1178 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1179 resp.tunnel_offloads_caps |= 1180 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1181 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1182 resp.tunnel_offloads_caps |= 1183 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1184 } 1185 1186 if (uhw_outlen) { 1187 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1188 1189 if (err) 1190 return err; 1191 } 1192 1193 return 0; 1194} 1195 1196static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1197 u8 *ib_width) 1198{ 1199 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1200 1201 if (active_width & MLX5_PTYS_WIDTH_1X) 1202 *ib_width = IB_WIDTH_1X; 1203 else if (active_width & MLX5_PTYS_WIDTH_2X) 1204 *ib_width = IB_WIDTH_2X; 1205 else if (active_width & MLX5_PTYS_WIDTH_4X) 1206 *ib_width = IB_WIDTH_4X; 1207 else if (active_width & MLX5_PTYS_WIDTH_8X) 1208 *ib_width = IB_WIDTH_8X; 1209 else if (active_width & MLX5_PTYS_WIDTH_12X) 1210 *ib_width = IB_WIDTH_12X; 1211 else { 1212 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1213 active_width); 1214 *ib_width = IB_WIDTH_4X; 1215 } 1216 1217 return; 1218} 1219 1220static int mlx5_mtu_to_ib_mtu(int mtu) 1221{ 1222 switch (mtu) { 1223 case 256: return 1; 1224 case 512: return 2; 1225 case 1024: return 3; 1226 case 2048: return 4; 1227 case 4096: return 5; 1228 default: 1229 pr_warn("invalid mtu\n"); 1230 return -1; 1231 } 1232} 1233 1234enum ib_max_vl_num { 1235 __IB_MAX_VL_0 = 1, 1236 __IB_MAX_VL_0_1 = 2, 1237 __IB_MAX_VL_0_3 = 3, 1238 __IB_MAX_VL_0_7 = 4, 1239 __IB_MAX_VL_0_14 = 5, 1240}; 1241 1242enum mlx5_vl_hw_cap { 1243 MLX5_VL_HW_0 = 1, 1244 MLX5_VL_HW_0_1 = 2, 1245 MLX5_VL_HW_0_2 = 3, 1246 MLX5_VL_HW_0_3 = 4, 1247 MLX5_VL_HW_0_4 = 5, 1248 MLX5_VL_HW_0_5 = 6, 1249 MLX5_VL_HW_0_6 = 7, 1250 MLX5_VL_HW_0_7 = 8, 1251 MLX5_VL_HW_0_14 = 15 1252}; 1253 1254static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1255 u8 *max_vl_num) 1256{ 1257 switch (vl_hw_cap) { 1258 case MLX5_VL_HW_0: 1259 *max_vl_num = __IB_MAX_VL_0; 1260 break; 1261 case MLX5_VL_HW_0_1: 1262 *max_vl_num = __IB_MAX_VL_0_1; 1263 break; 1264 case MLX5_VL_HW_0_3: 1265 *max_vl_num = __IB_MAX_VL_0_3; 1266 break; 1267 case MLX5_VL_HW_0_7: 1268 *max_vl_num = __IB_MAX_VL_0_7; 1269 break; 1270 case MLX5_VL_HW_0_14: 1271 *max_vl_num = __IB_MAX_VL_0_14; 1272 break; 1273 1274 default: 1275 return -EINVAL; 1276 } 1277 1278 return 0; 1279} 1280 1281static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1282 struct ib_port_attr *props) 1283{ 1284 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1285 struct mlx5_core_dev *mdev = dev->mdev; 1286 struct mlx5_hca_vport_context *rep; 1287 u16 max_mtu; 1288 u16 oper_mtu; 1289 int err; 1290 u16 ib_link_width_oper; 1291 u8 vl_hw_cap; 1292 1293 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1294 if (!rep) { 1295 err = -ENOMEM; 1296 goto out; 1297 } 1298 1299 /* props being zeroed by the caller, avoid zeroing it here */ 1300 1301 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1302 if (err) 1303 goto out; 1304 1305 props->lid = rep->lid; 1306 props->lmc = rep->lmc; 1307 props->sm_lid = rep->sm_lid; 1308 props->sm_sl = rep->sm_sl; 1309 props->state = rep->vport_state; 1310 props->phys_state = rep->port_physical_state; 1311 props->port_cap_flags = rep->cap_mask1; 1312 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1313 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1314 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1315 props->bad_pkey_cntr = rep->pkey_violation_counter; 1316 props->qkey_viol_cntr = rep->qkey_violation_counter; 1317 props->subnet_timeout = rep->subnet_timeout; 1318 props->init_type_reply = rep->init_type_reply; 1319 1320 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1321 props->port_cap_flags2 = rep->cap_mask2; 1322 1323 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1324 &props->active_speed, port); 1325 if (err) 1326 goto out; 1327 1328 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1329 1330 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1331 1332 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1333 1334 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1335 1336 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1337 1338 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1339 if (err) 1340 goto out; 1341 1342 err = translate_max_vl_num(ibdev, vl_hw_cap, 1343 &props->max_vl_num); 1344out: 1345 kfree(rep); 1346 return err; 1347} 1348 1349int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1350 struct ib_port_attr *props) 1351{ 1352 unsigned int count; 1353 int ret; 1354 1355 switch (mlx5_get_vport_access_method(ibdev)) { 1356 case MLX5_VPORT_ACCESS_METHOD_MAD: 1357 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1358 break; 1359 1360 case MLX5_VPORT_ACCESS_METHOD_HCA: 1361 ret = mlx5_query_hca_port(ibdev, port, props); 1362 break; 1363 1364 case MLX5_VPORT_ACCESS_METHOD_NIC: 1365 ret = mlx5_query_port_roce(ibdev, port, props); 1366 break; 1367 1368 default: 1369 ret = -EINVAL; 1370 } 1371 1372 if (!ret && props) { 1373 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1374 struct mlx5_core_dev *mdev; 1375 bool put_mdev = true; 1376 1377 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1378 if (!mdev) { 1379 /* If the port isn't affiliated yet query the master. 1380 * The master and slave will have the same values. 1381 */ 1382 mdev = dev->mdev; 1383 port = 1; 1384 put_mdev = false; 1385 } 1386 count = mlx5_core_reserved_gids_count(mdev); 1387 if (put_mdev) 1388 mlx5_ib_put_native_port_mdev(dev, port); 1389 props->gid_tbl_len -= count; 1390 } 1391 return ret; 1392} 1393 1394static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1395 struct ib_port_attr *props) 1396{ 1397 int ret; 1398 1399 /* Only link layer == ethernet is valid for representors 1400 * and we always use port 1 1401 */ 1402 ret = mlx5_query_port_roce(ibdev, port, props); 1403 if (ret || !props) 1404 return ret; 1405 1406 /* We don't support GIDS */ 1407 props->gid_tbl_len = 0; 1408 1409 return ret; 1410} 1411 1412static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1413 union ib_gid *gid) 1414{ 1415 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1416 struct mlx5_core_dev *mdev = dev->mdev; 1417 1418 switch (mlx5_get_vport_access_method(ibdev)) { 1419 case MLX5_VPORT_ACCESS_METHOD_MAD: 1420 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1421 1422 case MLX5_VPORT_ACCESS_METHOD_HCA: 1423 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1424 1425 default: 1426 return -EINVAL; 1427 } 1428 1429} 1430 1431static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1432 u16 index, u16 *pkey) 1433{ 1434 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1435 struct mlx5_core_dev *mdev; 1436 bool put_mdev = true; 1437 u8 mdev_port_num; 1438 int err; 1439 1440 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1441 if (!mdev) { 1442 /* The port isn't affiliated yet, get the PKey from the master 1443 * port. For RoCE the PKey tables will be the same. 1444 */ 1445 put_mdev = false; 1446 mdev = dev->mdev; 1447 mdev_port_num = 1; 1448 } 1449 1450 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1451 index, pkey); 1452 if (put_mdev) 1453 mlx5_ib_put_native_port_mdev(dev, port); 1454 1455 return err; 1456} 1457 1458static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1459 u16 *pkey) 1460{ 1461 switch (mlx5_get_vport_access_method(ibdev)) { 1462 case MLX5_VPORT_ACCESS_METHOD_MAD: 1463 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1464 1465 case MLX5_VPORT_ACCESS_METHOD_HCA: 1466 case MLX5_VPORT_ACCESS_METHOD_NIC: 1467 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1468 default: 1469 return -EINVAL; 1470 } 1471} 1472 1473static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1474 struct ib_device_modify *props) 1475{ 1476 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1477 struct mlx5_reg_node_desc in; 1478 struct mlx5_reg_node_desc out; 1479 int err; 1480 1481 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1482 return -EOPNOTSUPP; 1483 1484 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1485 return 0; 1486 1487 /* 1488 * If possible, pass node desc to FW, so it can generate 1489 * a 144 trap. If cmd fails, just ignore. 1490 */ 1491 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1492 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1493 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1494 if (err) 1495 return err; 1496 1497 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1498 1499 return err; 1500} 1501 1502static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1503 u32 value) 1504{ 1505 struct mlx5_hca_vport_context ctx = {}; 1506 struct mlx5_core_dev *mdev; 1507 u8 mdev_port_num; 1508 int err; 1509 1510 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1511 if (!mdev) 1512 return -ENODEV; 1513 1514 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1515 if (err) 1516 goto out; 1517 1518 if (~ctx.cap_mask1_perm & mask) { 1519 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1520 mask, ctx.cap_mask1_perm); 1521 err = -EINVAL; 1522 goto out; 1523 } 1524 1525 ctx.cap_mask1 = value; 1526 ctx.cap_mask1_perm = mask; 1527 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1528 0, &ctx); 1529 1530out: 1531 mlx5_ib_put_native_port_mdev(dev, port_num); 1532 1533 return err; 1534} 1535 1536static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1537 struct ib_port_modify *props) 1538{ 1539 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1540 struct ib_port_attr attr; 1541 u32 tmp; 1542 int err; 1543 u32 change_mask; 1544 u32 value; 1545 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1546 IB_LINK_LAYER_INFINIBAND); 1547 1548 /* CM layer calls ib_modify_port() regardless of the link layer. For 1549 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1550 */ 1551 if (!is_ib) 1552 return 0; 1553 1554 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1555 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1556 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1557 return set_port_caps_atomic(dev, port, change_mask, value); 1558 } 1559 1560 mutex_lock(&dev->cap_mask_mutex); 1561 1562 err = ib_query_port(ibdev, port, &attr); 1563 if (err) 1564 goto out; 1565 1566 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1567 ~props->clr_port_cap_mask; 1568 1569 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1570 1571out: 1572 mutex_unlock(&dev->cap_mask_mutex); 1573 return err; 1574} 1575 1576static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1577{ 1578 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1579 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1580} 1581 1582static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1583{ 1584 /* Large page with non 4k uar support might limit the dynamic size */ 1585 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1586 return MLX5_MIN_DYN_BFREGS; 1587 1588 return MLX5_MAX_DYN_BFREGS; 1589} 1590 1591static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1592 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1593 struct mlx5_bfreg_info *bfregi) 1594{ 1595 int uars_per_sys_page; 1596 int bfregs_per_sys_page; 1597 int ref_bfregs = req->total_num_bfregs; 1598 1599 if (req->total_num_bfregs == 0) 1600 return -EINVAL; 1601 1602 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1603 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1604 1605 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1606 return -ENOMEM; 1607 1608 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1609 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1610 /* This holds the required static allocation asked by the user */ 1611 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1612 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1613 return -EINVAL; 1614 1615 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1616 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1617 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1618 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1619 1620 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1621 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1622 lib_uar_4k ? "yes" : "no", ref_bfregs, 1623 req->total_num_bfregs, bfregi->total_num_bfregs, 1624 bfregi->num_sys_pages); 1625 1626 return 0; 1627} 1628 1629static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1630{ 1631 struct mlx5_bfreg_info *bfregi; 1632 int err; 1633 int i; 1634 1635 bfregi = &context->bfregi; 1636 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1637 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1638 if (err) 1639 goto error; 1640 1641 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1642 } 1643 1644 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1645 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1646 1647 return 0; 1648 1649error: 1650 for (--i; i >= 0; i--) 1651 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1652 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1653 1654 return err; 1655} 1656 1657static void deallocate_uars(struct mlx5_ib_dev *dev, 1658 struct mlx5_ib_ucontext *context) 1659{ 1660 struct mlx5_bfreg_info *bfregi; 1661 int i; 1662 1663 bfregi = &context->bfregi; 1664 for (i = 0; i < bfregi->num_sys_pages; i++) 1665 if (i < bfregi->num_static_sys_pages || 1666 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1667 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1668} 1669 1670int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1671{ 1672 int err = 0; 1673 1674 mutex_lock(&dev->lb.mutex); 1675 if (td) 1676 dev->lb.user_td++; 1677 if (qp) 1678 dev->lb.qps++; 1679 1680 if (dev->lb.user_td == 2 || 1681 dev->lb.qps == 1) { 1682 if (!dev->lb.enabled) { 1683 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1684 dev->lb.enabled = true; 1685 } 1686 } 1687 1688 mutex_unlock(&dev->lb.mutex); 1689 1690 return err; 1691} 1692 1693void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1694{ 1695 mutex_lock(&dev->lb.mutex); 1696 if (td) 1697 dev->lb.user_td--; 1698 if (qp) 1699 dev->lb.qps--; 1700 1701 if (dev->lb.user_td == 1 && 1702 dev->lb.qps == 0) { 1703 if (dev->lb.enabled) { 1704 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1705 dev->lb.enabled = false; 1706 } 1707 } 1708 1709 mutex_unlock(&dev->lb.mutex); 1710} 1711 1712static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1713 u16 uid) 1714{ 1715 int err; 1716 1717 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1718 return 0; 1719 1720 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1721 if (err) 1722 return err; 1723 1724 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1725 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1726 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1727 return err; 1728 1729 return mlx5_ib_enable_lb(dev, true, false); 1730} 1731 1732static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1733 u16 uid) 1734{ 1735 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1736 return; 1737 1738 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1739 1740 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1741 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1742 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1743 return; 1744 1745 mlx5_ib_disable_lb(dev, true, false); 1746} 1747 1748static int set_ucontext_resp(struct ib_ucontext *uctx, 1749 struct mlx5_ib_alloc_ucontext_resp *resp) 1750{ 1751 struct ib_device *ibdev = uctx->device; 1752 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1753 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1754 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1755 int err; 1756 1757 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1758 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1759 &resp->dump_fill_mkey); 1760 if (err) 1761 return err; 1762 resp->comp_mask |= 1763 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1764 } 1765 1766 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1767 if (dev->wc_support) 1768 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1769 log_bf_reg_size); 1770 resp->cache_line_size = cache_line_size(); 1771 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1772 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1773 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1774 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1775 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1776 resp->cqe_version = context->cqe_version; 1777 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1778 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1779 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1780 MLX5_CAP_GEN(dev->mdev, 1781 num_of_uars_per_page) : 1; 1782 1783 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1784 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1785 if (mlx5_get_flow_namespace(dev->mdev, 1786 MLX5_FLOW_NAMESPACE_EGRESS)) 1787 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1788 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1789 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1790 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1791 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1792 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1793 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1794 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1795 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1796 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1797 } 1798 1799 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1800 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1801 resp->num_ports = dev->num_ports; 1802 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1803 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1804 1805 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1806 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1807 resp->eth_min_inline++; 1808 } 1809 1810 if (dev->mdev->clock_info) 1811 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1812 1813 /* 1814 * We don't want to expose information from the PCI bar that is located 1815 * after 4096 bytes, so if the arch only supports larger pages, let's 1816 * pretend we don't support reading the HCA's core clock. This is also 1817 * forced by mmap function. 1818 */ 1819 if (PAGE_SIZE <= 4096) { 1820 resp->comp_mask |= 1821 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1822 resp->hca_core_clock_offset = 1823 offsetof(struct mlx5_init_seg, 1824 internal_timer_h) % PAGE_SIZE; 1825 } 1826 1827 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1828 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1829 1830 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1831 return 0; 1832} 1833 1834static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1835 struct ib_udata *udata) 1836{ 1837 struct ib_device *ibdev = uctx->device; 1838 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1839 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1840 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1841 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1842 struct mlx5_bfreg_info *bfregi; 1843 int ver; 1844 int err; 1845 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1846 max_cqe_version); 1847 bool lib_uar_4k; 1848 bool lib_uar_dyn; 1849 1850 if (!dev->ib_active) 1851 return -EAGAIN; 1852 1853 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1854 ver = 0; 1855 else if (udata->inlen >= min_req_v2) 1856 ver = 2; 1857 else 1858 return -EINVAL; 1859 1860 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1861 if (err) 1862 return err; 1863 1864 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1865 return -EOPNOTSUPP; 1866 1867 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1868 return -EOPNOTSUPP; 1869 1870 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1871 MLX5_NON_FP_BFREGS_PER_UAR); 1872 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1873 return -EINVAL; 1874 1875 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1876 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1877 bfregi = &context->bfregi; 1878 1879 if (lib_uar_dyn) { 1880 bfregi->lib_uar_dyn = lib_uar_dyn; 1881 goto uar_done; 1882 } 1883 1884 /* updates req->total_num_bfregs */ 1885 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1886 if (err) 1887 goto out_ctx; 1888 1889 mutex_init(&bfregi->lock); 1890 bfregi->lib_uar_4k = lib_uar_4k; 1891 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1892 GFP_KERNEL); 1893 if (!bfregi->count) { 1894 err = -ENOMEM; 1895 goto out_ctx; 1896 } 1897 1898 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1899 sizeof(*bfregi->sys_pages), 1900 GFP_KERNEL); 1901 if (!bfregi->sys_pages) { 1902 err = -ENOMEM; 1903 goto out_count; 1904 } 1905 1906 err = allocate_uars(dev, context); 1907 if (err) 1908 goto out_sys_pages; 1909 1910uar_done: 1911 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1912 err = mlx5_ib_devx_create(dev, true); 1913 if (err < 0) 1914 goto out_uars; 1915 context->devx_uid = err; 1916 } 1917 1918 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1919 context->devx_uid); 1920 if (err) 1921 goto out_devx; 1922 1923 INIT_LIST_HEAD(&context->db_page_list); 1924 mutex_init(&context->db_page_mutex); 1925 1926 context->cqe_version = min_t(__u8, 1927 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1928 req.max_cqe_version); 1929 1930 err = set_ucontext_resp(uctx, &resp); 1931 if (err) 1932 goto out_mdev; 1933 1934 resp.response_length = min(udata->outlen, sizeof(resp)); 1935 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1936 if (err) 1937 goto out_mdev; 1938 1939 bfregi->ver = ver; 1940 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1941 context->lib_caps = req.lib_caps; 1942 print_lib_caps(dev, context->lib_caps); 1943 1944 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1945 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1946 1947 atomic_set(&context->tx_port_affinity, 1948 atomic_add_return( 1949 1, &dev->port[port].roce.tx_port_affinity)); 1950 } 1951 1952 return 0; 1953 1954out_mdev: 1955 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1956out_devx: 1957 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1958 mlx5_ib_devx_destroy(dev, context->devx_uid); 1959 1960out_uars: 1961 deallocate_uars(dev, context); 1962 1963out_sys_pages: 1964 kfree(bfregi->sys_pages); 1965 1966out_count: 1967 kfree(bfregi->count); 1968 1969out_ctx: 1970 return err; 1971} 1972 1973static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1974 struct uverbs_attr_bundle *attrs) 1975{ 1976 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1977 int ret; 1978 1979 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1980 if (ret) 1981 return ret; 1982 1983 uctx_resp.response_length = 1984 min_t(size_t, 1985 uverbs_attr_get_len(attrs, 1986 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1987 sizeof(uctx_resp)); 1988 1989 ret = uverbs_copy_to_struct_or_zero(attrs, 1990 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1991 &uctx_resp, 1992 sizeof(uctx_resp)); 1993 return ret; 1994} 1995 1996static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1997{ 1998 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1999 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2000 struct mlx5_bfreg_info *bfregi; 2001 2002 bfregi = &context->bfregi; 2003 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2004 2005 if (context->devx_uid) 2006 mlx5_ib_devx_destroy(dev, context->devx_uid); 2007 2008 deallocate_uars(dev, context); 2009 kfree(bfregi->sys_pages); 2010 kfree(bfregi->count); 2011} 2012 2013static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2014 int uar_idx) 2015{ 2016 int fw_uars_per_page; 2017 2018 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2019 2020 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2021} 2022 2023static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2024 int uar_idx) 2025{ 2026 unsigned int fw_uars_per_page; 2027 2028 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2029 MLX5_UARS_IN_PAGE : 1; 2030 2031 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2032} 2033 2034static int get_command(unsigned long offset) 2035{ 2036 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2037} 2038 2039static int get_arg(unsigned long offset) 2040{ 2041 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2042} 2043 2044static int get_index(unsigned long offset) 2045{ 2046 return get_arg(offset); 2047} 2048 2049/* Index resides in an extra byte to enable larger values than 255 */ 2050static int get_extended_index(unsigned long offset) 2051{ 2052 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2053} 2054 2055 2056static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2057{ 2058} 2059 2060static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2061{ 2062 switch (cmd) { 2063 case MLX5_IB_MMAP_WC_PAGE: 2064 return "WC"; 2065 case MLX5_IB_MMAP_REGULAR_PAGE: 2066 return "best effort WC"; 2067 case MLX5_IB_MMAP_NC_PAGE: 2068 return "NC"; 2069 case MLX5_IB_MMAP_DEVICE_MEM: 2070 return "Device Memory"; 2071 default: 2072 return "Unknown"; 2073 } 2074} 2075 2076static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2077 struct vm_area_struct *vma, 2078 struct mlx5_ib_ucontext *context) 2079{ 2080 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2081 !(vma->vm_flags & VM_SHARED)) 2082 return -EINVAL; 2083 2084 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2085 return -EOPNOTSUPP; 2086 2087 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2088 return -EPERM; 2089 vma->vm_flags &= ~VM_MAYWRITE; 2090 2091 if (!dev->mdev->clock_info) 2092 return -EOPNOTSUPP; 2093 2094 return vm_insert_page(vma, vma->vm_start, 2095 virt_to_page(dev->mdev->clock_info)); 2096} 2097 2098static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2099{ 2100 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2101 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2102 struct mlx5_var_table *var_table = &dev->var_table; 2103 struct mlx5_ib_dm *mdm; 2104 2105 switch (mentry->mmap_flag) { 2106 case MLX5_IB_MMAP_TYPE_MEMIC: 2107 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2108 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2109 mdm->size); 2110 kfree(mdm); 2111 break; 2112 case MLX5_IB_MMAP_TYPE_VAR: 2113 mutex_lock(&var_table->bitmap_lock); 2114 clear_bit(mentry->page_idx, var_table->bitmap); 2115 mutex_unlock(&var_table->bitmap_lock); 2116 kfree(mentry); 2117 break; 2118 case MLX5_IB_MMAP_TYPE_UAR_WC: 2119 case MLX5_IB_MMAP_TYPE_UAR_NC: 2120 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2121 kfree(mentry); 2122 break; 2123 default: 2124 WARN_ON(true); 2125 } 2126} 2127 2128static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2129 struct vm_area_struct *vma, 2130 struct mlx5_ib_ucontext *context) 2131{ 2132 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2133 int err; 2134 unsigned long idx; 2135 phys_addr_t pfn; 2136 pgprot_t prot; 2137 u32 bfreg_dyn_idx = 0; 2138 u32 uar_index; 2139 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2140 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2141 bfregi->num_static_sys_pages; 2142 2143 if (bfregi->lib_uar_dyn) 2144 return -EINVAL; 2145 2146 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2147 return -EINVAL; 2148 2149 if (dyn_uar) 2150 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2151 else 2152 idx = get_index(vma->vm_pgoff); 2153 2154 if (idx >= max_valid_idx) { 2155 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2156 idx, max_valid_idx); 2157 return -EINVAL; 2158 } 2159 2160 switch (cmd) { 2161 case MLX5_IB_MMAP_WC_PAGE: 2162 case MLX5_IB_MMAP_ALLOC_WC: 2163 case MLX5_IB_MMAP_REGULAR_PAGE: 2164 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2165 prot = pgprot_writecombine(vma->vm_page_prot); 2166 break; 2167 case MLX5_IB_MMAP_NC_PAGE: 2168 prot = pgprot_noncached(vma->vm_page_prot); 2169 break; 2170 default: 2171 return -EINVAL; 2172 } 2173 2174 if (dyn_uar) { 2175 int uars_per_page; 2176 2177 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2178 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2179 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2180 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2181 bfreg_dyn_idx, bfregi->total_num_bfregs); 2182 return -EINVAL; 2183 } 2184 2185 mutex_lock(&bfregi->lock); 2186 /* Fail if uar already allocated, first bfreg index of each 2187 * page holds its count. 2188 */ 2189 if (bfregi->count[bfreg_dyn_idx]) { 2190 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2191 mutex_unlock(&bfregi->lock); 2192 return -EINVAL; 2193 } 2194 2195 bfregi->count[bfreg_dyn_idx]++; 2196 mutex_unlock(&bfregi->lock); 2197 2198 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2199 if (err) { 2200 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2201 goto free_bfreg; 2202 } 2203 } else { 2204 uar_index = bfregi->sys_pages[idx]; 2205 } 2206 2207 pfn = uar_index2pfn(dev, uar_index); 2208 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2209 2210 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2211 prot, NULL); 2212 if (err) { 2213 mlx5_ib_err(dev, 2214 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2215 err, mmap_cmd2str(cmd)); 2216 goto err; 2217 } 2218 2219 if (dyn_uar) 2220 bfregi->sys_pages[idx] = uar_index; 2221 return 0; 2222 2223err: 2224 if (!dyn_uar) 2225 return err; 2226 2227 mlx5_cmd_free_uar(dev->mdev, idx); 2228 2229free_bfreg: 2230 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2231 2232 return err; 2233} 2234 2235static int add_dm_mmap_entry(struct ib_ucontext *context, 2236 struct mlx5_ib_dm *mdm, 2237 u64 address) 2238{ 2239 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2240 mdm->mentry.address = address; 2241 return rdma_user_mmap_entry_insert_range( 2242 context, &mdm->mentry.rdma_entry, 2243 mdm->size, 2244 MLX5_IB_MMAP_DEVICE_MEM << 16, 2245 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2246} 2247 2248static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2249{ 2250 unsigned long idx; 2251 u8 command; 2252 2253 command = get_command(vma->vm_pgoff); 2254 idx = get_extended_index(vma->vm_pgoff); 2255 2256 return (command << 16 | idx); 2257} 2258 2259static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2260 struct vm_area_struct *vma, 2261 struct ib_ucontext *ucontext) 2262{ 2263 struct mlx5_user_mmap_entry *mentry; 2264 struct rdma_user_mmap_entry *entry; 2265 unsigned long pgoff; 2266 pgprot_t prot; 2267 phys_addr_t pfn; 2268 int ret; 2269 2270 pgoff = mlx5_vma_to_pgoff(vma); 2271 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2272 if (!entry) 2273 return -EINVAL; 2274 2275 mentry = to_mmmap(entry); 2276 pfn = (mentry->address >> PAGE_SHIFT); 2277 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2278 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2279 prot = pgprot_noncached(vma->vm_page_prot); 2280 else 2281 prot = pgprot_writecombine(vma->vm_page_prot); 2282 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2283 entry->npages * PAGE_SIZE, 2284 prot, 2285 entry); 2286 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2287 return ret; 2288} 2289 2290static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2291{ 2292 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2293 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2294 2295 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2296 (index & 0xFF)) << PAGE_SHIFT; 2297} 2298 2299static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2300{ 2301 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2302 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2303 unsigned long command; 2304 phys_addr_t pfn; 2305 2306 command = get_command(vma->vm_pgoff); 2307 switch (command) { 2308 case MLX5_IB_MMAP_WC_PAGE: 2309 case MLX5_IB_MMAP_ALLOC_WC: 2310 if (!dev->wc_support) 2311 return -EPERM; 2312 fallthrough; 2313 case MLX5_IB_MMAP_NC_PAGE: 2314 case MLX5_IB_MMAP_REGULAR_PAGE: 2315 return uar_mmap(dev, command, vma, context); 2316 2317 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2318 return -ENOSYS; 2319 2320 case MLX5_IB_MMAP_CORE_CLOCK: 2321 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2322 return -EINVAL; 2323 2324 if (vma->vm_flags & VM_WRITE) 2325 return -EPERM; 2326 vma->vm_flags &= ~VM_MAYWRITE; 2327 2328 /* Don't expose to user-space information it shouldn't have */ 2329 if (PAGE_SIZE > 4096) 2330 return -EOPNOTSUPP; 2331 2332 pfn = (dev->mdev->iseg_base + 2333 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2334 PAGE_SHIFT; 2335 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2336 PAGE_SIZE, 2337 pgprot_noncached(vma->vm_page_prot), 2338 NULL); 2339 case MLX5_IB_MMAP_CLOCK_INFO: 2340 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2341 2342 default: 2343 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2344 } 2345 2346 return 0; 2347} 2348 2349static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2350 u32 type) 2351{ 2352 switch (type) { 2353 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2354 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2355 return -EOPNOTSUPP; 2356 break; 2357 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2358 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2359 if (!capable(CAP_SYS_RAWIO) || 2360 !capable(CAP_NET_RAW)) 2361 return -EPERM; 2362 2363 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2364 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) || 2365 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) || 2366 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2))) 2367 return -EOPNOTSUPP; 2368 break; 2369 } 2370 2371 return 0; 2372} 2373 2374static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2375 struct mlx5_ib_dm *dm, 2376 struct ib_dm_alloc_attr *attr, 2377 struct uverbs_attr_bundle *attrs) 2378{ 2379 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2380 u64 start_offset; 2381 u16 page_idx; 2382 int err; 2383 u64 address; 2384 2385 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2386 2387 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2388 dm->size, attr->alignment); 2389 if (err) 2390 return err; 2391 2392 address = dm->dev_addr & PAGE_MASK; 2393 err = add_dm_mmap_entry(ctx, dm, address); 2394 if (err) 2395 goto err_dealloc; 2396 2397 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2398 err = uverbs_copy_to(attrs, 2399 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2400 &page_idx, 2401 sizeof(page_idx)); 2402 if (err) 2403 goto err_copy; 2404 2405 start_offset = dm->dev_addr & ~PAGE_MASK; 2406 err = uverbs_copy_to(attrs, 2407 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2408 &start_offset, sizeof(start_offset)); 2409 if (err) 2410 goto err_copy; 2411 2412 return 0; 2413 2414err_copy: 2415 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2416err_dealloc: 2417 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2418 2419 return err; 2420} 2421 2422static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2423 struct mlx5_ib_dm *dm, 2424 struct ib_dm_alloc_attr *attr, 2425 struct uverbs_attr_bundle *attrs, 2426 int type) 2427{ 2428 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2429 u64 act_size; 2430 int err; 2431 2432 /* Allocation size must a multiple of the basic block size 2433 * and a power of 2. 2434 */ 2435 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2436 act_size = roundup_pow_of_two(act_size); 2437 2438 dm->size = act_size; 2439 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2440 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2441 &dm->icm_dm.obj_id); 2442 if (err) 2443 return err; 2444 2445 err = uverbs_copy_to(attrs, 2446 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2447 &dm->dev_addr, sizeof(dm->dev_addr)); 2448 if (err) 2449 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2450 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2451 dm->icm_dm.obj_id); 2452 2453 return err; 2454} 2455 2456struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2457 struct ib_ucontext *context, 2458 struct ib_dm_alloc_attr *attr, 2459 struct uverbs_attr_bundle *attrs) 2460{ 2461 struct mlx5_ib_dm *dm; 2462 enum mlx5_ib_uapi_dm_type type; 2463 int err; 2464 2465 err = uverbs_get_const_default(&type, attrs, 2466 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2467 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2468 if (err) 2469 return ERR_PTR(err); 2470 2471 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2472 type, attr->length, attr->alignment); 2473 2474 err = check_dm_type_support(to_mdev(ibdev), type); 2475 if (err) 2476 return ERR_PTR(err); 2477 2478 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2479 if (!dm) 2480 return ERR_PTR(-ENOMEM); 2481 2482 dm->type = type; 2483 2484 switch (type) { 2485 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2486 err = handle_alloc_dm_memic(context, dm, 2487 attr, 2488 attrs); 2489 break; 2490 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2491 err = handle_alloc_dm_sw_icm(context, dm, 2492 attr, attrs, 2493 MLX5_SW_ICM_TYPE_STEERING); 2494 break; 2495 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2496 err = handle_alloc_dm_sw_icm(context, dm, 2497 attr, attrs, 2498 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2499 break; 2500 default: 2501 err = -EOPNOTSUPP; 2502 } 2503 2504 if (err) 2505 goto err_free; 2506 2507 return &dm->ibdm; 2508 2509err_free: 2510 kfree(dm); 2511 return ERR_PTR(err); 2512} 2513 2514int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2515{ 2516 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2517 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2518 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2519 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2520 int ret; 2521 2522 switch (dm->type) { 2523 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2524 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2525 return 0; 2526 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2527 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2528 dm->size, ctx->devx_uid, dm->dev_addr, 2529 dm->icm_dm.obj_id); 2530 if (ret) 2531 return ret; 2532 break; 2533 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2534 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2535 dm->size, ctx->devx_uid, dm->dev_addr, 2536 dm->icm_dm.obj_id); 2537 if (ret) 2538 return ret; 2539 break; 2540 default: 2541 return -EOPNOTSUPP; 2542 } 2543 2544 kfree(dm); 2545 2546 return 0; 2547} 2548 2549static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2550{ 2551 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2552 struct ib_device *ibdev = ibpd->device; 2553 struct mlx5_ib_alloc_pd_resp resp; 2554 int err; 2555 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2556 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2557 u16 uid = 0; 2558 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2559 udata, struct mlx5_ib_ucontext, ibucontext); 2560 2561 uid = context ? context->devx_uid : 0; 2562 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2563 MLX5_SET(alloc_pd_in, in, uid, uid); 2564 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2565 if (err) 2566 return err; 2567 2568 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2569 pd->uid = uid; 2570 if (udata) { 2571 resp.pdn = pd->pdn; 2572 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2573 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2574 return -EFAULT; 2575 } 2576 } 2577 2578 return 0; 2579} 2580 2581static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2582{ 2583 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2584 struct mlx5_ib_pd *mpd = to_mpd(pd); 2585 2586 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2587} 2588 2589static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2590{ 2591 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2592 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2593 int err; 2594 u16 uid; 2595 2596 uid = ibqp->pd ? 2597 to_mpd(ibqp->pd)->uid : 0; 2598 2599 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2600 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2601 return -EOPNOTSUPP; 2602 } 2603 2604 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2605 if (err) 2606 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2607 ibqp->qp_num, gid->raw); 2608 2609 return err; 2610} 2611 2612static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2613{ 2614 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2615 int err; 2616 u16 uid; 2617 2618 uid = ibqp->pd ? 2619 to_mpd(ibqp->pd)->uid : 0; 2620 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2621 if (err) 2622 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2623 ibqp->qp_num, gid->raw); 2624 2625 return err; 2626} 2627 2628static int init_node_data(struct mlx5_ib_dev *dev) 2629{ 2630 int err; 2631 2632 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2633 if (err) 2634 return err; 2635 2636 dev->mdev->rev_id = dev->mdev->pdev->revision; 2637 2638 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2639} 2640 2641static ssize_t fw_pages_show(struct device *device, 2642 struct device_attribute *attr, char *buf) 2643{ 2644 struct mlx5_ib_dev *dev = 2645 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2646 2647 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2648} 2649static DEVICE_ATTR_RO(fw_pages); 2650 2651static ssize_t reg_pages_show(struct device *device, 2652 struct device_attribute *attr, char *buf) 2653{ 2654 struct mlx5_ib_dev *dev = 2655 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2656 2657 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2658} 2659static DEVICE_ATTR_RO(reg_pages); 2660 2661static ssize_t hca_type_show(struct device *device, 2662 struct device_attribute *attr, char *buf) 2663{ 2664 struct mlx5_ib_dev *dev = 2665 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2666 2667 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2668} 2669static DEVICE_ATTR_RO(hca_type); 2670 2671static ssize_t hw_rev_show(struct device *device, 2672 struct device_attribute *attr, char *buf) 2673{ 2674 struct mlx5_ib_dev *dev = 2675 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2676 2677 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2678} 2679static DEVICE_ATTR_RO(hw_rev); 2680 2681static ssize_t board_id_show(struct device *device, 2682 struct device_attribute *attr, char *buf) 2683{ 2684 struct mlx5_ib_dev *dev = 2685 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2686 2687 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2688 dev->mdev->board_id); 2689} 2690static DEVICE_ATTR_RO(board_id); 2691 2692static struct attribute *mlx5_class_attributes[] = { 2693 &dev_attr_hw_rev.attr, 2694 &dev_attr_hca_type.attr, 2695 &dev_attr_board_id.attr, 2696 &dev_attr_fw_pages.attr, 2697 &dev_attr_reg_pages.attr, 2698 NULL, 2699}; 2700 2701static const struct attribute_group mlx5_attr_group = { 2702 .attrs = mlx5_class_attributes, 2703}; 2704 2705static void pkey_change_handler(struct work_struct *work) 2706{ 2707 struct mlx5_ib_port_resources *ports = 2708 container_of(work, struct mlx5_ib_port_resources, 2709 pkey_change_work); 2710 2711 mlx5_ib_gsi_pkey_change(ports->gsi); 2712} 2713 2714static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2715{ 2716 struct mlx5_ib_qp *mqp; 2717 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2718 struct mlx5_core_cq *mcq; 2719 struct list_head cq_armed_list; 2720 unsigned long flags_qp; 2721 unsigned long flags_cq; 2722 unsigned long flags; 2723 2724 INIT_LIST_HEAD(&cq_armed_list); 2725 2726 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2727 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2728 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2729 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2730 if (mqp->sq.tail != mqp->sq.head) { 2731 send_mcq = to_mcq(mqp->ibqp.send_cq); 2732 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2733 if (send_mcq->mcq.comp && 2734 mqp->ibqp.send_cq->comp_handler) { 2735 if (!send_mcq->mcq.reset_notify_added) { 2736 send_mcq->mcq.reset_notify_added = 1; 2737 list_add_tail(&send_mcq->mcq.reset_notify, 2738 &cq_armed_list); 2739 } 2740 } 2741 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2742 } 2743 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2744 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2745 /* no handling is needed for SRQ */ 2746 if (!mqp->ibqp.srq) { 2747 if (mqp->rq.tail != mqp->rq.head) { 2748 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2749 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2750 if (recv_mcq->mcq.comp && 2751 mqp->ibqp.recv_cq->comp_handler) { 2752 if (!recv_mcq->mcq.reset_notify_added) { 2753 recv_mcq->mcq.reset_notify_added = 1; 2754 list_add_tail(&recv_mcq->mcq.reset_notify, 2755 &cq_armed_list); 2756 } 2757 } 2758 spin_unlock_irqrestore(&recv_mcq->lock, 2759 flags_cq); 2760 } 2761 } 2762 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2763 } 2764 /*At that point all inflight post send were put to be executed as of we 2765 * lock/unlock above locks Now need to arm all involved CQs. 2766 */ 2767 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2768 mcq->comp(mcq, NULL); 2769 } 2770 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2771} 2772 2773static void delay_drop_handler(struct work_struct *work) 2774{ 2775 int err; 2776 struct mlx5_ib_delay_drop *delay_drop = 2777 container_of(work, struct mlx5_ib_delay_drop, 2778 delay_drop_work); 2779 2780 atomic_inc(&delay_drop->events_cnt); 2781 2782 mutex_lock(&delay_drop->lock); 2783 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2784 if (err) { 2785 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2786 delay_drop->timeout); 2787 delay_drop->activate = false; 2788 } 2789 mutex_unlock(&delay_drop->lock); 2790} 2791 2792static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2793 struct ib_event *ibev) 2794{ 2795 u8 port = (eqe->data.port.port >> 4) & 0xf; 2796 2797 switch (eqe->sub_type) { 2798 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2799 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2800 IB_LINK_LAYER_ETHERNET) 2801 schedule_work(&ibdev->delay_drop.delay_drop_work); 2802 break; 2803 default: /* do nothing */ 2804 return; 2805 } 2806} 2807 2808static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2809 struct ib_event *ibev) 2810{ 2811 u8 port = (eqe->data.port.port >> 4) & 0xf; 2812 2813 ibev->element.port_num = port; 2814 2815 switch (eqe->sub_type) { 2816 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2817 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2818 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2819 /* In RoCE, port up/down events are handled in 2820 * mlx5_netdev_event(). 2821 */ 2822 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2823 IB_LINK_LAYER_ETHERNET) 2824 return -EINVAL; 2825 2826 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2827 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2828 break; 2829 2830 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2831 ibev->event = IB_EVENT_LID_CHANGE; 2832 break; 2833 2834 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2835 ibev->event = IB_EVENT_PKEY_CHANGE; 2836 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2837 break; 2838 2839 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2840 ibev->event = IB_EVENT_GID_CHANGE; 2841 break; 2842 2843 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2844 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2845 break; 2846 default: 2847 return -EINVAL; 2848 } 2849 2850 return 0; 2851} 2852 2853static void mlx5_ib_handle_event(struct work_struct *_work) 2854{ 2855 struct mlx5_ib_event_work *work = 2856 container_of(_work, struct mlx5_ib_event_work, work); 2857 struct mlx5_ib_dev *ibdev; 2858 struct ib_event ibev; 2859 bool fatal = false; 2860 2861 if (work->is_slave) { 2862 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2863 if (!ibdev) 2864 goto out; 2865 } else { 2866 ibdev = work->dev; 2867 } 2868 2869 switch (work->event) { 2870 case MLX5_DEV_EVENT_SYS_ERROR: 2871 ibev.event = IB_EVENT_DEVICE_FATAL; 2872 mlx5_ib_handle_internal_error(ibdev); 2873 ibev.element.port_num = (u8)(unsigned long)work->param; 2874 fatal = true; 2875 break; 2876 case MLX5_EVENT_TYPE_PORT_CHANGE: 2877 if (handle_port_change(ibdev, work->param, &ibev)) 2878 goto out; 2879 break; 2880 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2881 handle_general_event(ibdev, work->param, &ibev); 2882 fallthrough; 2883 default: 2884 goto out; 2885 } 2886 2887 ibev.device = &ibdev->ib_dev; 2888 2889 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2890 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2891 goto out; 2892 } 2893 2894 if (ibdev->ib_active) 2895 ib_dispatch_event(&ibev); 2896 2897 if (fatal) 2898 ibdev->ib_active = false; 2899out: 2900 kfree(work); 2901} 2902 2903static int mlx5_ib_event(struct notifier_block *nb, 2904 unsigned long event, void *param) 2905{ 2906 struct mlx5_ib_event_work *work; 2907 2908 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2909 if (!work) 2910 return NOTIFY_DONE; 2911 2912 INIT_WORK(&work->work, mlx5_ib_handle_event); 2913 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2914 work->is_slave = false; 2915 work->param = param; 2916 work->event = event; 2917 2918 queue_work(mlx5_ib_event_wq, &work->work); 2919 2920 return NOTIFY_OK; 2921} 2922 2923static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2924 unsigned long event, void *param) 2925{ 2926 struct mlx5_ib_event_work *work; 2927 2928 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2929 if (!work) 2930 return NOTIFY_DONE; 2931 2932 INIT_WORK(&work->work, mlx5_ib_handle_event); 2933 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2934 work->is_slave = true; 2935 work->param = param; 2936 work->event = event; 2937 queue_work(mlx5_ib_event_wq, &work->work); 2938 2939 return NOTIFY_OK; 2940} 2941 2942static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2943{ 2944 struct mlx5_hca_vport_context vport_ctx; 2945 int err; 2946 int port; 2947 2948 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) { 2949 dev->mdev->port_caps[port - 1].has_smi = false; 2950 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2951 MLX5_CAP_PORT_TYPE_IB) { 2952 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2953 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2954 port, 0, 2955 &vport_ctx); 2956 if (err) { 2957 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2958 port, err); 2959 return err; 2960 } 2961 dev->mdev->port_caps[port - 1].has_smi = 2962 vport_ctx.has_smi; 2963 } else { 2964 dev->mdev->port_caps[port - 1].has_smi = true; 2965 } 2966 } 2967 } 2968 return 0; 2969} 2970 2971static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2972{ 2973 int port; 2974 2975 for (port = 1; port <= dev->num_ports; port++) 2976 mlx5_query_ext_port_caps(dev, port); 2977} 2978 2979static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port) 2980{ 2981 struct ib_device_attr *dprops = NULL; 2982 struct ib_port_attr *pprops = NULL; 2983 int err = -ENOMEM; 2984 2985 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL); 2986 if (!pprops) 2987 goto out; 2988 2989 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2990 if (!dprops) 2991 goto out; 2992 2993 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL); 2994 if (err) { 2995 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2996 goto out; 2997 } 2998 2999 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3000 if (err) { 3001 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3002 port, err); 3003 goto out; 3004 } 3005 3006 dev->mdev->port_caps[port - 1].pkey_table_len = 3007 dprops->max_pkeys; 3008 dev->mdev->port_caps[port - 1].gid_table_len = 3009 pprops->gid_tbl_len; 3010 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3011 port, dprops->max_pkeys, pprops->gid_tbl_len); 3012 3013out: 3014 kfree(pprops); 3015 kfree(dprops); 3016 3017 return err; 3018} 3019 3020static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3021{ 3022 /* For representors use port 1, is this is the only native 3023 * port 3024 */ 3025 if (dev->is_rep) 3026 return __get_port_caps(dev, 1); 3027 return __get_port_caps(dev, port); 3028} 3029 3030static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3031{ 3032 switch (umr_fence_cap) { 3033 case MLX5_CAP_UMR_FENCE_NONE: 3034 return MLX5_FENCE_MODE_NONE; 3035 case MLX5_CAP_UMR_FENCE_SMALL: 3036 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3037 default: 3038 return MLX5_FENCE_MODE_STRONG_ORDERING; 3039 } 3040} 3041 3042static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3043{ 3044 struct mlx5_ib_resources *devr = &dev->devr; 3045 struct ib_srq_init_attr attr; 3046 struct ib_device *ibdev; 3047 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3048 int port; 3049 int ret = 0; 3050 3051 ibdev = &dev->ib_dev; 3052 3053 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3054 return -EOPNOTSUPP; 3055 3056 mutex_init(&devr->mutex); 3057 3058 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 3059 if (!devr->p0) 3060 return -ENOMEM; 3061 3062 devr->p0->device = ibdev; 3063 devr->p0->uobject = NULL; 3064 atomic_set(&devr->p0->usecnt, 0); 3065 3066 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 3067 if (ret) 3068 goto error0; 3069 3070 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 3071 if (!devr->c0) { 3072 ret = -ENOMEM; 3073 goto error1; 3074 } 3075 3076 devr->c0->device = &dev->ib_dev; 3077 atomic_set(&devr->c0->usecnt, 0); 3078 3079 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 3080 if (ret) 3081 goto err_create_cq; 3082 3083 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3084 if (ret) 3085 goto error2; 3086 3087 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3088 if (ret) 3089 goto error3; 3090 3091 memset(&attr, 0, sizeof(attr)); 3092 attr.attr.max_sge = 1; 3093 attr.attr.max_wr = 1; 3094 attr.srq_type = IB_SRQT_XRC; 3095 attr.ext.cq = devr->c0; 3096 3097 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3098 if (!devr->s0) { 3099 ret = -ENOMEM; 3100 goto error4; 3101 } 3102 3103 devr->s0->device = &dev->ib_dev; 3104 devr->s0->pd = devr->p0; 3105 devr->s0->srq_type = IB_SRQT_XRC; 3106 devr->s0->ext.cq = devr->c0; 3107 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 3108 if (ret) 3109 goto err_create; 3110 3111 atomic_inc(&devr->s0->ext.cq->usecnt); 3112 atomic_inc(&devr->p0->usecnt); 3113 atomic_set(&devr->s0->usecnt, 0); 3114 3115 memset(&attr, 0, sizeof(attr)); 3116 attr.attr.max_sge = 1; 3117 attr.attr.max_wr = 1; 3118 attr.srq_type = IB_SRQT_BASIC; 3119 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3120 if (!devr->s1) { 3121 ret = -ENOMEM; 3122 goto error5; 3123 } 3124 3125 devr->s1->device = &dev->ib_dev; 3126 devr->s1->pd = devr->p0; 3127 devr->s1->srq_type = IB_SRQT_BASIC; 3128 devr->s1->ext.cq = devr->c0; 3129 3130 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 3131 if (ret) 3132 goto error6; 3133 3134 atomic_inc(&devr->p0->usecnt); 3135 atomic_set(&devr->s1->usecnt, 0); 3136 3137 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3138 INIT_WORK(&devr->ports[port].pkey_change_work, 3139 pkey_change_handler); 3140 3141 return 0; 3142 3143error6: 3144 kfree(devr->s1); 3145error5: 3146 mlx5_ib_destroy_srq(devr->s0, NULL); 3147err_create: 3148 kfree(devr->s0); 3149error4: 3150 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3151error3: 3152 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3153error2: 3154 mlx5_ib_destroy_cq(devr->c0, NULL); 3155err_create_cq: 3156 kfree(devr->c0); 3157error1: 3158 mlx5_ib_dealloc_pd(devr->p0, NULL); 3159error0: 3160 kfree(devr->p0); 3161 return ret; 3162} 3163 3164static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3165{ 3166 struct mlx5_ib_resources *devr = &dev->devr; 3167 int port; 3168 3169 mlx5_ib_destroy_srq(devr->s1, NULL); 3170 kfree(devr->s1); 3171 mlx5_ib_destroy_srq(devr->s0, NULL); 3172 kfree(devr->s0); 3173 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3174 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3175 mlx5_ib_destroy_cq(devr->c0, NULL); 3176 kfree(devr->c0); 3177 mlx5_ib_dealloc_pd(devr->p0, NULL); 3178 kfree(devr->p0); 3179 3180 /* Make sure no change P_Key work items are still executing */ 3181 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3182 cancel_work_sync(&devr->ports[port].pkey_change_work); 3183} 3184 3185static u32 get_core_cap_flags(struct ib_device *ibdev, 3186 struct mlx5_hca_vport_context *rep) 3187{ 3188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3189 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3190 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3191 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3192 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3193 u32 ret = 0; 3194 3195 if (rep->grh_required) 3196 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3197 3198 if (ll == IB_LINK_LAYER_INFINIBAND) 3199 return ret | RDMA_CORE_PORT_IBA_IB; 3200 3201 if (raw_support) 3202 ret |= RDMA_CORE_PORT_RAW_PACKET; 3203 3204 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3205 return ret; 3206 3207 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3208 return ret; 3209 3210 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3211 ret |= RDMA_CORE_PORT_IBA_ROCE; 3212 3213 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3214 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3215 3216 return ret; 3217} 3218 3219static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3220 struct ib_port_immutable *immutable) 3221{ 3222 struct ib_port_attr attr; 3223 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3224 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3225 struct mlx5_hca_vport_context rep = {0}; 3226 int err; 3227 3228 err = ib_query_port(ibdev, port_num, &attr); 3229 if (err) 3230 return err; 3231 3232 if (ll == IB_LINK_LAYER_INFINIBAND) { 3233 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3234 &rep); 3235 if (err) 3236 return err; 3237 } 3238 3239 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3240 immutable->gid_tbl_len = attr.gid_tbl_len; 3241 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3242 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3243 3244 return 0; 3245} 3246 3247static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3248 struct ib_port_immutable *immutable) 3249{ 3250 struct ib_port_attr attr; 3251 int err; 3252 3253 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3254 3255 err = ib_query_port(ibdev, port_num, &attr); 3256 if (err) 3257 return err; 3258 3259 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3260 immutable->gid_tbl_len = attr.gid_tbl_len; 3261 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3262 3263 return 0; 3264} 3265 3266static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3267{ 3268 struct mlx5_ib_dev *dev = 3269 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3270 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3271 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3272 fw_rev_sub(dev->mdev)); 3273} 3274 3275static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3276{ 3277 struct mlx5_core_dev *mdev = dev->mdev; 3278 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3279 MLX5_FLOW_NAMESPACE_LAG); 3280 struct mlx5_flow_table *ft; 3281 int err; 3282 3283 if (!ns || !mlx5_lag_is_roce(mdev)) 3284 return 0; 3285 3286 err = mlx5_cmd_create_vport_lag(mdev); 3287 if (err) 3288 return err; 3289 3290 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3291 if (IS_ERR(ft)) { 3292 err = PTR_ERR(ft); 3293 goto err_destroy_vport_lag; 3294 } 3295 3296 dev->flow_db->lag_demux_ft = ft; 3297 dev->lag_active = true; 3298 return 0; 3299 3300err_destroy_vport_lag: 3301 mlx5_cmd_destroy_vport_lag(mdev); 3302 return err; 3303} 3304 3305static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3306{ 3307 struct mlx5_core_dev *mdev = dev->mdev; 3308 3309 if (dev->lag_active) { 3310 dev->lag_active = false; 3311 3312 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3313 dev->flow_db->lag_demux_ft = NULL; 3314 3315 mlx5_cmd_destroy_vport_lag(mdev); 3316 } 3317} 3318 3319static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3320{ 3321 int err; 3322 3323 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3324 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3325 if (err) { 3326 dev->port[port_num].roce.nb.notifier_call = NULL; 3327 return err; 3328 } 3329 3330 return 0; 3331} 3332 3333static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3334{ 3335 if (dev->port[port_num].roce.nb.notifier_call) { 3336 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3337 dev->port[port_num].roce.nb.notifier_call = NULL; 3338 } 3339} 3340 3341static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3342{ 3343 int err; 3344 3345 err = mlx5_nic_vport_enable_roce(dev->mdev); 3346 if (err) 3347 return err; 3348 3349 err = mlx5_eth_lag_init(dev); 3350 if (err) 3351 goto err_disable_roce; 3352 3353 return 0; 3354 3355err_disable_roce: 3356 mlx5_nic_vport_disable_roce(dev->mdev); 3357 3358 return err; 3359} 3360 3361static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3362{ 3363 mlx5_eth_lag_cleanup(dev); 3364 mlx5_nic_vport_disable_roce(dev->mdev); 3365} 3366 3367static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3368 enum rdma_netdev_t type, 3369 struct rdma_netdev_alloc_params *params) 3370{ 3371 if (type != RDMA_NETDEV_IPOIB) 3372 return -EOPNOTSUPP; 3373 3374 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3375} 3376 3377static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3378 size_t count, loff_t *pos) 3379{ 3380 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3381 char lbuf[20]; 3382 int len; 3383 3384 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3385 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3386} 3387 3388static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3389 size_t count, loff_t *pos) 3390{ 3391 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3392 u32 timeout; 3393 u32 var; 3394 3395 if (kstrtouint_from_user(buf, count, 0, &var)) 3396 return -EFAULT; 3397 3398 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3399 1000); 3400 if (timeout != var) 3401 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3402 timeout); 3403 3404 delay_drop->timeout = timeout; 3405 3406 return count; 3407} 3408 3409static const struct file_operations fops_delay_drop_timeout = { 3410 .owner = THIS_MODULE, 3411 .open = simple_open, 3412 .write = delay_drop_timeout_write, 3413 .read = delay_drop_timeout_read, 3414}; 3415 3416static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3417 struct mlx5_ib_multiport_info *mpi) 3418{ 3419 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3420 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3421 int comps; 3422 int err; 3423 int i; 3424 3425 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3426 3427 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3428 3429 spin_lock(&port->mp.mpi_lock); 3430 if (!mpi->ibdev) { 3431 spin_unlock(&port->mp.mpi_lock); 3432 return; 3433 } 3434 3435 mpi->ibdev = NULL; 3436 3437 spin_unlock(&port->mp.mpi_lock); 3438 if (mpi->mdev_events.notifier_call) 3439 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3440 mpi->mdev_events.notifier_call = NULL; 3441 mlx5_remove_netdev_notifier(ibdev, port_num); 3442 spin_lock(&port->mp.mpi_lock); 3443 3444 comps = mpi->mdev_refcnt; 3445 if (comps) { 3446 mpi->unaffiliate = true; 3447 init_completion(&mpi->unref_comp); 3448 spin_unlock(&port->mp.mpi_lock); 3449 3450 for (i = 0; i < comps; i++) 3451 wait_for_completion(&mpi->unref_comp); 3452 3453 spin_lock(&port->mp.mpi_lock); 3454 mpi->unaffiliate = false; 3455 } 3456 3457 port->mp.mpi = NULL; 3458 3459 spin_unlock(&port->mp.mpi_lock); 3460 3461 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3462 3463 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3464 /* Log an error, still needed to cleanup the pointers and add 3465 * it back to the list. 3466 */ 3467 if (err) 3468 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3469 port_num + 1); 3470 3471 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3472} 3473 3474static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3475 struct mlx5_ib_multiport_info *mpi) 3476{ 3477 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3478 int err; 3479 3480 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3481 3482 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3483 if (ibdev->port[port_num].mp.mpi) { 3484 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3485 port_num + 1); 3486 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3487 return false; 3488 } 3489 3490 ibdev->port[port_num].mp.mpi = mpi; 3491 mpi->ibdev = ibdev; 3492 mpi->mdev_events.notifier_call = NULL; 3493 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3494 3495 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3496 if (err) 3497 goto unbind; 3498 3499 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 3500 if (err) 3501 goto unbind; 3502 3503 err = mlx5_add_netdev_notifier(ibdev, port_num); 3504 if (err) { 3505 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3506 port_num + 1); 3507 goto unbind; 3508 } 3509 3510 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3511 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3512 3513 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3514 3515 return true; 3516 3517unbind: 3518 mlx5_ib_unbind_slave_port(ibdev, mpi); 3519 return false; 3520} 3521 3522static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3523{ 3524 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3525 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3526 port_num + 1); 3527 struct mlx5_ib_multiport_info *mpi; 3528 int err; 3529 int i; 3530 3531 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3532 return 0; 3533 3534 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3535 &dev->sys_image_guid); 3536 if (err) 3537 return err; 3538 3539 err = mlx5_nic_vport_enable_roce(dev->mdev); 3540 if (err) 3541 return err; 3542 3543 mutex_lock(&mlx5_ib_multiport_mutex); 3544 for (i = 0; i < dev->num_ports; i++) { 3545 bool bound = false; 3546 3547 /* build a stub multiport info struct for the native port. */ 3548 if (i == port_num) { 3549 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3550 if (!mpi) { 3551 mutex_unlock(&mlx5_ib_multiport_mutex); 3552 mlx5_nic_vport_disable_roce(dev->mdev); 3553 return -ENOMEM; 3554 } 3555 3556 mpi->is_master = true; 3557 mpi->mdev = dev->mdev; 3558 mpi->sys_image_guid = dev->sys_image_guid; 3559 dev->port[i].mp.mpi = mpi; 3560 mpi->ibdev = dev; 3561 mpi = NULL; 3562 continue; 3563 } 3564 3565 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3566 list) { 3567 if (dev->sys_image_guid == mpi->sys_image_guid && 3568 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3569 bound = mlx5_ib_bind_slave_port(dev, mpi); 3570 } 3571 3572 if (bound) { 3573 dev_dbg(mpi->mdev->device, 3574 "removing port from unaffiliated list.\n"); 3575 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3576 list_del(&mpi->list); 3577 break; 3578 } 3579 } 3580 if (!bound) { 3581 get_port_caps(dev, i + 1); 3582 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3583 i + 1); 3584 } 3585 } 3586 3587 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3588 mutex_unlock(&mlx5_ib_multiport_mutex); 3589 return err; 3590} 3591 3592static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3593{ 3594 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3595 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3596 port_num + 1); 3597 int i; 3598 3599 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3600 return; 3601 3602 mutex_lock(&mlx5_ib_multiport_mutex); 3603 for (i = 0; i < dev->num_ports; i++) { 3604 if (dev->port[i].mp.mpi) { 3605 /* Destroy the native port stub */ 3606 if (i == port_num) { 3607 kfree(dev->port[i].mp.mpi); 3608 dev->port[i].mp.mpi = NULL; 3609 } else { 3610 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3611 list_add_tail(&dev->port[i].mp.mpi->list, 3612 &mlx5_ib_unaffiliated_port_list); 3613 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3614 } 3615 } 3616 } 3617 3618 mlx5_ib_dbg(dev, "removing from devlist\n"); 3619 list_del(&dev->ib_dev_list); 3620 mutex_unlock(&mlx5_ib_multiport_mutex); 3621 3622 mlx5_nic_vport_disable_roce(dev->mdev); 3623} 3624 3625static int mmap_obj_cleanup(struct ib_uobject *uobject, 3626 enum rdma_remove_reason why, 3627 struct uverbs_attr_bundle *attrs) 3628{ 3629 struct mlx5_user_mmap_entry *obj = uobject->object; 3630 3631 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3632 return 0; 3633} 3634 3635static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3636 struct mlx5_user_mmap_entry *entry, 3637 size_t length) 3638{ 3639 return rdma_user_mmap_entry_insert_range( 3640 &c->ibucontext, &entry->rdma_entry, length, 3641 (MLX5_IB_MMAP_OFFSET_START << 16), 3642 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3643} 3644 3645static struct mlx5_user_mmap_entry * 3646alloc_var_entry(struct mlx5_ib_ucontext *c) 3647{ 3648 struct mlx5_user_mmap_entry *entry; 3649 struct mlx5_var_table *var_table; 3650 u32 page_idx; 3651 int err; 3652 3653 var_table = &to_mdev(c->ibucontext.device)->var_table; 3654 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3655 if (!entry) 3656 return ERR_PTR(-ENOMEM); 3657 3658 mutex_lock(&var_table->bitmap_lock); 3659 page_idx = find_first_zero_bit(var_table->bitmap, 3660 var_table->num_var_hw_entries); 3661 if (page_idx >= var_table->num_var_hw_entries) { 3662 err = -ENOSPC; 3663 mutex_unlock(&var_table->bitmap_lock); 3664 goto end; 3665 } 3666 3667 set_bit(page_idx, var_table->bitmap); 3668 mutex_unlock(&var_table->bitmap_lock); 3669 3670 entry->address = var_table->hw_start_addr + 3671 (page_idx * var_table->stride_size); 3672 entry->page_idx = page_idx; 3673 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3674 3675 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3676 var_table->stride_size); 3677 if (err) 3678 goto err_insert; 3679 3680 return entry; 3681 3682err_insert: 3683 mutex_lock(&var_table->bitmap_lock); 3684 clear_bit(page_idx, var_table->bitmap); 3685 mutex_unlock(&var_table->bitmap_lock); 3686end: 3687 kfree(entry); 3688 return ERR_PTR(err); 3689} 3690 3691static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3692 struct uverbs_attr_bundle *attrs) 3693{ 3694 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3695 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3696 struct mlx5_ib_ucontext *c; 3697 struct mlx5_user_mmap_entry *entry; 3698 u64 mmap_offset; 3699 u32 length; 3700 int err; 3701 3702 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3703 if (IS_ERR(c)) 3704 return PTR_ERR(c); 3705 3706 entry = alloc_var_entry(c); 3707 if (IS_ERR(entry)) 3708 return PTR_ERR(entry); 3709 3710 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3711 length = entry->rdma_entry.npages * PAGE_SIZE; 3712 uobj->object = entry; 3713 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3714 3715 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3716 &mmap_offset, sizeof(mmap_offset)); 3717 if (err) 3718 return err; 3719 3720 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3721 &entry->page_idx, sizeof(entry->page_idx)); 3722 if (err) 3723 return err; 3724 3725 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3726 &length, sizeof(length)); 3727 return err; 3728} 3729 3730DECLARE_UVERBS_NAMED_METHOD( 3731 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3732 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3733 MLX5_IB_OBJECT_VAR, 3734 UVERBS_ACCESS_NEW, 3735 UA_MANDATORY), 3736 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3737 UVERBS_ATTR_TYPE(u32), 3738 UA_MANDATORY), 3739 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3740 UVERBS_ATTR_TYPE(u32), 3741 UA_MANDATORY), 3742 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3743 UVERBS_ATTR_TYPE(u64), 3744 UA_MANDATORY)); 3745 3746DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3747 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3748 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3749 MLX5_IB_OBJECT_VAR, 3750 UVERBS_ACCESS_DESTROY, 3751 UA_MANDATORY)); 3752 3753DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3754 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3755 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3756 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3757 3758static bool var_is_supported(struct ib_device *device) 3759{ 3760 struct mlx5_ib_dev *dev = to_mdev(device); 3761 3762 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3763 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3764} 3765 3766static struct mlx5_user_mmap_entry * 3767alloc_uar_entry(struct mlx5_ib_ucontext *c, 3768 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3769{ 3770 struct mlx5_user_mmap_entry *entry; 3771 struct mlx5_ib_dev *dev; 3772 u32 uar_index; 3773 int err; 3774 3775 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3776 if (!entry) 3777 return ERR_PTR(-ENOMEM); 3778 3779 dev = to_mdev(c->ibucontext.device); 3780 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3781 if (err) 3782 goto end; 3783 3784 entry->page_idx = uar_index; 3785 entry->address = uar_index2paddress(dev, uar_index); 3786 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3787 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3788 else 3789 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3790 3791 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3792 if (err) 3793 goto err_insert; 3794 3795 return entry; 3796 3797err_insert: 3798 mlx5_cmd_free_uar(dev->mdev, uar_index); 3799end: 3800 kfree(entry); 3801 return ERR_PTR(err); 3802} 3803 3804static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3805 struct uverbs_attr_bundle *attrs) 3806{ 3807 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3808 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3809 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3810 struct mlx5_ib_ucontext *c; 3811 struct mlx5_user_mmap_entry *entry; 3812 u64 mmap_offset; 3813 u32 length; 3814 int err; 3815 3816 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3817 if (IS_ERR(c)) 3818 return PTR_ERR(c); 3819 3820 err = uverbs_get_const(&alloc_type, attrs, 3821 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3822 if (err) 3823 return err; 3824 3825 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3826 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3827 return -EOPNOTSUPP; 3828 3829 if (!to_mdev(c->ibucontext.device)->wc_support && 3830 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3831 return -EOPNOTSUPP; 3832 3833 entry = alloc_uar_entry(c, alloc_type); 3834 if (IS_ERR(entry)) 3835 return PTR_ERR(entry); 3836 3837 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3838 length = entry->rdma_entry.npages * PAGE_SIZE; 3839 uobj->object = entry; 3840 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3841 3842 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3843 &mmap_offset, sizeof(mmap_offset)); 3844 if (err) 3845 return err; 3846 3847 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3848 &entry->page_idx, sizeof(entry->page_idx)); 3849 if (err) 3850 return err; 3851 3852 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3853 &length, sizeof(length)); 3854 return err; 3855} 3856 3857DECLARE_UVERBS_NAMED_METHOD( 3858 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3859 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3860 MLX5_IB_OBJECT_UAR, 3861 UVERBS_ACCESS_NEW, 3862 UA_MANDATORY), 3863 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3864 enum mlx5_ib_uapi_uar_alloc_type, 3865 UA_MANDATORY), 3866 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3867 UVERBS_ATTR_TYPE(u32), 3868 UA_MANDATORY), 3869 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3870 UVERBS_ATTR_TYPE(u32), 3871 UA_MANDATORY), 3872 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3873 UVERBS_ATTR_TYPE(u64), 3874 UA_MANDATORY)); 3875 3876DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3877 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3878 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3879 MLX5_IB_OBJECT_UAR, 3880 UVERBS_ACCESS_DESTROY, 3881 UA_MANDATORY)); 3882 3883DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3884 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3885 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3886 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3887 3888ADD_UVERBS_ATTRIBUTES_SIMPLE( 3889 mlx5_ib_dm, 3890 UVERBS_OBJECT_DM, 3891 UVERBS_METHOD_DM_ALLOC, 3892 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 3893 UVERBS_ATTR_TYPE(u64), 3894 UA_MANDATORY), 3895 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 3896 UVERBS_ATTR_TYPE(u16), 3897 UA_OPTIONAL), 3898 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 3899 enum mlx5_ib_uapi_dm_type, 3900 UA_OPTIONAL)); 3901 3902ADD_UVERBS_ATTRIBUTES_SIMPLE( 3903 mlx5_ib_flow_action, 3904 UVERBS_OBJECT_FLOW_ACTION, 3905 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3906 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3907 enum mlx5_ib_uapi_flow_action_flags)); 3908 3909ADD_UVERBS_ATTRIBUTES_SIMPLE( 3910 mlx5_ib_query_context, 3911 UVERBS_OBJECT_DEVICE, 3912 UVERBS_METHOD_QUERY_CONTEXT, 3913 UVERBS_ATTR_PTR_OUT( 3914 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3915 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3916 dump_fill_mkey), 3917 UA_MANDATORY)); 3918 3919static const struct uapi_definition mlx5_ib_defs[] = { 3920 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3921 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3922 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3923 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3924 3925 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3926 &mlx5_ib_flow_action), 3927 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 3928 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3929 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3930 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3931 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3932 {} 3933}; 3934 3935static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3936{ 3937 mlx5_ib_cleanup_multiport_master(dev); 3938 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3939 cleanup_srcu_struct(&dev->odp_srcu); 3940 mutex_destroy(&dev->cap_mask_mutex); 3941 WARN_ON(!xa_empty(&dev->sig_mrs)); 3942 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3943} 3944 3945static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3946{ 3947 struct mlx5_core_dev *mdev = dev->mdev; 3948 int err; 3949 int i; 3950 3951 for (i = 0; i < dev->num_ports; i++) { 3952 spin_lock_init(&dev->port[i].mp.mpi_lock); 3953 rwlock_init(&dev->port[i].roce.netdev_lock); 3954 dev->port[i].roce.dev = dev; 3955 dev->port[i].roce.native_port_num = i + 1; 3956 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3957 } 3958 3959 mlx5_ib_internal_fill_odp_caps(dev); 3960 3961 err = mlx5_ib_init_multiport_master(dev); 3962 if (err) 3963 return err; 3964 3965 err = set_has_smi_cap(dev); 3966 if (err) 3967 goto err_mp; 3968 3969 if (!mlx5_core_mp_enabled(mdev)) { 3970 for (i = 1; i <= dev->num_ports; i++) { 3971 err = get_port_caps(dev, i); 3972 if (err) 3973 break; 3974 } 3975 } else { 3976 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 3977 } 3978 if (err) 3979 goto err_mp; 3980 3981 if (mlx5_use_mad_ifc(dev)) 3982 get_ext_port_caps(dev); 3983 3984 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3985 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3986 dev->ib_dev.phys_port_cnt = dev->num_ports; 3987 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3988 dev->ib_dev.dev.parent = mdev->device; 3989 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3990 3991 err = init_srcu_struct(&dev->odp_srcu); 3992 if (err) 3993 goto err_mp; 3994 3995 mutex_init(&dev->cap_mask_mutex); 3996 INIT_LIST_HEAD(&dev->qp_list); 3997 spin_lock_init(&dev->reset_flow_resource_lock); 3998 xa_init(&dev->odp_mkeys); 3999 xa_init(&dev->sig_mrs); 4000 atomic_set(&dev->mkey_var, 0); 4001 4002 spin_lock_init(&dev->dm.lock); 4003 dev->dm.dev = mdev; 4004 return 0; 4005 4006err_mp: 4007 mlx5_ib_cleanup_multiport_master(dev); 4008 return err; 4009} 4010 4011static int mlx5_ib_enable_driver(struct ib_device *dev) 4012{ 4013 struct mlx5_ib_dev *mdev = to_mdev(dev); 4014 int ret; 4015 4016 ret = mlx5_ib_test_wc(mdev); 4017 mlx5_ib_dbg(mdev, "Write-Combining %s", 4018 mdev->wc_support ? "supported" : "not supported"); 4019 4020 return ret; 4021} 4022 4023static const struct ib_device_ops mlx5_ib_dev_ops = { 4024 .owner = THIS_MODULE, 4025 .driver_id = RDMA_DRIVER_MLX5, 4026 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4027 4028 .add_gid = mlx5_ib_add_gid, 4029 .alloc_mr = mlx5_ib_alloc_mr, 4030 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4031 .alloc_pd = mlx5_ib_alloc_pd, 4032 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4033 .attach_mcast = mlx5_ib_mcg_attach, 4034 .check_mr_status = mlx5_ib_check_mr_status, 4035 .create_ah = mlx5_ib_create_ah, 4036 .create_cq = mlx5_ib_create_cq, 4037 .create_qp = mlx5_ib_create_qp, 4038 .create_srq = mlx5_ib_create_srq, 4039 .dealloc_pd = mlx5_ib_dealloc_pd, 4040 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4041 .del_gid = mlx5_ib_del_gid, 4042 .dereg_mr = mlx5_ib_dereg_mr, 4043 .destroy_ah = mlx5_ib_destroy_ah, 4044 .destroy_cq = mlx5_ib_destroy_cq, 4045 .destroy_qp = mlx5_ib_destroy_qp, 4046 .destroy_srq = mlx5_ib_destroy_srq, 4047 .detach_mcast = mlx5_ib_mcg_detach, 4048 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4049 .drain_rq = mlx5_ib_drain_rq, 4050 .drain_sq = mlx5_ib_drain_sq, 4051 .enable_driver = mlx5_ib_enable_driver, 4052 .get_dev_fw_str = get_dev_fw_str, 4053 .get_dma_mr = mlx5_ib_get_dma_mr, 4054 .get_link_layer = mlx5_ib_port_link_layer, 4055 .map_mr_sg = mlx5_ib_map_mr_sg, 4056 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4057 .mmap = mlx5_ib_mmap, 4058 .mmap_free = mlx5_ib_mmap_free, 4059 .modify_cq = mlx5_ib_modify_cq, 4060 .modify_device = mlx5_ib_modify_device, 4061 .modify_port = mlx5_ib_modify_port, 4062 .modify_qp = mlx5_ib_modify_qp, 4063 .modify_srq = mlx5_ib_modify_srq, 4064 .poll_cq = mlx5_ib_poll_cq, 4065 .post_recv = mlx5_ib_post_recv_nodrain, 4066 .post_send = mlx5_ib_post_send_nodrain, 4067 .post_srq_recv = mlx5_ib_post_srq_recv, 4068 .process_mad = mlx5_ib_process_mad, 4069 .query_ah = mlx5_ib_query_ah, 4070 .query_device = mlx5_ib_query_device, 4071 .query_gid = mlx5_ib_query_gid, 4072 .query_pkey = mlx5_ib_query_pkey, 4073 .query_qp = mlx5_ib_query_qp, 4074 .query_srq = mlx5_ib_query_srq, 4075 .query_ucontext = mlx5_ib_query_ucontext, 4076 .reg_user_mr = mlx5_ib_reg_user_mr, 4077 .req_notify_cq = mlx5_ib_arm_cq, 4078 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4079 .resize_cq = mlx5_ib_resize_cq, 4080 4081 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4082 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4083 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4084 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4085 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4086 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4087}; 4088 4089static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4090 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4091}; 4092 4093static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4094 .get_vf_config = mlx5_ib_get_vf_config, 4095 .get_vf_guid = mlx5_ib_get_vf_guid, 4096 .get_vf_stats = mlx5_ib_get_vf_stats, 4097 .set_vf_guid = mlx5_ib_set_vf_guid, 4098 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4099}; 4100 4101static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4102 .alloc_mw = mlx5_ib_alloc_mw, 4103 .dealloc_mw = mlx5_ib_dealloc_mw, 4104 4105 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4106}; 4107 4108static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4109 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4110 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4111 4112 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4113}; 4114 4115static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 4116 .alloc_dm = mlx5_ib_alloc_dm, 4117 .dealloc_dm = mlx5_ib_dealloc_dm, 4118 .reg_dm_mr = mlx5_ib_reg_dm_mr, 4119}; 4120 4121static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4122{ 4123 struct mlx5_core_dev *mdev = dev->mdev; 4124 struct mlx5_var_table *var_table = &dev->var_table; 4125 u8 log_doorbell_bar_size; 4126 u8 log_doorbell_stride; 4127 u64 bar_size; 4128 4129 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4130 log_doorbell_bar_size); 4131 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4132 log_doorbell_stride); 4133 var_table->hw_start_addr = dev->mdev->bar_addr + 4134 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4135 doorbell_bar_offset); 4136 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4137 var_table->stride_size = 1ULL << log_doorbell_stride; 4138 var_table->num_var_hw_entries = div_u64(bar_size, 4139 var_table->stride_size); 4140 mutex_init(&var_table->bitmap_lock); 4141 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4142 GFP_KERNEL); 4143 return (var_table->bitmap) ? 0 : -ENOMEM; 4144} 4145 4146static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4147{ 4148 bitmap_free(dev->var_table.bitmap); 4149} 4150 4151static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4152{ 4153 struct mlx5_core_dev *mdev = dev->mdev; 4154 int err; 4155 4156 dev->ib_dev.uverbs_cmd_mask = 4157 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 4158 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 4159 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 4160 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 4161 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 4162 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 4163 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 4164 (1ull << IB_USER_VERBS_CMD_REG_MR) | 4165 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 4166 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 4167 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 4168 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 4169 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4170 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4171 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4172 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4173 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4174 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4175 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4176 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4177 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4178 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4179 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4180 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4181 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4182 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4183 dev->ib_dev.uverbs_ex_cmd_mask |= 4184 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4185 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4186 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 4187 4188 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4189 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4190 ib_set_device_ops(&dev->ib_dev, 4191 &mlx5_ib_dev_ipoib_enhanced_ops); 4192 4193 if (mlx5_core_is_pf(mdev)) 4194 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4195 4196 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4197 4198 if (MLX5_CAP_GEN(mdev, imaicl)) { 4199 dev->ib_dev.uverbs_cmd_mask |= 4200 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4201 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4202 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4203 } 4204 4205 if (MLX5_CAP_GEN(mdev, xrc)) { 4206 dev->ib_dev.uverbs_cmd_mask |= 4207 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4208 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4209 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4210 } 4211 4212 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4213 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4214 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4215 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4216 4217 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4218 4219 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4220 dev->ib_dev.driver_def = mlx5_ib_defs; 4221 4222 err = init_node_data(dev); 4223 if (err) 4224 return err; 4225 4226 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4227 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4228 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4229 mutex_init(&dev->lb.mutex); 4230 4231 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4232 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4233 err = mlx5_ib_init_var_table(dev); 4234 if (err) 4235 return err; 4236 } 4237 4238 dev->ib_dev.use_cq_dim = true; 4239 4240 return 0; 4241} 4242 4243static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4244 .get_port_immutable = mlx5_port_immutable, 4245 .query_port = mlx5_ib_query_port, 4246}; 4247 4248static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4249{ 4250 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4251 return 0; 4252} 4253 4254static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4255 .get_port_immutable = mlx5_port_rep_immutable, 4256 .query_port = mlx5_ib_rep_query_port, 4257}; 4258 4259static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4260{ 4261 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4262 return 0; 4263} 4264 4265static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4266 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4267 .create_wq = mlx5_ib_create_wq, 4268 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4269 .destroy_wq = mlx5_ib_destroy_wq, 4270 .get_netdev = mlx5_ib_get_netdev, 4271 .modify_wq = mlx5_ib_modify_wq, 4272 4273 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4274 ib_rwq_ind_tbl), 4275}; 4276 4277static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4278{ 4279 struct mlx5_core_dev *mdev = dev->mdev; 4280 enum rdma_link_layer ll; 4281 int port_type_cap; 4282 u8 port_num = 0; 4283 int err; 4284 4285 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4286 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4287 4288 if (ll == IB_LINK_LAYER_ETHERNET) { 4289 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4290 4291 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4292 4293 /* Register only for native ports */ 4294 err = mlx5_add_netdev_notifier(dev, port_num); 4295 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4296 /* 4297 * We don't enable ETH interface for 4298 * 1. IB representors 4299 * 2. User disabled ROCE through devlink interface 4300 */ 4301 return err; 4302 4303 err = mlx5_enable_eth(dev); 4304 if (err) 4305 goto cleanup; 4306 } 4307 4308 return 0; 4309cleanup: 4310 mlx5_remove_netdev_notifier(dev, port_num); 4311 return err; 4312} 4313 4314static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4315{ 4316 struct mlx5_core_dev *mdev = dev->mdev; 4317 enum rdma_link_layer ll; 4318 int port_type_cap; 4319 u8 port_num; 4320 4321 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4322 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4323 4324 if (ll == IB_LINK_LAYER_ETHERNET) { 4325 if (!dev->is_rep) 4326 mlx5_disable_eth(dev); 4327 4328 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4329 mlx5_remove_netdev_notifier(dev, port_num); 4330 } 4331} 4332 4333static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4334{ 4335 mlx5_ib_init_cong_debugfs(dev, 4336 mlx5_core_native_port_num(dev->mdev) - 1); 4337 return 0; 4338} 4339 4340static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4341{ 4342 mlx5_ib_cleanup_cong_debugfs(dev, 4343 mlx5_core_native_port_num(dev->mdev) - 1); 4344} 4345 4346static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4347{ 4348 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4349 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4350} 4351 4352static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4353{ 4354 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4355} 4356 4357static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4358{ 4359 int err; 4360 4361 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4362 if (err) 4363 return err; 4364 4365 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4366 if (err) 4367 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4368 4369 return err; 4370} 4371 4372static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4373{ 4374 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4375 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4376} 4377 4378static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4379{ 4380 const char *name; 4381 4382 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4383 if (!mlx5_lag_is_roce(dev->mdev)) 4384 name = "mlx5_%d"; 4385 else 4386 name = "mlx5_bond_%d"; 4387 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4388} 4389 4390static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4391{ 4392 int err; 4393 4394 err = mlx5_mr_cache_cleanup(dev); 4395 if (err) 4396 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4397 4398 if (dev->umrc.qp) 4399 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4400 if (dev->umrc.cq) 4401 ib_free_cq(dev->umrc.cq); 4402 if (dev->umrc.pd) 4403 ib_dealloc_pd(dev->umrc.pd); 4404} 4405 4406static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4407{ 4408 ib_unregister_device(&dev->ib_dev); 4409} 4410 4411enum { 4412 MAX_UMR_WR = 128, 4413}; 4414 4415static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4416{ 4417 struct ib_qp_init_attr *init_attr = NULL; 4418 struct ib_qp_attr *attr = NULL; 4419 struct ib_pd *pd; 4420 struct ib_cq *cq; 4421 struct ib_qp *qp; 4422 int ret; 4423 4424 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4425 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4426 if (!attr || !init_attr) { 4427 ret = -ENOMEM; 4428 goto error_0; 4429 } 4430 4431 pd = ib_alloc_pd(&dev->ib_dev, 0); 4432 if (IS_ERR(pd)) { 4433 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4434 ret = PTR_ERR(pd); 4435 goto error_0; 4436 } 4437 4438 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4439 if (IS_ERR(cq)) { 4440 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4441 ret = PTR_ERR(cq); 4442 goto error_2; 4443 } 4444 4445 init_attr->send_cq = cq; 4446 init_attr->recv_cq = cq; 4447 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4448 init_attr->cap.max_send_wr = MAX_UMR_WR; 4449 init_attr->cap.max_send_sge = 1; 4450 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4451 init_attr->port_num = 1; 4452 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4453 if (IS_ERR(qp)) { 4454 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4455 ret = PTR_ERR(qp); 4456 goto error_3; 4457 } 4458 qp->device = &dev->ib_dev; 4459 qp->real_qp = qp; 4460 qp->uobject = NULL; 4461 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4462 qp->send_cq = init_attr->send_cq; 4463 qp->recv_cq = init_attr->recv_cq; 4464 4465 attr->qp_state = IB_QPS_INIT; 4466 attr->port_num = 1; 4467 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4468 IB_QP_PORT, NULL); 4469 if (ret) { 4470 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4471 goto error_4; 4472 } 4473 4474 memset(attr, 0, sizeof(*attr)); 4475 attr->qp_state = IB_QPS_RTR; 4476 attr->path_mtu = IB_MTU_256; 4477 4478 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4479 if (ret) { 4480 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4481 goto error_4; 4482 } 4483 4484 memset(attr, 0, sizeof(*attr)); 4485 attr->qp_state = IB_QPS_RTS; 4486 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4487 if (ret) { 4488 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4489 goto error_4; 4490 } 4491 4492 dev->umrc.qp = qp; 4493 dev->umrc.cq = cq; 4494 dev->umrc.pd = pd; 4495 4496 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4497 ret = mlx5_mr_cache_init(dev); 4498 if (ret) { 4499 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4500 goto error_4; 4501 } 4502 4503 kfree(attr); 4504 kfree(init_attr); 4505 4506 return 0; 4507 4508error_4: 4509 mlx5_ib_destroy_qp(qp, NULL); 4510 dev->umrc.qp = NULL; 4511 4512error_3: 4513 ib_free_cq(cq); 4514 dev->umrc.cq = NULL; 4515 4516error_2: 4517 ib_dealloc_pd(pd); 4518 dev->umrc.pd = NULL; 4519 4520error_0: 4521 kfree(attr); 4522 kfree(init_attr); 4523 return ret; 4524} 4525 4526static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4527{ 4528 struct dentry *root; 4529 4530 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4531 return 0; 4532 4533 mutex_init(&dev->delay_drop.lock); 4534 dev->delay_drop.dev = dev; 4535 dev->delay_drop.activate = false; 4536 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4537 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4538 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4539 atomic_set(&dev->delay_drop.events_cnt, 0); 4540 4541 if (!mlx5_debugfs_root) 4542 return 0; 4543 4544 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4545 dev->delay_drop.dir_debugfs = root; 4546 4547 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4548 &dev->delay_drop.events_cnt); 4549 debugfs_create_atomic_t("num_rqs", 0400, root, 4550 &dev->delay_drop.rqs_cnt); 4551 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4552 &fops_delay_drop_timeout); 4553 return 0; 4554} 4555 4556static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4557{ 4558 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4559 return; 4560 4561 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4562 if (!dev->delay_drop.dir_debugfs) 4563 return; 4564 4565 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4566 dev->delay_drop.dir_debugfs = NULL; 4567} 4568 4569static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4570{ 4571 dev->mdev_events.notifier_call = mlx5_ib_event; 4572 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4573 return 0; 4574} 4575 4576static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4577{ 4578 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4579} 4580 4581void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4582 const struct mlx5_ib_profile *profile, 4583 int stage) 4584{ 4585 dev->ib_active = false; 4586 4587 /* Number of stages to cleanup */ 4588 while (stage) { 4589 stage--; 4590 if (profile->stage[stage].cleanup) 4591 profile->stage[stage].cleanup(dev); 4592 } 4593 4594 kfree(dev->port); 4595 ib_dealloc_device(&dev->ib_dev); 4596} 4597 4598void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 4599 const struct mlx5_ib_profile *profile) 4600{ 4601 int err; 4602 int i; 4603 4604 dev->profile = profile; 4605 4606 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4607 if (profile->stage[i].init) { 4608 err = profile->stage[i].init(dev); 4609 if (err) 4610 goto err_out; 4611 } 4612 } 4613 4614 dev->ib_active = true; 4615 4616 return dev; 4617 4618err_out: 4619 __mlx5_ib_remove(dev, profile, i); 4620 4621 return NULL; 4622} 4623 4624static const struct mlx5_ib_profile pf_profile = { 4625 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4626 mlx5_ib_stage_init_init, 4627 mlx5_ib_stage_init_cleanup), 4628 STAGE_CREATE(MLX5_IB_STAGE_FS, 4629 mlx5_ib_fs_init, 4630 mlx5_ib_fs_cleanup), 4631 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4632 mlx5_ib_stage_caps_init, 4633 mlx5_ib_stage_caps_cleanup), 4634 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4635 mlx5_ib_stage_non_default_cb, 4636 NULL), 4637 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4638 mlx5_ib_roce_init, 4639 mlx5_ib_roce_cleanup), 4640 STAGE_CREATE(MLX5_IB_STAGE_QP, 4641 mlx5_init_qp_table, 4642 mlx5_cleanup_qp_table), 4643 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4644 mlx5_init_srq_table, 4645 mlx5_cleanup_srq_table), 4646 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4647 mlx5_ib_dev_res_init, 4648 mlx5_ib_dev_res_cleanup), 4649 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4650 mlx5_ib_stage_dev_notifier_init, 4651 mlx5_ib_stage_dev_notifier_cleanup), 4652 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4653 mlx5_ib_odp_init_one, 4654 mlx5_ib_odp_cleanup_one), 4655 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4656 mlx5_ib_counters_init, 4657 mlx5_ib_counters_cleanup), 4658 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4659 mlx5_ib_stage_cong_debugfs_init, 4660 mlx5_ib_stage_cong_debugfs_cleanup), 4661 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4662 mlx5_ib_stage_uar_init, 4663 mlx5_ib_stage_uar_cleanup), 4664 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4665 mlx5_ib_stage_bfrag_init, 4666 mlx5_ib_stage_bfrag_cleanup), 4667 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4668 NULL, 4669 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4670 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4671 mlx5_ib_devx_init, 4672 mlx5_ib_devx_cleanup), 4673 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4674 mlx5_ib_stage_ib_reg_init, 4675 mlx5_ib_stage_ib_reg_cleanup), 4676 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4677 mlx5_ib_stage_post_ib_reg_umr_init, 4678 NULL), 4679 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4680 mlx5_ib_stage_delay_drop_init, 4681 mlx5_ib_stage_delay_drop_cleanup), 4682 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4683 mlx5_ib_restrack_init, 4684 NULL), 4685}; 4686 4687const struct mlx5_ib_profile raw_eth_profile = { 4688 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4689 mlx5_ib_stage_init_init, 4690 mlx5_ib_stage_init_cleanup), 4691 STAGE_CREATE(MLX5_IB_STAGE_FS, 4692 mlx5_ib_fs_init, 4693 mlx5_ib_fs_cleanup), 4694 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4695 mlx5_ib_stage_caps_init, 4696 mlx5_ib_stage_caps_cleanup), 4697 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4698 mlx5_ib_stage_raw_eth_non_default_cb, 4699 NULL), 4700 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4701 mlx5_ib_roce_init, 4702 mlx5_ib_roce_cleanup), 4703 STAGE_CREATE(MLX5_IB_STAGE_QP, 4704 mlx5_init_qp_table, 4705 mlx5_cleanup_qp_table), 4706 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4707 mlx5_init_srq_table, 4708 mlx5_cleanup_srq_table), 4709 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4710 mlx5_ib_dev_res_init, 4711 mlx5_ib_dev_res_cleanup), 4712 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4713 mlx5_ib_stage_dev_notifier_init, 4714 mlx5_ib_stage_dev_notifier_cleanup), 4715 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4716 mlx5_ib_counters_init, 4717 mlx5_ib_counters_cleanup), 4718 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4719 mlx5_ib_stage_cong_debugfs_init, 4720 mlx5_ib_stage_cong_debugfs_cleanup), 4721 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4722 mlx5_ib_stage_uar_init, 4723 mlx5_ib_stage_uar_cleanup), 4724 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4725 mlx5_ib_stage_bfrag_init, 4726 mlx5_ib_stage_bfrag_cleanup), 4727 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4728 NULL, 4729 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4730 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4731 mlx5_ib_devx_init, 4732 mlx5_ib_devx_cleanup), 4733 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4734 mlx5_ib_stage_ib_reg_init, 4735 mlx5_ib_stage_ib_reg_cleanup), 4736 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4737 mlx5_ib_stage_post_ib_reg_umr_init, 4738 NULL), 4739 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4740 mlx5_ib_stage_delay_drop_init, 4741 mlx5_ib_stage_delay_drop_cleanup), 4742 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4743 mlx5_ib_restrack_init, 4744 NULL), 4745}; 4746 4747static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 4748{ 4749 struct mlx5_ib_multiport_info *mpi; 4750 struct mlx5_ib_dev *dev; 4751 bool bound = false; 4752 int err; 4753 4754 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4755 if (!mpi) 4756 return NULL; 4757 4758 mpi->mdev = mdev; 4759 4760 err = mlx5_query_nic_vport_system_image_guid(mdev, 4761 &mpi->sys_image_guid); 4762 if (err) { 4763 kfree(mpi); 4764 return NULL; 4765 } 4766 4767 mutex_lock(&mlx5_ib_multiport_mutex); 4768 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4769 if (dev->sys_image_guid == mpi->sys_image_guid) 4770 bound = mlx5_ib_bind_slave_port(dev, mpi); 4771 4772 if (bound) { 4773 rdma_roce_rescan_device(&dev->ib_dev); 4774 mpi->ibdev->ib_active = true; 4775 break; 4776 } 4777 } 4778 4779 if (!bound) { 4780 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4781 dev_dbg(mdev->device, 4782 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4783 } 4784 mutex_unlock(&mlx5_ib_multiport_mutex); 4785 4786 return mpi; 4787} 4788 4789static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 4790{ 4791 const struct mlx5_ib_profile *profile; 4792 enum rdma_link_layer ll; 4793 struct mlx5_ib_dev *dev; 4794 int port_type_cap; 4795 int num_ports; 4796 4797 if (MLX5_ESWITCH_MANAGER(mdev) && 4798 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) { 4799 if (!mlx5_core_mp_enabled(mdev)) 4800 mlx5_ib_register_vport_reps(mdev); 4801 return mdev; 4802 } 4803 4804 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4805 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4806 4807 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 4808 return mlx5_ib_add_slave_port(mdev); 4809 4810 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4811 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4812 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4813 if (!dev) 4814 return NULL; 4815 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4816 GFP_KERNEL); 4817 if (!dev->port) { 4818 ib_dealloc_device(&dev->ib_dev); 4819 return NULL; 4820 } 4821 4822 dev->mdev = mdev; 4823 dev->num_ports = num_ports; 4824 4825 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4826 profile = &raw_eth_profile; 4827 else 4828 profile = &pf_profile; 4829 4830 return __mlx5_ib_add(dev, profile); 4831} 4832 4833static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4834{ 4835 struct mlx5_ib_multiport_info *mpi; 4836 struct mlx5_ib_dev *dev; 4837 4838 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) { 4839 mlx5_ib_unregister_vport_reps(mdev); 4840 return; 4841 } 4842 4843 if (mlx5_core_is_mp_slave(mdev)) { 4844 mpi = context; 4845 mutex_lock(&mlx5_ib_multiport_mutex); 4846 if (mpi->ibdev) 4847 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4848 list_del(&mpi->list); 4849 mutex_unlock(&mlx5_ib_multiport_mutex); 4850 kfree(mpi); 4851 return; 4852 } 4853 4854 dev = context; 4855 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4856} 4857 4858static struct mlx5_interface mlx5_ib_interface = { 4859 .add = mlx5_ib_add, 4860 .remove = mlx5_ib_remove, 4861 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4862}; 4863 4864unsigned long mlx5_ib_get_xlt_emergency_page(void) 4865{ 4866 mutex_lock(&xlt_emergency_page_mutex); 4867 return xlt_emergency_page; 4868} 4869 4870void mlx5_ib_put_xlt_emergency_page(void) 4871{ 4872 mutex_unlock(&xlt_emergency_page_mutex); 4873} 4874 4875static int __init mlx5_ib_init(void) 4876{ 4877 int err; 4878 4879 xlt_emergency_page = __get_free_page(GFP_KERNEL); 4880 if (!xlt_emergency_page) 4881 return -ENOMEM; 4882 4883 mutex_init(&xlt_emergency_page_mutex); 4884 4885 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4886 if (!mlx5_ib_event_wq) { 4887 free_page(xlt_emergency_page); 4888 return -ENOMEM; 4889 } 4890 4891 mlx5_ib_odp_init(); 4892 4893 err = mlx5_register_interface(&mlx5_ib_interface); 4894 4895 return err; 4896} 4897 4898static void __exit mlx5_ib_cleanup(void) 4899{ 4900 mlx5_unregister_interface(&mlx5_ib_interface); 4901 destroy_workqueue(mlx5_ib_event_wq); 4902 mutex_destroy(&xlt_emergency_page_mutex); 4903 free_page(xlt_emergency_page); 4904} 4905 4906module_init(mlx5_ib_init); 4907module_exit(mlx5_ib_cleanup); 4908