1/*******************************************************************************
2*
3* Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
4*
5* This software is available to you under a choice of one of two
6* licenses.  You may choose to be licensed under the terms of the GNU
7* General Public License (GPL) Version 2, available from the file
8* COPYING in the main directory of this source tree, or the
9* OpenFabrics.org BSD license below:
10*
11*   Redistribution and use in source and binary forms, with or
12*   without modification, are permitted provided that the following
13*   conditions are met:
14*
15*    - Redistributions of source code must retain the above
16*	copyright notice, this list of conditions and the following
17*	disclaimer.
18*
19*    - Redistributions in binary form must reproduce the above
20*	copyright notice, this list of conditions and the following
21*	disclaimer in the documentation and/or other materials
22*	provided with the distribution.
23*
24* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31* SOFTWARE.
32*
33*******************************************************************************/
34
35#ifndef I40IW_HMC_H
36#define I40IW_HMC_H
37
38#include "i40iw_d.h"
39
40struct i40iw_hw;
41enum i40iw_status_code;
42
43#define I40IW_HMC_MAX_BP_COUNT 512
44#define I40IW_MAX_SD_ENTRIES 11
45#define I40IW_HW_DBG_HMC_INVALID_BP_MARK     0xCA
46
47#define I40IW_HMC_INFO_SIGNATURE	0x484D5347
48#define I40IW_HMC_PD_CNT_IN_SD		512
49#define I40IW_HMC_DIRECT_BP_SIZE	0x200000
50#define I40IW_HMC_MAX_SD_COUNT		4096
51#define I40IW_HMC_PAGED_BP_SIZE		4096
52#define I40IW_HMC_PD_BP_BUF_ALIGNMENT	4096
53#define I40IW_FIRST_VF_FPM_ID		16
54#define FPM_MULTIPLIER			1024
55
56#define I40IW_INC_SD_REFCNT(sd_table)   ((sd_table)->ref_cnt++)
57#define I40IW_INC_PD_REFCNT(pd_table)   ((pd_table)->ref_cnt++)
58#define I40IW_INC_BP_REFCNT(bp)         ((bp)->ref_cnt++)
59
60#define I40IW_DEC_SD_REFCNT(sd_table)   ((sd_table)->ref_cnt--)
61#define I40IW_DEC_PD_REFCNT(pd_table)   ((pd_table)->ref_cnt--)
62#define I40IW_DEC_BP_REFCNT(bp)         ((bp)->ref_cnt--)
63
64/**
65 * I40IW_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
66 * @hw: pointer to our hw struct
67 * @sd_idx: segment descriptor index
68 * @pd_idx: page descriptor index
69 */
70#define I40IW_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx)                  \
71	i40iw_wr32((hw), I40E_PFHMC_PDINV,                                    \
72		(((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) |             \
73		(0x1 << I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT) | \
74		((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
75
76/**
77 * I40IW_INVALIDATE_VF_HMC_PD - Invalidates the pd cache in the hardware
78 * @hw: pointer to our hw struct
79 * @sd_idx: segment descriptor index
80 * @pd_idx: page descriptor index
81 * @hmc_fn_id: VF's function id
82 */
83#define I40IW_INVALIDATE_VF_HMC_PD(hw, sd_idx, pd_idx, hmc_fn_id)        \
84	i40iw_wr32(hw, I40E_GLHMC_VFPDINV(hmc_fn_id - I40IW_FIRST_VF_FPM_ID),  \
85	     ((sd_idx << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) |              \
86	      (pd_idx << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
87
88struct i40iw_hmc_obj_info {
89	u64 base;
90	u32 max_cnt;
91	u32 cnt;
92	u64 size;
93};
94
95enum i40iw_sd_entry_type {
96	I40IW_SD_TYPE_INVALID = 0,
97	I40IW_SD_TYPE_PAGED = 1,
98	I40IW_SD_TYPE_DIRECT = 2
99};
100
101struct i40iw_hmc_bp {
102	enum i40iw_sd_entry_type entry_type;
103	struct i40iw_dma_mem addr;
104	u32 sd_pd_index;
105	u32 ref_cnt;
106};
107
108struct i40iw_hmc_pd_entry {
109	struct i40iw_hmc_bp bp;
110	u32 sd_index;
111	bool rsrc_pg;
112	bool valid;
113};
114
115struct i40iw_hmc_pd_table {
116	struct i40iw_dma_mem pd_page_addr;
117	struct i40iw_hmc_pd_entry *pd_entry;
118	struct i40iw_virt_mem pd_entry_virt_mem;
119	u32 ref_cnt;
120	u32 sd_index;
121};
122
123struct i40iw_hmc_sd_entry {
124	enum i40iw_sd_entry_type entry_type;
125	bool valid;
126
127	union {
128		struct i40iw_hmc_pd_table pd_table;
129		struct i40iw_hmc_bp bp;
130	} u;
131};
132
133struct i40iw_hmc_sd_table {
134	struct i40iw_virt_mem addr;
135	u32 sd_cnt;
136	u32 ref_cnt;
137	struct i40iw_hmc_sd_entry *sd_entry;
138};
139
140struct i40iw_hmc_info {
141	u32 signature;
142	u8 hmc_fn_id;
143	u16 first_sd_index;
144
145	struct i40iw_hmc_obj_info *hmc_obj;
146	struct i40iw_virt_mem hmc_obj_virt_mem;
147	struct i40iw_hmc_sd_table sd_table;
148	u16 sd_indexes[I40IW_HMC_MAX_SD_COUNT];
149};
150
151struct update_sd_entry {
152	u64 cmd;
153	u64 data;
154};
155
156struct i40iw_update_sds_info {
157	u32 cnt;
158	u8 hmc_fn_id;
159	struct update_sd_entry entry[I40IW_MAX_SD_ENTRIES];
160};
161
162struct i40iw_ccq_cqe_info;
163struct i40iw_hmc_fcn_info {
164	void (*callback_fcn)(struct i40iw_sc_dev *, void *,
165			     struct i40iw_ccq_cqe_info *);
166	void *cqp_callback_param;
167	u32 vf_id;
168	u16 iw_vf_idx;
169	bool free_fcn;
170};
171
172enum i40iw_hmc_rsrc_type {
173	I40IW_HMC_IW_QP = 0,
174	I40IW_HMC_IW_CQ = 1,
175	I40IW_HMC_IW_SRQ = 2,
176	I40IW_HMC_IW_HTE = 3,
177	I40IW_HMC_IW_ARP = 4,
178	I40IW_HMC_IW_APBVT_ENTRY = 5,
179	I40IW_HMC_IW_MR = 6,
180	I40IW_HMC_IW_XF = 7,
181	I40IW_HMC_IW_XFFL = 8,
182	I40IW_HMC_IW_Q1 = 9,
183	I40IW_HMC_IW_Q1FL = 10,
184	I40IW_HMC_IW_TIMER = 11,
185	I40IW_HMC_IW_FSIMC = 12,
186	I40IW_HMC_IW_FSIAV = 13,
187	I40IW_HMC_IW_PBLE = 14,
188	I40IW_HMC_IW_MAX = 15,
189};
190
191struct i40iw_hmc_create_obj_info {
192	struct i40iw_hmc_info *hmc_info;
193	struct i40iw_virt_mem add_sd_virt_mem;
194	u32 rsrc_type;
195	u32 start_idx;
196	u32 count;
197	u32 add_sd_cnt;
198	enum i40iw_sd_entry_type entry_type;
199	bool is_pf;
200};
201
202struct i40iw_hmc_del_obj_info {
203	struct i40iw_hmc_info *hmc_info;
204	struct i40iw_virt_mem del_sd_virt_mem;
205	u32 rsrc_type;
206	u32 start_idx;
207	u32 count;
208	u32 del_sd_cnt;
209	bool is_pf;
210};
211
212enum i40iw_status_code i40iw_copy_dma_mem(struct i40iw_hw *hw, void *dest_buf,
213					  struct i40iw_dma_mem *src_mem, u64 src_offset, u64 size);
214enum i40iw_status_code i40iw_sc_create_hmc_obj(struct i40iw_sc_dev *dev,
215					       struct i40iw_hmc_create_obj_info *info);
216enum i40iw_status_code i40iw_sc_del_hmc_obj(struct i40iw_sc_dev *dev,
217					    struct i40iw_hmc_del_obj_info *info,
218					    bool reset);
219enum i40iw_status_code i40iw_hmc_sd_one(struct i40iw_sc_dev *dev, u8 hmc_fn_id,
220					u64 pa, u32 sd_idx, enum i40iw_sd_entry_type type,
221					bool setsd);
222enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev,
223					      struct i40iw_update_sds_info *info);
224struct i40iw_vfdev *i40iw_vfdev_from_fpm(struct i40iw_sc_dev *dev, u8 hmc_fn_id);
225struct i40iw_hmc_info *i40iw_vf_hmcinfo_from_fpm(struct i40iw_sc_dev *dev,
226						 u8 hmc_fn_id);
227enum i40iw_status_code i40iw_add_sd_table_entry(struct i40iw_hw *hw,
228						struct i40iw_hmc_info *hmc_info, u32 sd_index,
229						enum i40iw_sd_entry_type type, u64 direct_mode_sz);
230enum i40iw_status_code i40iw_add_pd_table_entry(struct i40iw_hw *hw,
231						struct i40iw_hmc_info *hmc_info, u32 pd_index,
232						struct i40iw_dma_mem *rsrc_pg);
233enum i40iw_status_code i40iw_remove_pd_bp(struct i40iw_hw *hw,
234					  struct i40iw_hmc_info *hmc_info, u32 idx, bool is_pf);
235enum i40iw_status_code i40iw_prep_remove_sd_bp(struct i40iw_hmc_info *hmc_info, u32 idx);
236enum i40iw_status_code i40iw_prep_remove_pd_page(struct i40iw_hmc_info *hmc_info, u32 idx);
237
238#define     ENTER_SHARED_FUNCTION()
239#define     EXIT_SHARED_FUNCTION()
240
241#endif				/* I40IW_HMC_H */
242