1/* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef _HNS_ROCE_DEVICE_H 34#define _HNS_ROCE_DEVICE_H 35 36#include <rdma/ib_verbs.h> 37 38#define DRV_NAME "hns_roce" 39 40#define PCI_REVISION_ID_HIP08 0x21 41#define PCI_REVISION_ID_HIP09 0x30 42 43#define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 44 45#define HNS_ROCE_MAX_MSG_LEN 0x80000000 46 47#define HNS_ROCE_IB_MIN_SQ_STRIDE 6 48 49#define BA_BYTE_LEN 8 50 51/* Hardware specification only for v1 engine */ 52#define HNS_ROCE_MIN_CQE_NUM 0x40 53#define HNS_ROCE_MIN_WQE_NUM 0x20 54 55/* Hardware specification only for v1 engine */ 56#define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 57#define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 58 59#define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 60#define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 61 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 62#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 63#define HNS_ROCE_MIN_CQE_CNT 16 64 65#define HNS_ROCE_MAX_IRQ_NUM 128 66 67#define HNS_ROCE_SGE_IN_WQE 2 68#define HNS_ROCE_SGE_SHIFT 4 69 70#define EQ_ENABLE 1 71#define EQ_DISABLE 0 72 73#define HNS_ROCE_CEQ 0 74#define HNS_ROCE_AEQ 1 75 76#define HNS_ROCE_CEQE_SIZE 0x4 77#define HNS_ROCE_AEQE_SIZE 0x10 78 79#define HNS_ROCE_V3_EQE_SIZE 0x40 80 81#define HNS_ROCE_V2_CQE_SIZE 32 82#define HNS_ROCE_V3_CQE_SIZE 64 83 84#define HNS_ROCE_V2_QPC_SZ 256 85#define HNS_ROCE_V3_QPC_SZ 512 86 87#define HNS_ROCE_MAX_PORTS 6 88#define HNS_ROCE_GID_SIZE 16 89#define HNS_ROCE_SGE_SIZE 16 90 91#define HNS_ROCE_HOP_NUM_0 0xff 92 93#define BITMAP_NO_RR 0 94#define BITMAP_RR 1 95 96#define MR_TYPE_MR 0x00 97#define MR_TYPE_FRMR 0x01 98#define MR_TYPE_DMA 0x03 99 100#define HNS_ROCE_FRMR_MAX_PA 512 101 102#define PKEY_ID 0xffff 103#define GUID_LEN 8 104#define NODE_DESC_SIZE 64 105#define DB_REG_OFFSET 0x1000 106 107/* Configure to HW for PAGE_SIZE larger than 4KB */ 108#define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 109 110#define PAGES_SHIFT_8 8 111#define PAGES_SHIFT_16 16 112#define PAGES_SHIFT_24 24 113#define PAGES_SHIFT_32 32 114 115#define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 116#define SRQ_DB_REG 0x230 117 118/* The chip implementation of the consumer index is calculated 119 * according to twice the actual EQ depth 120 */ 121#define EQ_DEPTH_COEFF 2 122 123enum { 124 SERV_TYPE_RC, 125 SERV_TYPE_UC, 126 SERV_TYPE_RD, 127 SERV_TYPE_UD, 128}; 129 130enum { 131 HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0), 132 HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1), 133}; 134 135enum hns_roce_cq_flags { 136 HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0), 137}; 138 139enum hns_roce_qp_state { 140 HNS_ROCE_QP_STATE_RST, 141 HNS_ROCE_QP_STATE_INIT, 142 HNS_ROCE_QP_STATE_RTR, 143 HNS_ROCE_QP_STATE_RTS, 144 HNS_ROCE_QP_STATE_SQD, 145 HNS_ROCE_QP_STATE_ERR, 146 HNS_ROCE_QP_NUM_STATE, 147}; 148 149enum hns_roce_event { 150 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 151 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 152 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 153 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 154 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 155 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 156 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 157 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 158 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 159 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 160 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 161 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 162 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 163 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 164 /* 0x10 and 0x11 is unused in currently application case */ 165 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 166 HNS_ROCE_EVENT_TYPE_MB = 0x13, 167 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 168 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 169}; 170 171/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 172enum { 173 HNS_ROCE_LWQCE_QPC_ERROR = 1, 174 HNS_ROCE_LWQCE_MTU_ERROR = 2, 175 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 176 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 177 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 178 HNS_ROCE_LWQCE_SL_ERROR = 6, 179 HNS_ROCE_LWQCE_PORT_ERROR = 7, 180}; 181 182/* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 183enum { 184 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 185 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 186 HNS_ROCE_LAVWQE_VA_ERROR = 3, 187 HNS_ROCE_LAVWQE_PD_ERROR = 4, 188 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 189 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 190 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 191}; 192 193/* DOORBELL overflow subtype */ 194enum { 195 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 196 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 197 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 198 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 199 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 200 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 201}; 202 203enum { 204 /* RQ&SRQ related operations */ 205 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 206 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 207}; 208 209#define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 210 211enum { 212 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 213 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 214 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 215 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 216 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 217 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 218 HNS_ROCE_CAP_FLAG_MW = BIT(7), 219 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 220 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 221 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 222}; 223 224#define HNS_ROCE_DB_TYPE_COUNT 2 225#define HNS_ROCE_DB_UNIT_SIZE 4 226 227enum { 228 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 229}; 230 231enum hns_roce_reset_stage { 232 HNS_ROCE_STATE_NON_RST, 233 HNS_ROCE_STATE_RST_BEF_DOWN, 234 HNS_ROCE_STATE_RST_DOWN, 235 HNS_ROCE_STATE_RST_UNINIT, 236 HNS_ROCE_STATE_RST_INIT, 237 HNS_ROCE_STATE_RST_INITED, 238}; 239 240enum hns_roce_instance_state { 241 HNS_ROCE_STATE_NON_INIT, 242 HNS_ROCE_STATE_INIT, 243 HNS_ROCE_STATE_INITED, 244 HNS_ROCE_STATE_UNINIT, 245}; 246 247enum { 248 HNS_ROCE_RST_DIRECT_RETURN = 0, 249}; 250 251enum { 252 CMD_RST_PRC_OTHERS, 253 CMD_RST_PRC_SUCCESS, 254 CMD_RST_PRC_EBUSY, 255}; 256 257#define HNS_ROCE_CMD_SUCCESS 1 258 259#define HNS_ROCE_PORT_DOWN 0 260#define HNS_ROCE_PORT_UP 1 261 262/* The minimum page size is 4K for hardware */ 263#define HNS_HW_PAGE_SHIFT 12 264#define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 265 266/* The minimum page count for hardware access page directly. */ 267#define HNS_HW_DIRECT_PAGE_COUNT 2 268 269struct hns_roce_uar { 270 u64 pfn; 271 unsigned long index; 272 unsigned long logic_idx; 273}; 274 275struct hns_roce_ucontext { 276 struct ib_ucontext ibucontext; 277 struct hns_roce_uar uar; 278 struct list_head page_list; 279 struct mutex page_mutex; 280}; 281 282struct hns_roce_pd { 283 struct ib_pd ibpd; 284 unsigned long pdn; 285}; 286 287struct hns_roce_bitmap { 288 /* Bitmap Traversal last a bit which is 1 */ 289 unsigned long last; 290 unsigned long top; 291 unsigned long max; 292 unsigned long reserved_top; 293 unsigned long mask; 294 spinlock_t lock; 295 unsigned long *table; 296}; 297 298/* For Hardware Entry Memory */ 299struct hns_roce_hem_table { 300 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 301 u32 type; 302 /* HEM array elment num */ 303 unsigned long num_hem; 304 /* HEM entry record obj total num */ 305 unsigned long num_obj; 306 /* Single obj size */ 307 unsigned long obj_size; 308 unsigned long table_chunk_size; 309 int lowmem; 310 struct mutex mutex; 311 struct hns_roce_hem **hem; 312 u64 **bt_l1; 313 dma_addr_t *bt_l1_dma_addr; 314 u64 **bt_l0; 315 dma_addr_t *bt_l0_dma_addr; 316}; 317 318struct hns_roce_buf_region { 319 int offset; /* page offset */ 320 u32 count; /* page count */ 321 int hopnum; /* addressing hop num */ 322}; 323 324#define HNS_ROCE_MAX_BT_REGION 3 325#define HNS_ROCE_MAX_BT_LEVEL 3 326struct hns_roce_hem_list { 327 struct list_head root_bt; 328 /* link all bt dma mem by hop config */ 329 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 330 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 331 dma_addr_t root_ba; /* pointer to the root ba table */ 332}; 333 334struct hns_roce_buf_attr { 335 struct { 336 size_t size; /* region size */ 337 int hopnum; /* multi-hop addressing hop num */ 338 } region[HNS_ROCE_MAX_BT_REGION]; 339 int region_count; /* valid region count */ 340 unsigned int page_shift; /* buffer page shift */ 341 bool fixed_page; /* decide page shift is fixed-size or maximum size */ 342 int user_access; /* umem access flag */ 343 bool mtt_only; /* only alloc buffer-required MTT memory */ 344}; 345 346struct hns_roce_hem_cfg { 347 dma_addr_t root_ba; /* root BA table's address */ 348 bool is_direct; /* addressing without BA table */ 349 unsigned int ba_pg_shift; /* BA table page shift */ 350 unsigned int buf_pg_shift; /* buffer page shift */ 351 unsigned int buf_pg_count; /* buffer page count */ 352 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 353 int region_count; 354}; 355 356/* memory translate region */ 357struct hns_roce_mtr { 358 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 359 struct ib_umem *umem; /* user space buffer */ 360 struct hns_roce_buf *kmem; /* kernel space buffer */ 361 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 362}; 363 364struct hns_roce_mw { 365 struct ib_mw ibmw; 366 u32 pdn; 367 u32 rkey; 368 int enabled; /* MW's active status */ 369 u32 pbl_hop_num; 370 u32 pbl_ba_pg_sz; 371 u32 pbl_buf_pg_sz; 372}; 373 374/* Only support 4K page size for mr register */ 375#define MR_SIZE_4K 0 376 377struct hns_roce_mr { 378 struct ib_mr ibmr; 379 u64 iova; /* MR's virtual orignal addr */ 380 u64 size; /* Address range of MR */ 381 u32 key; /* Key of MR */ 382 u32 pd; /* PD num of MR */ 383 u32 access; /* Access permission of MR */ 384 int enabled; /* MR's active status */ 385 int type; /* MR's register type */ 386 u32 pbl_hop_num; /* multi-hop number */ 387 struct hns_roce_mtr pbl_mtr; 388 u32 npages; 389 dma_addr_t *page_list; 390}; 391 392struct hns_roce_mr_table { 393 struct hns_roce_bitmap mtpt_bitmap; 394 struct hns_roce_hem_table mtpt_table; 395}; 396 397struct hns_roce_wq { 398 u64 *wrid; /* Work request ID */ 399 spinlock_t lock; 400 u32 wqe_cnt; /* WQE num */ 401 int max_gs; 402 int offset; 403 int wqe_shift; /* WQE size */ 404 u32 head; 405 u32 tail; 406 void __iomem *db_reg_l; 407}; 408 409struct hns_roce_sge { 410 unsigned int sge_cnt; /* SGE num */ 411 int offset; 412 int sge_shift; /* SGE size */ 413}; 414 415struct hns_roce_buf_list { 416 void *buf; 417 dma_addr_t map; 418}; 419 420struct hns_roce_buf { 421 struct hns_roce_buf_list direct; 422 struct hns_roce_buf_list *page_list; 423 u32 npages; 424 u32 size; 425 unsigned int page_shift; 426}; 427 428struct hns_roce_db_pgdir { 429 struct list_head list; 430 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 431 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 432 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 433 u32 *page; 434 dma_addr_t db_dma; 435}; 436 437struct hns_roce_user_db_page { 438 struct list_head list; 439 struct ib_umem *umem; 440 unsigned long user_virt; 441 refcount_t refcount; 442}; 443 444struct hns_roce_db { 445 u32 *db_record; 446 union { 447 struct hns_roce_db_pgdir *pgdir; 448 struct hns_roce_user_db_page *user_page; 449 } u; 450 dma_addr_t dma; 451 void *virt_addr; 452 int index; 453 int order; 454}; 455 456struct hns_roce_cq { 457 struct ib_cq ib_cq; 458 struct hns_roce_mtr mtr; 459 struct hns_roce_db db; 460 u32 flags; 461 spinlock_t lock; 462 u32 cq_depth; 463 u32 cons_index; 464 u32 *set_ci_db; 465 void __iomem *cq_db_l; 466 u16 *tptr_addr; 467 int arm_sn; 468 int cqe_size; 469 unsigned long cqn; 470 u32 vector; 471 atomic_t refcount; 472 struct completion free; 473 struct list_head sq_list; /* all qps on this send cq */ 474 struct list_head rq_list; /* all qps on this recv cq */ 475 int is_armed; /* cq is armed */ 476 struct list_head node; /* all armed cqs are on a list */ 477}; 478 479struct hns_roce_idx_que { 480 struct hns_roce_mtr mtr; 481 int entry_shift; 482 unsigned long *bitmap; 483}; 484 485struct hns_roce_srq { 486 struct ib_srq ibsrq; 487 unsigned long srqn; 488 u32 wqe_cnt; 489 int max_gs; 490 int wqe_shift; 491 void __iomem *db_reg_l; 492 493 atomic_t refcount; 494 struct completion free; 495 496 struct hns_roce_mtr buf_mtr; 497 498 u64 *wrid; 499 struct hns_roce_idx_que idx_que; 500 spinlock_t lock; 501 int head; 502 int tail; 503 struct mutex mutex; 504 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 505}; 506 507struct hns_roce_uar_table { 508 struct hns_roce_bitmap bitmap; 509}; 510 511struct hns_roce_qp_table { 512 struct hns_roce_bitmap bitmap; 513 struct hns_roce_hem_table qp_table; 514 struct hns_roce_hem_table irrl_table; 515 struct hns_roce_hem_table trrl_table; 516 struct hns_roce_hem_table sccc_table; 517 struct mutex scc_mutex; 518}; 519 520struct hns_roce_cq_table { 521 struct hns_roce_bitmap bitmap; 522 struct xarray array; 523 struct hns_roce_hem_table table; 524}; 525 526struct hns_roce_srq_table { 527 struct hns_roce_bitmap bitmap; 528 struct xarray xa; 529 struct hns_roce_hem_table table; 530}; 531 532struct hns_roce_raq_table { 533 struct hns_roce_buf_list *e_raq_buf; 534}; 535 536struct hns_roce_av { 537 u8 port; 538 u8 gid_index; 539 u8 stat_rate; 540 u8 hop_limit; 541 u32 flowlabel; 542 u16 udp_sport; 543 u8 sl; 544 u8 tclass; 545 u8 dgid[HNS_ROCE_GID_SIZE]; 546 u8 mac[ETH_ALEN]; 547 u16 vlan_id; 548 u8 vlan_en; 549}; 550 551struct hns_roce_ah { 552 struct ib_ah ibah; 553 struct hns_roce_av av; 554}; 555 556struct hns_roce_cmd_context { 557 struct completion done; 558 int result; 559 int next; 560 u64 out_param; 561 u16 token; 562}; 563 564struct hns_roce_cmdq { 565 struct dma_pool *pool; 566 struct mutex hcr_mutex; 567 struct semaphore poll_sem; 568 /* 569 * Event mode: cmd register mutex protection, 570 * ensure to not exceed max_cmds and user use limit region 571 */ 572 struct semaphore event_sem; 573 int max_cmds; 574 spinlock_t context_lock; 575 int free_head; 576 struct hns_roce_cmd_context *context; 577 /* 578 * Result of get integer part 579 * which max_comds compute according a power of 2 580 */ 581 u16 token_mask; 582 /* 583 * Process whether use event mode, init default non-zero 584 * After the event queue of cmd event ready, 585 * can switch into event mode 586 * close device, switch into poll mode(non event mode) 587 */ 588 u8 use_events; 589}; 590 591struct hns_roce_cmd_mailbox { 592 void *buf; 593 dma_addr_t dma; 594}; 595 596struct hns_roce_dev; 597 598struct hns_roce_rinl_sge { 599 void *addr; 600 u32 len; 601}; 602 603struct hns_roce_rinl_wqe { 604 struct hns_roce_rinl_sge *sg_list; 605 u32 sge_cnt; 606}; 607 608struct hns_roce_rinl_buf { 609 struct hns_roce_rinl_wqe *wqe_list; 610 u32 wqe_cnt; 611}; 612 613enum { 614 HNS_ROCE_FLUSH_FLAG = 0, 615}; 616 617struct hns_roce_work { 618 struct hns_roce_dev *hr_dev; 619 struct work_struct work; 620 u32 qpn; 621 u32 cqn; 622 int event_type; 623 int sub_type; 624}; 625 626struct hns_roce_qp { 627 struct ib_qp ibqp; 628 struct hns_roce_wq rq; 629 struct hns_roce_db rdb; 630 struct hns_roce_db sdb; 631 unsigned long en_flags; 632 u32 doorbell_qpn; 633 enum ib_sig_type sq_signal_bits; 634 struct hns_roce_wq sq; 635 636 struct hns_roce_mtr mtr; 637 638 u32 buff_size; 639 struct mutex mutex; 640 u8 port; 641 u8 phy_port; 642 u8 sl; 643 u8 resp_depth; 644 u8 state; 645 u32 access_flags; 646 u32 atomic_rd_en; 647 u32 pkey_index; 648 u32 qkey; 649 void (*event)(struct hns_roce_qp *qp, 650 enum hns_roce_event event_type); 651 unsigned long qpn; 652 653 atomic_t refcount; 654 struct completion free; 655 656 struct hns_roce_sge sge; 657 u32 next_sge; 658 enum ib_mtu path_mtu; 659 u32 max_inline_data; 660 661 /* 0: flush needed, 1: unneeded */ 662 unsigned long flush_flag; 663 struct hns_roce_work flush_work; 664 struct hns_roce_rinl_buf rq_inl_buf; 665 struct list_head node; /* all qps are on a list */ 666 struct list_head rq_node; /* all recv qps are on a list */ 667 struct list_head sq_node; /* all send qps are on a list */ 668}; 669 670struct hns_roce_ib_iboe { 671 spinlock_t lock; 672 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 673 struct notifier_block nb; 674 u8 phy_port[HNS_ROCE_MAX_PORTS]; 675}; 676 677enum { 678 HNS_ROCE_EQ_STAT_INVALID = 0, 679 HNS_ROCE_EQ_STAT_VALID = 2, 680}; 681 682struct hns_roce_ceqe { 683 __le32 comp; 684 __le32 rsv[15]; 685}; 686 687struct hns_roce_aeqe { 688 __le32 asyn; 689 union { 690 struct { 691 __le32 qp; 692 u32 rsv0; 693 u32 rsv1; 694 } qp_event; 695 696 struct { 697 __le32 srq; 698 u32 rsv0; 699 u32 rsv1; 700 } srq_event; 701 702 struct { 703 __le32 cq; 704 u32 rsv0; 705 u32 rsv1; 706 } cq_event; 707 708 struct { 709 __le32 ceqe; 710 u32 rsv0; 711 u32 rsv1; 712 } ce_event; 713 714 struct { 715 __le64 out_param; 716 __le16 token; 717 u8 status; 718 u8 rsv0; 719 } __packed cmd; 720 } event; 721 __le32 rsv[12]; 722}; 723 724struct hns_roce_eq { 725 struct hns_roce_dev *hr_dev; 726 void __iomem *doorbell; 727 728 int type_flag; /* Aeq:1 ceq:0 */ 729 int eqn; 730 u32 entries; 731 int log_entries; 732 int eqe_size; 733 int irq; 734 int log_page_size; 735 int cons_index; 736 struct hns_roce_buf_list *buf_list; 737 int over_ignore; 738 int coalesce; 739 int arm_st; 740 int hop_num; 741 struct hns_roce_mtr mtr; 742 u16 eq_max_cnt; 743 int eq_period; 744 int shift; 745 int event_type; 746 int sub_type; 747}; 748 749struct hns_roce_eq_table { 750 struct hns_roce_eq *eq; 751 void __iomem **eqc_base; /* only for hw v1 */ 752}; 753 754struct hns_roce_caps { 755 u64 fw_ver; 756 u8 num_ports; 757 int gid_table_len[HNS_ROCE_MAX_PORTS]; 758 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 759 int local_ca_ack_delay; 760 int num_uars; 761 u32 phy_num_uars; 762 u32 max_sq_sg; 763 u32 max_sq_inline; 764 u32 max_rq_sg; 765 u32 max_extend_sg; 766 int num_qps; 767 int reserved_qps; 768 int num_qpc_timer; 769 int num_cqc_timer; 770 int num_srqs; 771 u32 max_wqes; 772 u32 max_srq_wrs; 773 u32 max_srq_sges; 774 u32 max_sq_desc_sz; 775 u32 max_rq_desc_sz; 776 u32 max_srq_desc_sz; 777 int max_qp_init_rdma; 778 int max_qp_dest_rdma; 779 int num_cqs; 780 u32 max_cqes; 781 u32 min_cqes; 782 u32 min_wqes; 783 int reserved_cqs; 784 int reserved_srqs; 785 int num_aeq_vectors; 786 int num_comp_vectors; 787 int num_other_vectors; 788 int num_mtpts; 789 u32 num_mtt_segs; 790 u32 num_cqe_segs; 791 u32 num_srqwqe_segs; 792 u32 num_idx_segs; 793 int reserved_mrws; 794 int reserved_uars; 795 int num_pds; 796 int reserved_pds; 797 u32 mtt_entry_sz; 798 u32 cqe_sz; 799 u32 page_size_cap; 800 u32 reserved_lkey; 801 int mtpt_entry_sz; 802 int qpc_sz; 803 int irrl_entry_sz; 804 int trrl_entry_sz; 805 int cqc_entry_sz; 806 int sccc_sz; 807 int qpc_timer_entry_sz; 808 int cqc_timer_entry_sz; 809 int srqc_entry_sz; 810 int idx_entry_sz; 811 u32 pbl_ba_pg_sz; 812 u32 pbl_buf_pg_sz; 813 u32 pbl_hop_num; 814 int aeqe_depth; 815 int ceqe_depth; 816 u32 aeqe_size; 817 u32 ceqe_size; 818 enum ib_mtu max_mtu; 819 u32 qpc_bt_num; 820 u32 qpc_timer_bt_num; 821 u32 srqc_bt_num; 822 u32 cqc_bt_num; 823 u32 cqc_timer_bt_num; 824 u32 mpt_bt_num; 825 u32 sccc_bt_num; 826 u32 qpc_ba_pg_sz; 827 u32 qpc_buf_pg_sz; 828 u32 qpc_hop_num; 829 u32 srqc_ba_pg_sz; 830 u32 srqc_buf_pg_sz; 831 u32 srqc_hop_num; 832 u32 cqc_ba_pg_sz; 833 u32 cqc_buf_pg_sz; 834 u32 cqc_hop_num; 835 u32 mpt_ba_pg_sz; 836 u32 mpt_buf_pg_sz; 837 u32 mpt_hop_num; 838 u32 mtt_ba_pg_sz; 839 u32 mtt_buf_pg_sz; 840 u32 mtt_hop_num; 841 u32 wqe_sq_hop_num; 842 u32 wqe_sge_hop_num; 843 u32 wqe_rq_hop_num; 844 u32 sccc_ba_pg_sz; 845 u32 sccc_buf_pg_sz; 846 u32 sccc_hop_num; 847 u32 qpc_timer_ba_pg_sz; 848 u32 qpc_timer_buf_pg_sz; 849 u32 qpc_timer_hop_num; 850 u32 cqc_timer_ba_pg_sz; 851 u32 cqc_timer_buf_pg_sz; 852 u32 cqc_timer_hop_num; 853 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 854 u32 cqe_buf_pg_sz; 855 u32 cqe_hop_num; 856 u32 srqwqe_ba_pg_sz; 857 u32 srqwqe_buf_pg_sz; 858 u32 srqwqe_hop_num; 859 u32 idx_ba_pg_sz; 860 u32 idx_buf_pg_sz; 861 u32 idx_hop_num; 862 u32 eqe_ba_pg_sz; 863 u32 eqe_buf_pg_sz; 864 u32 eqe_hop_num; 865 u32 sl_num; 866 u32 tsq_buf_pg_sz; 867 u32 tpq_buf_pg_sz; 868 u32 chunk_sz; /* chunk size in non multihop mode */ 869 u64 flags; 870 u16 default_ceq_max_cnt; 871 u16 default_ceq_period; 872 u16 default_aeq_max_cnt; 873 u16 default_aeq_period; 874 u16 default_aeq_arm_st; 875 u16 default_ceq_arm_st; 876}; 877 878struct hns_roce_dfx_hw { 879 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 880 int *buffer); 881}; 882 883enum hns_roce_device_state { 884 HNS_ROCE_DEVICE_STATE_INITED, 885 HNS_ROCE_DEVICE_STATE_RST_DOWN, 886 HNS_ROCE_DEVICE_STATE_UNINIT, 887}; 888 889struct hns_roce_hw { 890 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 891 int (*cmq_init)(struct hns_roce_dev *hr_dev); 892 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 893 int (*hw_profile)(struct hns_roce_dev *hr_dev); 894 int (*hw_init)(struct hns_roce_dev *hr_dev); 895 void (*hw_exit)(struct hns_roce_dev *hr_dev); 896 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 897 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 898 u16 token, int event); 899 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); 900 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); 901 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 902 const union ib_gid *gid, const struct ib_gid_attr *attr); 903 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 904 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 905 enum ib_mtu mtu); 906 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 907 struct hns_roce_mr *mr, unsigned long mtpt_idx); 908 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 909 struct hns_roce_mr *mr, int flags, u32 pdn, 910 int mr_access_flags, u64 iova, u64 size, 911 void *mb_buf); 912 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 913 struct hns_roce_mr *mr); 914 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 915 void (*write_cqc)(struct hns_roce_dev *hr_dev, 916 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 917 dma_addr_t dma_handle); 918 int (*set_hem)(struct hns_roce_dev *hr_dev, 919 struct hns_roce_hem_table *table, int obj, int step_idx); 920 int (*clear_hem)(struct hns_roce_dev *hr_dev, 921 struct hns_roce_hem_table *table, int obj, 922 int step_idx); 923 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 924 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 925 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 926 int attr_mask, enum ib_qp_state cur_state, 927 enum ib_qp_state new_state); 928 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); 929 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 930 struct hns_roce_qp *hr_qp); 931 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 932 const struct ib_send_wr **bad_wr); 933 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 934 const struct ib_recv_wr **bad_recv_wr); 935 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 936 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 937 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 938 struct ib_udata *udata); 939 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 940 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 941 int (*init_eq)(struct hns_roce_dev *hr_dev); 942 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 943 void (*write_srqc)(struct hns_roce_dev *hr_dev, 944 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, 945 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, 946 dma_addr_t dma_handle_wqe, 947 dma_addr_t dma_handle_idx); 948 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 949 enum ib_srq_attr_mask srq_attr_mask, 950 struct ib_udata *udata); 951 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); 952 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 953 const struct ib_recv_wr **bad_wr); 954 const struct ib_device_ops *hns_roce_dev_ops; 955 const struct ib_device_ops *hns_roce_dev_srq_ops; 956}; 957 958struct hns_roce_dev { 959 struct ib_device ib_dev; 960 struct platform_device *pdev; 961 struct pci_dev *pci_dev; 962 struct device *dev; 963 struct hns_roce_uar priv_uar; 964 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 965 spinlock_t sm_lock; 966 spinlock_t bt_cmd_lock; 967 bool active; 968 bool is_reset; 969 bool dis_db; 970 unsigned long reset_cnt; 971 struct hns_roce_ib_iboe iboe; 972 enum hns_roce_device_state state; 973 struct list_head qp_list; /* list of all qps on this dev */ 974 spinlock_t qp_list_lock; /* protect qp_list */ 975 976 struct list_head pgdir_list; 977 struct mutex pgdir_mutex; 978 int irq[HNS_ROCE_MAX_IRQ_NUM]; 979 u8 __iomem *reg_base; 980 struct hns_roce_caps caps; 981 struct xarray qp_table_xa; 982 983 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 984 u64 sys_image_guid; 985 u32 vendor_id; 986 u32 vendor_part_id; 987 u32 hw_rev; 988 void __iomem *priv_addr; 989 990 struct hns_roce_cmdq cmd; 991 struct hns_roce_bitmap pd_bitmap; 992 struct hns_roce_uar_table uar_table; 993 struct hns_roce_mr_table mr_table; 994 struct hns_roce_cq_table cq_table; 995 struct hns_roce_srq_table srq_table; 996 struct hns_roce_qp_table qp_table; 997 struct hns_roce_eq_table eq_table; 998 struct hns_roce_hem_table qpc_timer_table; 999 struct hns_roce_hem_table cqc_timer_table; 1000 1001 int cmd_mod; 1002 int loop_idc; 1003 u32 sdb_offset; 1004 u32 odb_offset; 1005 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 1006 u32 tptr_size; /* only for hw v1 */ 1007 const struct hns_roce_hw *hw; 1008 void *priv; 1009 struct workqueue_struct *irq_workq; 1010 const struct hns_roce_dfx_hw *dfx; 1011}; 1012 1013static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1014{ 1015 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1016} 1017 1018static inline struct hns_roce_ucontext 1019 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1020{ 1021 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1022} 1023 1024static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1025{ 1026 return container_of(ibpd, struct hns_roce_pd, ibpd); 1027} 1028 1029static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1030{ 1031 return container_of(ibah, struct hns_roce_ah, ibah); 1032} 1033 1034static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1035{ 1036 return container_of(ibmr, struct hns_roce_mr, ibmr); 1037} 1038 1039static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1040{ 1041 return container_of(ibmw, struct hns_roce_mw, ibmw); 1042} 1043 1044static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1045{ 1046 return container_of(ibqp, struct hns_roce_qp, ibqp); 1047} 1048 1049static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1050{ 1051 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1052} 1053 1054static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1055{ 1056 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1057} 1058 1059static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1060{ 1061 __raw_writeq(*(u64 *) val, dest); 1062} 1063 1064static inline struct hns_roce_qp 1065 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1066{ 1067 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1068} 1069 1070static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf) 1071{ 1072 if (buf->page_list) 1073 return false; 1074 1075 return true; 1076} 1077 1078static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 1079{ 1080 if (hns_roce_buf_is_direct(buf)) 1081 return (char *)(buf->direct.buf) + (offset & (buf->size - 1)); 1082 1083 return (char *)(buf->page_list[offset >> buf->page_shift].buf) + 1084 (offset & ((1 << buf->page_shift) - 1)); 1085} 1086 1087static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx) 1088{ 1089 if (hns_roce_buf_is_direct(buf)) 1090 return buf->direct.map + ((dma_addr_t)idx << buf->page_shift); 1091 else 1092 return buf->page_list[idx].map; 1093} 1094 1095#define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1096 1097static inline u64 to_hr_hw_page_addr(u64 addr) 1098{ 1099 return addr >> HNS_HW_PAGE_SHIFT; 1100} 1101 1102static inline u32 to_hr_hw_page_shift(u32 page_shift) 1103{ 1104 return page_shift - HNS_HW_PAGE_SHIFT; 1105} 1106 1107static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1108{ 1109 if (count > 0) 1110 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1111 1112 return 0; 1113} 1114 1115static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1116{ 1117 return hr_hw_page_align(count << buf_shift); 1118} 1119 1120static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1121{ 1122 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1123} 1124 1125static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1126{ 1127 if (!count) 1128 return 0; 1129 1130 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1131} 1132 1133#define DSCP_SHIFT 2 1134 1135static inline u8 get_tclass(const struct ib_global_route *grh) 1136{ 1137 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1138 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1139} 1140 1141int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1142int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1143void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1144void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1145 1146int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1147void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1148void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1149 u64 out_param); 1150int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1151void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1152 1153/* hns roce hw need current block and next block addr from mtt */ 1154#define MTT_MIN_COUNT 2 1155int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1156 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1157int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1158 struct hns_roce_buf_attr *buf_attr, 1159 unsigned int page_shift, struct ib_udata *udata, 1160 unsigned long user_addr); 1161void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1162 struct hns_roce_mtr *mtr); 1163int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1164 dma_addr_t *pages, int page_cnt); 1165 1166int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1167int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1168int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1169int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1170int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1171 1172void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1173void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1174void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1175void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1176void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1177void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1178 1179int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1180void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1181 int rr); 1182int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1183 u32 reserved_bot, u32 resetrved_top); 1184void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1185void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1186int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1187 int align, unsigned long *obj); 1188void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1189 unsigned long obj, int cnt, 1190 int rr); 1191 1192int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1193 struct ib_udata *udata); 1194int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1195static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1196{ 1197 return 0; 1198} 1199 1200int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1201int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1202 1203struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1204struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1205 u64 virt_addr, int access_flags, 1206 struct ib_udata *udata); 1207int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, 1208 u64 virt_addr, int mr_access_flags, struct ib_pd *pd, 1209 struct ib_udata *udata); 1210struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1211 u32 max_num_sg); 1212int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1213 unsigned int *sg_offset); 1214int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1215int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1216 struct hns_roce_cmd_mailbox *mailbox, 1217 unsigned long mpt_index); 1218unsigned long key_to_hw_index(u32 key); 1219 1220int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1221int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1222 1223void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1224int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 1225 struct hns_roce_buf *buf, u32 page_shift); 1226 1227int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1228 int buf_cnt, int start, struct hns_roce_buf *buf); 1229int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1230 int buf_cnt, int start, struct ib_umem *umem, 1231 unsigned int page_shift); 1232 1233int hns_roce_create_srq(struct ib_srq *srq, 1234 struct ib_srq_init_attr *srq_init_attr, 1235 struct ib_udata *udata); 1236int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1237 enum ib_srq_attr_mask srq_attr_mask, 1238 struct ib_udata *udata); 1239int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1240 1241struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1242 struct ib_qp_init_attr *init_attr, 1243 struct ib_udata *udata); 1244int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1245 int attr_mask, struct ib_udata *udata); 1246void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1247void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 1248void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n); 1249void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n); 1250bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1251 struct ib_cq *ib_cq); 1252enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1253void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1254 struct hns_roce_cq *recv_cq); 1255void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1256 struct hns_roce_cq *recv_cq); 1257void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1258void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1259 struct ib_udata *udata); 1260__be32 send_ieth(const struct ib_send_wr *wr); 1261int to_hr_qp_type(int qp_type); 1262 1263int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1264 struct ib_udata *udata); 1265 1266int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1267int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1268 struct ib_udata *udata, unsigned long virt, 1269 struct hns_roce_db *db); 1270void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1271 struct hns_roce_db *db); 1272int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1273 int order); 1274void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1275 1276void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1277void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1278void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1279void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1280int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1281void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1282int hns_roce_init(struct hns_roce_dev *hr_dev); 1283void hns_roce_exit(struct hns_roce_dev *hr_dev); 1284 1285int hns_roce_fill_res_cq_entry(struct sk_buff *msg, 1286 struct ib_cq *ib_cq); 1287#endif /* _HNS_ROCE_DEVICE_H */ 1288