1/* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef _HNS_ROCE_COMMON_H 34#define _HNS_ROCE_COMMON_H 35 36#define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) 37#define roce_read(dev, reg) readl((dev)->reg_base + (reg)) 38#define roce_raw_write(value, addr) \ 39 __raw_writel((__force u32)cpu_to_le32(value), (addr)) 40 41#define roce_get_field(origin, mask, shift) \ 42 (((le32_to_cpu(origin)) & (mask)) >> (shift)) 43 44#define roce_get_bit(origin, shift) \ 45 roce_get_field((origin), (1ul << (shift)), (shift)) 46 47#define roce_set_field(origin, mask, shift, val) \ 48 do { \ 49 (origin) &= ~cpu_to_le32(mask); \ 50 (origin) |= cpu_to_le32(((u32)(val) << (shift)) & (mask)); \ 51 } while (0) 52 53#define roce_set_bit(origin, shift, val) \ 54 roce_set_field((origin), (1ul << (shift)), (shift), (val)) 55 56#define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3 57#define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4 58 59#define ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S 5 60 61#define ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S 6 62 63#define ROCEE_GLB_CFG_ROCEE_PORT_ST_S 10 64#define ROCEE_GLB_CFG_ROCEE_PORT_ST_M \ 65 (((1UL << 6) - 1) << ROCEE_GLB_CFG_ROCEE_PORT_ST_S) 66 67#define ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S 16 68 69#define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0 70#define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M \ 71 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S) 72 73#define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S 24 74#define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M \ 75 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S) 76 77#define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0 78#define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M \ 79 (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S) 80 81#define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S 24 82#define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M \ 83 (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S) 84 85#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0 86#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M \ 87 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S) 88 89#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S 16 90#define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M \ 91 (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S) 92 93#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0 94#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M \ 95 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S) 96 97#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S 16 98#define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M \ 99 (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S) 100 101#define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0 102#define ROCEE_RAQ_WL_ROCEE_RAQ_WL_M \ 103 (((1UL << 8) - 1) << ROCEE_RAQ_WL_ROCEE_RAQ_WL_S) 104 105#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0 106#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M \ 107 (((1UL << 15) - 1) << \ 108 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S) 109 110#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S 16 111#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M \ 112 (((1UL << 4) - 1) << \ 113 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S) 114 115#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S 20 116 117#define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE 21 118 119#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0 120#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M \ 121 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S) 122 123#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S 5 124#define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M \ 125 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S) 126 127#define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0 128#define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M \ 129 (((1UL << 5) - 1) << ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S) 130 131#define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S 5 132#define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M \ 133 (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S) 134 135#define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0 136#define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M \ 137 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S) 138 139#define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S 8 140#define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M \ 141 (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S) 142 143#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S 0 144#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M \ 145 (((1UL << 19) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S) 146 147#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_S 19 148 149#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S 20 150#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M \ 151 (((1UL << 2) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S) 152 153#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S 22 154#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M \ 155 (((1UL << 5) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S) 156 157#define ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S 31 158 159#define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S 0 160#define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M \ 161 (((1UL << 3) - 1) << ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S) 162 163#define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S 0 164#define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M \ 165 (((1UL << 15) - 1) << ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S) 166 167#define ROCEE_MB6_ROCEE_MB_CMD_S 0 168#define ROCEE_MB6_ROCEE_MB_CMD_M \ 169 (((1UL << 8) - 1) << ROCEE_MB6_ROCEE_MB_CMD_S) 170 171#define ROCEE_MB6_ROCEE_MB_CMD_MDF_S 8 172#define ROCEE_MB6_ROCEE_MB_CMD_MDF_M \ 173 (((1UL << 4) - 1) << ROCEE_MB6_ROCEE_MB_CMD_MDF_S) 174 175#define ROCEE_MB6_ROCEE_MB_EVENT_S 14 176 177#define ROCEE_MB6_ROCEE_MB_HW_RUN_S 15 178 179#define ROCEE_MB6_ROCEE_MB_TOKEN_S 16 180#define ROCEE_MB6_ROCEE_MB_TOKEN_M \ 181 (((1UL << 16) - 1) << ROCEE_MB6_ROCEE_MB_TOKEN_S) 182 183#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S 0 184#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M \ 185 (((1UL << 24) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S) 186 187#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S 24 188#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M \ 189 (((1UL << 4) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S) 190 191#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S 28 192#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M \ 193 (((1UL << 3) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S) 194 195#define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S 31 196 197#define ROCEE_SMAC_H_ROCEE_SMAC_H_S 0 198#define ROCEE_SMAC_H_ROCEE_SMAC_H_M \ 199 (((1UL << 16) - 1) << ROCEE_SMAC_H_ROCEE_SMAC_H_S) 200 201#define ROCEE_SMAC_H_ROCEE_PORT_MTU_S 16 202#define ROCEE_SMAC_H_ROCEE_PORT_MTU_M \ 203 (((1UL << 4) - 1) << ROCEE_SMAC_H_ROCEE_PORT_MTU_S) 204 205#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S 0 206#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M \ 207 (((1UL << 2) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S) 208 209#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S 8 210#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M \ 211 (((1UL << 4) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S) 212 213#define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S 17 214 215#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S 0 216#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M \ 217 (((1UL << 5) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S) 218 219#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S 16 220#define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M \ 221 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S) 222 223#define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S 0 224#define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M \ 225 (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S) 226 227#define ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S 16 228#define ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S 1 229#define ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S 0 230 231#define ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S 0 232#define ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S 1 233 234#define ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S 0 235 236#define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S 0 237#define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M \ 238 (((1UL << 28) - 1) << ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) 239 240#define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S 0 241#define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \ 242 (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) 243 244#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0 245#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \ 246 (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S) 247 248#define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S 0 249#define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M \ 250 (((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S) 251 252#define ROCEE_SDB_CNT_CMP_BITS 16 253 254#define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S 20 255 256#define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0 257 258/*************ROCEE_REG DEFINITION****************/ 259#define ROCEE_VENDOR_ID_REG 0x0 260#define ROCEE_VENDOR_PART_ID_REG 0x4 261 262#define ROCEE_SYS_IMAGE_GUID_L_REG 0xC 263#define ROCEE_SYS_IMAGE_GUID_H_REG 0x10 264 265#define ROCEE_PORT_GID_L_0_REG 0x50 266#define ROCEE_PORT_GID_ML_0_REG 0x54 267#define ROCEE_PORT_GID_MH_0_REG 0x58 268#define ROCEE_PORT_GID_H_0_REG 0x5C 269 270#define ROCEE_BT_CMD_H_REG 0x204 271 272#define ROCEE_SMAC_L_0_REG 0x240 273#define ROCEE_SMAC_H_0_REG 0x244 274 275#define ROCEE_QP1C_CFG3_0_REG 0x27C 276 277#define ROCEE_CAEP_AEQE_CONS_IDX_REG 0x3AC 278#define ROCEE_CAEP_CEQC_CONS_IDX_0_REG 0x3BC 279 280#define ROCEE_ECC_UCERR_ALM1_REG 0xB38 281#define ROCEE_ECC_UCERR_ALM2_REG 0xB3C 282#define ROCEE_ECC_CERR_ALM1_REG 0xB44 283#define ROCEE_ECC_CERR_ALM2_REG 0xB48 284 285#define ROCEE_ACK_DELAY_REG 0x14 286#define ROCEE_GLB_CFG_REG 0x18 287 288#define ROCEE_DMAE_USER_CFG1_REG 0x40 289#define ROCEE_DMAE_USER_CFG2_REG 0x44 290 291#define ROCEE_DB_SQ_WL_REG 0x154 292#define ROCEE_DB_OTHERS_WL_REG 0x158 293#define ROCEE_RAQ_WL_REG 0x15C 294#define ROCEE_WRMS_POL_TIME_INTERVAL_REG 0x160 295#define ROCEE_EXT_DB_SQ_REG 0x164 296#define ROCEE_EXT_DB_SQ_H_REG 0x168 297#define ROCEE_EXT_DB_OTH_REG 0x16C 298 299#define ROCEE_EXT_DB_OTH_H_REG 0x170 300#define ROCEE_EXT_DB_SQ_WL_EMPTY_REG 0x174 301#define ROCEE_EXT_DB_SQ_WL_REG 0x178 302#define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG 0x17C 303#define ROCEE_EXT_DB_OTHERS_WL_REG 0x180 304#define ROCEE_EXT_RAQ_REG 0x184 305#define ROCEE_EXT_RAQ_H_REG 0x188 306 307#define ROCEE_CAEP_CE_INTERVAL_CFG_REG 0x190 308#define ROCEE_CAEP_CE_BURST_NUM_CFG_REG 0x194 309#define ROCEE_BT_CMD_L_REG 0x200 310 311#define ROCEE_MB1_REG 0x210 312#define ROCEE_MB6_REG 0x224 313#define ROCEE_DB_SQ_L_0_REG 0x230 314#define ROCEE_DB_OTHERS_L_0_REG 0x238 315#define ROCEE_QP1C_CFG0_0_REG 0x270 316 317#define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG 0x3A0 318#define ROCEE_CAEP_CEQC_SHIFT_0_REG 0x3B0 319#define ROCEE_CAEP_CE_IRQ_MASK_0_REG 0x3C0 320#define ROCEE_CAEP_CEQ_ALM_OVF_0_REG 0x3C4 321#define ROCEE_CAEP_AE_MASK_REG 0x6C8 322#define ROCEE_CAEP_AE_ST_REG 0x6CC 323 324#define ROCEE_CAEP_CQE_WCMD_EMPTY 0x850 325#define ROCEE_SCAEP_WR_CQE_CNT 0x8D0 326#define ROCEE_ECC_UCERR_ALM0_REG 0xB34 327#define ROCEE_ECC_CERR_ALM0_REG 0xB40 328 329/* V2 ROCEE REG */ 330#define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000 331#define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004 332#define ROCEE_TX_CMQ_DEPTH_REG 0x07008 333#define ROCEE_TX_CMQ_TAIL_REG 0x07010 334#define ROCEE_TX_CMQ_HEAD_REG 0x07014 335 336#define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018 337#define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c 338#define ROCEE_RX_CMQ_DEPTH_REG 0x07020 339#define ROCEE_RX_CMQ_TAIL_REG 0x07024 340#define ROCEE_RX_CMQ_HEAD_REG 0x07028 341 342#define ROCEE_VF_EQ_DB_CFG0_REG 0x238 343#define ROCEE_VF_EQ_DB_CFG1_REG 0x23C 344 345#define ROCEE_VF_ABN_INT_CFG_REG 0x13000 346#define ROCEE_VF_ABN_INT_ST_REG 0x13004 347#define ROCEE_VF_ABN_INT_EN_REG 0x13008 348#define ROCEE_VF_EVENT_INT_EN_REG 0x1300c 349 350#endif /* _HNS_ROCE_COMMON_H */ 351