1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2/*
3 * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6#ifndef _EFA_COM_H_
7#define _EFA_COM_H_
8
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/dma-mapping.h>
12#include <linux/semaphore.h>
13#include <linux/sched.h>
14
15#include <rdma/ib_verbs.h>
16
17#include "efa_common_defs.h"
18#include "efa_admin_defs.h"
19#include "efa_admin_cmds_defs.h"
20#include "efa_regs_defs.h"
21
22#define EFA_MAX_HANDLERS 256
23
24struct efa_com_admin_cq {
25	struct efa_admin_acq_entry *entries;
26	dma_addr_t dma_addr;
27	spinlock_t lock; /* Protects ACQ */
28
29	u16 cc; /* consumer counter */
30	u8 phase;
31};
32
33struct efa_com_admin_sq {
34	struct efa_admin_aq_entry *entries;
35	dma_addr_t dma_addr;
36	spinlock_t lock; /* Protects ASQ */
37
38	u32 __iomem *db_addr;
39
40	u16 cc; /* consumer counter */
41	u16 pc; /* producer counter */
42	u8 phase;
43
44};
45
46/* Don't use anything other than atomic64 */
47struct efa_com_stats_admin {
48	atomic64_t submitted_cmd;
49	atomic64_t completed_cmd;
50	atomic64_t cmd_err;
51	atomic64_t no_completion;
52};
53
54enum {
55	EFA_AQ_STATE_RUNNING_BIT = 0,
56	EFA_AQ_STATE_POLLING_BIT = 1,
57};
58
59struct efa_com_admin_queue {
60	void *dmadev;
61	void *efa_dev;
62	struct efa_comp_ctx *comp_ctx;
63	u32 completion_timeout; /* usecs */
64	u16 poll_interval; /* msecs */
65	u16 depth;
66	struct efa_com_admin_cq cq;
67	struct efa_com_admin_sq sq;
68	u16 msix_vector_idx;
69
70	unsigned long state;
71
72	/* Count the number of available admin commands */
73	struct semaphore avail_cmds;
74
75	struct efa_com_stats_admin stats;
76
77	spinlock_t comp_ctx_lock; /* Protects completion context pool */
78	u32 *comp_ctx_pool;
79	u16 comp_ctx_pool_next;
80};
81
82struct efa_aenq_handlers;
83
84struct efa_com_aenq {
85	struct efa_admin_aenq_entry *entries;
86	struct efa_aenq_handlers *aenq_handlers;
87	dma_addr_t dma_addr;
88	u32 cc; /* consumer counter */
89	u16 msix_vector_idx;
90	u16 depth;
91	u8 phase;
92};
93
94struct efa_com_mmio_read {
95	struct efa_admin_mmio_req_read_less_resp *read_resp;
96	dma_addr_t read_resp_dma_addr;
97	u16 seq_num;
98	u16 mmio_read_timeout; /* usecs */
99	/* serializes mmio reads */
100	spinlock_t lock;
101};
102
103struct efa_com_dev {
104	struct efa_com_admin_queue aq;
105	struct efa_com_aenq aenq;
106	u8 __iomem *reg_bar;
107	void *dmadev;
108	void *efa_dev;
109	u32 supported_features;
110	u32 dma_addr_bits;
111
112	struct efa_com_mmio_read mmio_read;
113};
114
115typedef void (*efa_aenq_handler)(void *data,
116	      struct efa_admin_aenq_entry *aenq_e);
117
118/* Holds aenq handlers. Indexed by AENQ event group */
119struct efa_aenq_handlers {
120	efa_aenq_handler handlers[EFA_MAX_HANDLERS];
121	efa_aenq_handler unimplemented_handler;
122};
123
124int efa_com_admin_init(struct efa_com_dev *edev,
125		       struct efa_aenq_handlers *aenq_handlers);
126void efa_com_admin_destroy(struct efa_com_dev *edev);
127int efa_com_dev_reset(struct efa_com_dev *edev,
128		      enum efa_regs_reset_reason_types reset_reason);
129void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling);
130void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev);
131int efa_com_mmio_reg_read_init(struct efa_com_dev *edev);
132void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev);
133
134int efa_com_validate_version(struct efa_com_dev *edev);
135int efa_com_get_dma_width(struct efa_com_dev *edev);
136
137int efa_com_cmd_exec(struct efa_com_admin_queue *aq,
138		     struct efa_admin_aq_entry *cmd,
139		     size_t cmd_size,
140		     struct efa_admin_acq_entry *comp,
141		     size_t comp_size);
142void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data);
143
144#endif /* _EFA_COM_H_ */
145