1/* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface 37 */ 38 39#define dev_fmt(fmt) "QPLIB: " fmt 40 41#include <linux/interrupt.h> 42#include <linux/spinlock.h> 43#include <linux/pci.h> 44#include <linux/prefetch.h> 45#include <linux/delay.h> 46 47#include "roce_hsi.h" 48#include "qplib_res.h" 49#include "qplib_rcfw.h" 50#include "qplib_sp.h" 51#include "qplib_fp.h" 52 53static void bnxt_qplib_service_creq(struct tasklet_struct *t); 54 55/* Hardware communication channel */ 56static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 57{ 58 struct bnxt_qplib_cmdq_ctx *cmdq; 59 u16 cbit; 60 int rc; 61 62 cmdq = &rcfw->cmdq; 63 cbit = cookie % rcfw->cmdq_depth; 64 rc = wait_event_timeout(cmdq->waitq, 65 !test_bit(cbit, cmdq->cmdq_bitmap), 66 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS)); 67 return rc ? 0 : -ETIMEDOUT; 68}; 69 70static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 71{ 72 u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT; 73 struct bnxt_qplib_cmdq_ctx *cmdq; 74 u16 cbit; 75 76 cmdq = &rcfw->cmdq; 77 cbit = cookie % rcfw->cmdq_depth; 78 if (!test_bit(cbit, cmdq->cmdq_bitmap)) 79 goto done; 80 do { 81 mdelay(1); /* 1m sec */ 82 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); 83 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); 84done: 85 return count ? 0 : -ETIMEDOUT; 86}; 87 88static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req, 89 struct creq_base *resp, void *sb, u8 is_block) 90{ 91 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 92 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; 93 struct bnxt_qplib_crsqe *crsqe; 94 struct bnxt_qplib_cmdqe *cmdqe; 95 u32 sw_prod, cmdq_prod; 96 struct pci_dev *pdev; 97 unsigned long flags; 98 u32 size, opcode; 99 u16 cookie, cbit; 100 u8 *preq; 101 102 pdev = rcfw->pdev; 103 104 opcode = req->opcode; 105 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 106 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC && 107 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW && 108 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) { 109 dev_err(&pdev->dev, 110 "RCFW not initialized, reject opcode 0x%x\n", opcode); 111 return -EINVAL; 112 } 113 114 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 115 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) { 116 dev_err(&pdev->dev, "RCFW already initialized!\n"); 117 return -EINVAL; 118 } 119 120 if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags)) 121 return -ETIMEDOUT; 122 123 /* Cmdq are in 16-byte units, each request can consume 1 or more 124 * cmdqe 125 */ 126 spin_lock_irqsave(&hwq->lock, flags); 127 if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) { 128 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n"); 129 spin_unlock_irqrestore(&hwq->lock, flags); 130 return -EAGAIN; 131 } 132 133 134 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 135 cbit = cookie % rcfw->cmdq_depth; 136 if (is_block) 137 cookie |= RCFW_CMD_IS_BLOCKING; 138 139 set_bit(cbit, cmdq->cmdq_bitmap); 140 req->cookie = cpu_to_le16(cookie); 141 crsqe = &rcfw->crsqe_tbl[cbit]; 142 if (crsqe->resp) { 143 spin_unlock_irqrestore(&hwq->lock, flags); 144 return -EBUSY; 145 } 146 147 size = req->cmd_size; 148 /* change the cmd_size to the number of 16byte cmdq unit. 149 * req->cmd_size is modified here 150 */ 151 bnxt_qplib_set_cmd_slots(req); 152 153 memset(resp, 0, sizeof(*resp)); 154 crsqe->resp = (struct creq_qp_event *)resp; 155 crsqe->resp->cookie = req->cookie; 156 crsqe->req_size = req->cmd_size; 157 if (req->resp_size && sb) { 158 struct bnxt_qplib_rcfw_sbuf *sbuf = sb; 159 160 req->resp_addr = cpu_to_le64(sbuf->dma_addr); 161 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) / 162 BNXT_QPLIB_CMDQE_UNITS; 163 } 164 165 preq = (u8 *)req; 166 do { 167 /* Locate the next cmdq slot */ 168 sw_prod = HWQ_CMP(hwq->prod, hwq); 169 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL); 170 if (!cmdqe) { 171 dev_err(&pdev->dev, 172 "RCFW request failed with no cmdqe!\n"); 173 goto done; 174 } 175 /* Copy a segment of the req cmd to the cmdq */ 176 memset(cmdqe, 0, sizeof(*cmdqe)); 177 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe))); 178 preq += min_t(u32, size, sizeof(*cmdqe)); 179 size -= min_t(u32, size, sizeof(*cmdqe)); 180 hwq->prod++; 181 } while (size > 0); 182 cmdq->seq_num++; 183 184 cmdq_prod = hwq->prod & 0xFFFF; 185 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) { 186 /* The very first doorbell write 187 * is required to set this flag 188 * which prompts the FW to reset 189 * its internal pointers 190 */ 191 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); 192 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 193 } 194 195 /* ring CMDQ DB */ 196 wmb(); 197 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 198 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 199done: 200 spin_unlock_irqrestore(&hwq->lock, flags); 201 /* Return the CREQ response pointer */ 202 return 0; 203} 204 205int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 206 struct cmdq_base *req, 207 struct creq_base *resp, 208 void *sb, u8 is_block) 209{ 210 struct creq_qp_event *evnt = (struct creq_qp_event *)resp; 211 u16 cookie; 212 u8 opcode, retry_cnt = 0xFF; 213 int rc = 0; 214 215 do { 216 opcode = req->opcode; 217 rc = __send_message(rcfw, req, resp, sb, is_block); 218 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE; 219 if (!rc) 220 break; 221 222 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) { 223 /* send failed */ 224 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n", 225 cookie, opcode); 226 return rc; 227 } 228 is_block ? mdelay(1) : usleep_range(500, 1000); 229 230 } while (retry_cnt--); 231 232 if (is_block) 233 rc = __block_for_resp(rcfw, cookie); 234 else 235 rc = __wait_for_resp(rcfw, cookie); 236 if (rc) { 237 /* timed out */ 238 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n", 239 cookie, opcode, RCFW_CMD_WAIT_TIME_MS); 240 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags); 241 return rc; 242 } 243 244 if (evnt->status) { 245 /* failed with status */ 246 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n", 247 cookie, opcode, evnt->status); 248 rc = -EFAULT; 249 } 250 251 return rc; 252} 253/* Completions */ 254static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, 255 struct creq_func_event *func_event) 256{ 257 int rc; 258 259 switch (func_event->event) { 260 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 261 break; 262 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 263 break; 264 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 265 break; 266 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 267 break; 268 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 269 break; 270 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 271 break; 272 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 273 break; 274 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 275 /* SRQ ctx error, call srq_handler?? 276 * But there's no SRQ handle! 277 */ 278 break; 279 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 280 break; 281 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 282 break; 283 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 284 break; 285 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST: 286 break; 287 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED: 288 break; 289 default: 290 return -EINVAL; 291 } 292 293 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL); 294 return rc; 295} 296 297static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 298 struct creq_qp_event *qp_event, 299 u32 *num_wait) 300{ 301 struct creq_qp_error_notification *err_event; 302 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq; 303 struct bnxt_qplib_crsqe *crsqe; 304 struct bnxt_qplib_qp *qp; 305 u16 cbit, blocked = 0; 306 struct pci_dev *pdev; 307 unsigned long flags; 308 u32 wait_cmds = 0; 309 __le16 mcookie; 310 u16 cookie; 311 int rc = 0; 312 u32 qp_id, tbl_indx; 313 314 pdev = rcfw->pdev; 315 switch (qp_event->event) { 316 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 317 err_event = (struct creq_qp_error_notification *)qp_event; 318 qp_id = le32_to_cpu(err_event->xid); 319 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw); 320 qp = rcfw->qp_tbl[tbl_indx].qp_handle; 321 dev_dbg(&pdev->dev, "Received QP error notification\n"); 322 dev_dbg(&pdev->dev, 323 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 324 qp_id, err_event->req_err_state_reason, 325 err_event->res_err_state_reason); 326 if (!qp) 327 break; 328 bnxt_qplib_mark_qp_error(qp); 329 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp); 330 break; 331 default: 332 /* 333 * Command Response 334 * cmdq->lock needs to be acquired to synchronie 335 * the command send and completion reaping. This function 336 * is always called with creq->lock held. Using 337 * the nested variant of spin_lock. 338 * 339 */ 340 341 spin_lock_irqsave_nested(&hwq->lock, flags, 342 SINGLE_DEPTH_NESTING); 343 cookie = le16_to_cpu(qp_event->cookie); 344 mcookie = qp_event->cookie; 345 blocked = cookie & RCFW_CMD_IS_BLOCKING; 346 cookie &= RCFW_MAX_COOKIE_VALUE; 347 cbit = cookie % rcfw->cmdq_depth; 348 crsqe = &rcfw->crsqe_tbl[cbit]; 349 if (crsqe->resp && 350 crsqe->resp->cookie == mcookie) { 351 memcpy(crsqe->resp, qp_event, sizeof(*qp_event)); 352 crsqe->resp = NULL; 353 } else { 354 if (crsqe->resp && crsqe->resp->cookie) 355 dev_err(&pdev->dev, 356 "CMD %s cookie sent=%#x, recd=%#x\n", 357 crsqe->resp ? "mismatch" : "collision", 358 crsqe->resp ? crsqe->resp->cookie : 0, 359 mcookie); 360 } 361 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap)) 362 dev_warn(&pdev->dev, 363 "CMD bit %d was not requested\n", cbit); 364 hwq->cons += crsqe->req_size; 365 crsqe->req_size = 0; 366 367 if (!blocked) 368 wait_cmds++; 369 spin_unlock_irqrestore(&hwq->lock, flags); 370 } 371 *num_wait += wait_cmds; 372 return rc; 373} 374 375/* SP - CREQ Completion handlers */ 376static void bnxt_qplib_service_creq(struct tasklet_struct *t) 377{ 378 struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet); 379 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq; 380 u32 type, budget = CREQ_ENTRY_POLL_BUDGET; 381 struct bnxt_qplib_hwq *hwq = &creq->hwq; 382 struct creq_base *creqe; 383 u32 sw_cons, raw_cons; 384 unsigned long flags; 385 u32 num_wakeup = 0; 386 387 /* Service the CREQ until budget is over */ 388 spin_lock_irqsave(&hwq->lock, flags); 389 raw_cons = hwq->cons; 390 while (budget > 0) { 391 sw_cons = HWQ_CMP(raw_cons, hwq); 392 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL); 393 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements)) 394 break; 395 /* The valid test of the entry must be done first before 396 * reading any further. 397 */ 398 dma_rmb(); 399 400 type = creqe->type & CREQ_BASE_TYPE_MASK; 401 switch (type) { 402 case CREQ_BASE_TYPE_QP_EVENT: 403 bnxt_qplib_process_qp_event 404 (rcfw, (struct creq_qp_event *)creqe, 405 &num_wakeup); 406 creq->stats.creq_qp_event_processed++; 407 break; 408 case CREQ_BASE_TYPE_FUNC_EVENT: 409 if (!bnxt_qplib_process_func_event 410 (rcfw, (struct creq_func_event *)creqe)) 411 creq->stats.creq_func_event_processed++; 412 else 413 dev_warn(&rcfw->pdev->dev, 414 "aeqe:%#x Not handled\n", type); 415 break; 416 default: 417 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT) 418 dev_warn(&rcfw->pdev->dev, 419 "creqe with event 0x%x not handled\n", 420 type); 421 break; 422 } 423 raw_cons++; 424 budget--; 425 } 426 427 if (hwq->cons != raw_cons) { 428 hwq->cons = raw_cons; 429 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, 430 rcfw->res->cctx, true); 431 } 432 spin_unlock_irqrestore(&hwq->lock, flags); 433 if (num_wakeup) 434 wake_up_nr(&rcfw->cmdq.waitq, num_wakeup); 435} 436 437static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) 438{ 439 struct bnxt_qplib_rcfw *rcfw = dev_instance; 440 struct bnxt_qplib_creq_ctx *creq; 441 struct bnxt_qplib_hwq *hwq; 442 u32 sw_cons; 443 444 creq = &rcfw->creq; 445 hwq = &creq->hwq; 446 /* Prefetch the CREQ element */ 447 sw_cons = HWQ_CMP(hwq->cons, hwq); 448 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL)); 449 450 tasklet_schedule(&creq->creq_tasklet); 451 452 return IRQ_HANDLED; 453} 454 455/* RCFW */ 456int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw) 457{ 458 struct cmdq_deinitialize_fw req; 459 struct creq_deinitialize_fw_resp resp; 460 u16 cmd_flags = 0; 461 int rc; 462 463 RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags); 464 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 465 NULL, 0); 466 if (rc) 467 return rc; 468 469 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 470 return 0; 471} 472 473int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 474 struct bnxt_qplib_ctx *ctx, int is_virtfn) 475{ 476 struct creq_initialize_fw_resp resp; 477 struct cmdq_initialize_fw req; 478 u16 cmd_flags = 0; 479 u8 pgsz, lvl; 480 int rc; 481 482 RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags); 483 /* Supply (log-base-2-of-host-page-size - base-page-shift) 484 * to bono to adjust the doorbell page sizes. 485 */ 486 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT - 487 RCFW_DBR_BASE_PAGE_SHIFT); 488 /* 489 * Gen P5 devices doesn't require this allocation 490 * as the L2 driver does the same for RoCE also. 491 * Also, VFs need not setup the HW context area, PF 492 * shall setup this area for VF. Skipping the 493 * HW programming 494 */ 495 if (is_virtfn) 496 goto skip_ctx_setup; 497 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 498 goto config_vf_res; 499 500 lvl = ctx->qpc_tbl.level; 501 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl); 502 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 503 lvl; 504 lvl = ctx->mrw_tbl.level; 505 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl); 506 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 507 lvl; 508 lvl = ctx->srqc_tbl.level; 509 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl); 510 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 511 lvl; 512 lvl = ctx->cq_tbl.level; 513 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl); 514 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 515 lvl; 516 lvl = ctx->tim_tbl.level; 517 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl); 518 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 519 lvl; 520 lvl = ctx->tqm_ctx.pde.level; 521 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde); 522 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 523 lvl; 524 req.qpc_page_dir = 525 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 526 req.mrw_page_dir = 527 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 528 req.srq_page_dir = 529 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 530 req.cq_page_dir = 531 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 532 req.tim_page_dir = 533 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 534 req.tqm_page_dir = 535 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]); 536 537 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements); 538 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements); 539 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements); 540 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements); 541 542config_vf_res: 543 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 544 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 545 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 546 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 547 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 548 549skip_ctx_setup: 550 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id); 551 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 552 NULL, 0); 553 if (rc) 554 return rc; 555 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 556 return 0; 557} 558 559void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 560{ 561 kfree(rcfw->cmdq.cmdq_bitmap); 562 kfree(rcfw->qp_tbl); 563 kfree(rcfw->crsqe_tbl); 564 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq); 565 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq); 566 rcfw->pdev = NULL; 567} 568 569int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 570 struct bnxt_qplib_rcfw *rcfw, 571 struct bnxt_qplib_ctx *ctx, 572 int qp_tbl_sz) 573{ 574 struct bnxt_qplib_hwq_attr hwq_attr = {}; 575 struct bnxt_qplib_sg_info sginfo = {}; 576 struct bnxt_qplib_cmdq_ctx *cmdq; 577 struct bnxt_qplib_creq_ctx *creq; 578 u32 bmap_size = 0; 579 580 rcfw->pdev = res->pdev; 581 cmdq = &rcfw->cmdq; 582 creq = &rcfw->creq; 583 rcfw->res = res; 584 585 sginfo.pgsize = PAGE_SIZE; 586 sginfo.pgshft = PAGE_SHIFT; 587 588 hwq_attr.sginfo = &sginfo; 589 hwq_attr.res = rcfw->res; 590 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT; 591 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS; 592 hwq_attr.type = bnxt_qplib_get_hwq_type(res); 593 594 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) { 595 dev_err(&rcfw->pdev->dev, 596 "HW channel CREQ allocation failed\n"); 597 goto fail; 598 } 599 if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK) 600 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256; 601 else 602 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192; 603 604 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth); 605 hwq_attr.depth = rcfw->cmdq_depth & 0x7FFFFFFF; 606 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS; 607 hwq_attr.type = HWQ_TYPE_CTX; 608 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { 609 dev_err(&rcfw->pdev->dev, 610 "HW channel CMDQ allocation failed\n"); 611 goto fail; 612 } 613 614 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements, 615 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL); 616 if (!rcfw->crsqe_tbl) 617 goto fail; 618 619 bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long); 620 cmdq->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL); 621 if (!cmdq->cmdq_bitmap) 622 goto fail; 623 624 /* Allocate one extra to hold the QP1 entries */ 625 rcfw->qp_tbl_size = qp_tbl_sz + 1; 626 rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node), 627 GFP_KERNEL); 628 if (!rcfw->qp_tbl) 629 goto fail; 630 631 return 0; 632 633fail: 634 bnxt_qplib_free_rcfw_channel(rcfw); 635 return -ENOMEM; 636} 637 638void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill) 639{ 640 struct bnxt_qplib_creq_ctx *creq; 641 642 creq = &rcfw->creq; 643 644 if (!creq->requested) 645 return; 646 647 tasklet_disable(&creq->creq_tasklet); 648 /* Mask h/w interrupts */ 649 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false); 650 /* Sync with last running IRQ-handler */ 651 synchronize_irq(creq->msix_vec); 652 if (kill) 653 tasklet_kill(&creq->creq_tasklet); 654 655 free_irq(creq->msix_vec, rcfw); 656 kfree(creq->irq_name); 657 creq->irq_name = NULL; 658 creq->requested = false; 659} 660 661void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 662{ 663 struct bnxt_qplib_creq_ctx *creq; 664 struct bnxt_qplib_cmdq_ctx *cmdq; 665 unsigned long indx; 666 667 creq = &rcfw->creq; 668 cmdq = &rcfw->cmdq; 669 /* Make sure the HW channel is stopped! */ 670 bnxt_qplib_rcfw_stop_irq(rcfw, true); 671 672 iounmap(cmdq->cmdq_mbox.reg.bar_reg); 673 iounmap(creq->creq_db.reg.bar_reg); 674 675 indx = find_first_bit(cmdq->cmdq_bitmap, rcfw->cmdq_depth); 676 if (indx != rcfw->cmdq_depth) 677 dev_err(&rcfw->pdev->dev, 678 "disabling RCFW with pending cmd-bit %lx\n", indx); 679 680 cmdq->cmdq_mbox.reg.bar_reg = NULL; 681 creq->creq_db.reg.bar_reg = NULL; 682 creq->aeq_handler = NULL; 683 creq->msix_vec = 0; 684} 685 686int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 687 bool need_init) 688{ 689 struct bnxt_qplib_creq_ctx *creq; 690 struct bnxt_qplib_res *res; 691 int rc; 692 693 creq = &rcfw->creq; 694 res = rcfw->res; 695 696 if (creq->requested) 697 return -EFAULT; 698 699 creq->msix_vec = msix_vector; 700 if (need_init) 701 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq); 702 else 703 tasklet_enable(&creq->creq_tasklet); 704 705 creq->irq_name = kasprintf(GFP_KERNEL, "bnxt_re-creq@pci:%s", 706 pci_name(res->pdev)); 707 if (!creq->irq_name) 708 return -ENOMEM; 709 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0, 710 creq->irq_name, rcfw); 711 if (rc) { 712 kfree(creq->irq_name); 713 creq->irq_name = NULL; 714 tasklet_disable(&creq->creq_tasklet); 715 return rc; 716 } 717 creq->requested = true; 718 719 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, res->cctx, true); 720 721 return 0; 722} 723 724static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf) 725{ 726 struct bnxt_qplib_cmdq_mbox *mbox; 727 resource_size_t bar_reg; 728 struct pci_dev *pdev; 729 u16 prod_offt; 730 int rc = 0; 731 732 pdev = rcfw->pdev; 733 mbox = &rcfw->cmdq.cmdq_mbox; 734 735 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION; 736 mbox->reg.len = RCFW_COMM_SIZE; 737 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id); 738 if (!mbox->reg.bar_base) { 739 dev_err(&pdev->dev, 740 "QPLIB: CMDQ BAR region %d resc start is 0!\n", 741 mbox->reg.bar_id); 742 return -ENOMEM; 743 } 744 745 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET; 746 mbox->reg.len = RCFW_COMM_SIZE; 747 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len); 748 if (!mbox->reg.bar_reg) { 749 dev_err(&pdev->dev, 750 "QPLIB: CMDQ BAR region %d mapping failed\n", 751 mbox->reg.bar_id); 752 return -ENOMEM; 753 } 754 755 prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET : 756 RCFW_PF_COMM_PROD_OFFSET; 757 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt); 758 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET); 759 return rc; 760} 761 762static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt) 763{ 764 struct bnxt_qplib_creq_db *creq_db; 765 resource_size_t bar_reg; 766 struct pci_dev *pdev; 767 768 pdev = rcfw->pdev; 769 creq_db = &rcfw->creq.creq_db; 770 771 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION; 772 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id); 773 if (!creq_db->reg.bar_id) 774 dev_err(&pdev->dev, 775 "QPLIB: CREQ BAR region %d resc start is 0!", 776 creq_db->reg.bar_id); 777 778 bar_reg = creq_db->reg.bar_base + reg_offt; 779 /* Unconditionally map 8 bytes to support 57500 series */ 780 creq_db->reg.len = 8; 781 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len); 782 if (!creq_db->reg.bar_reg) { 783 dev_err(&pdev->dev, 784 "QPLIB: CREQ BAR region %d mapping failed", 785 creq_db->reg.bar_id); 786 return -ENOMEM; 787 } 788 creq_db->dbinfo.db = creq_db->reg.bar_reg; 789 creq_db->dbinfo.hwq = &rcfw->creq.hwq; 790 creq_db->dbinfo.xid = rcfw->creq.ring_id; 791 return 0; 792} 793 794static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw) 795{ 796 struct bnxt_qplib_cmdq_ctx *cmdq; 797 struct bnxt_qplib_creq_ctx *creq; 798 struct bnxt_qplib_cmdq_mbox *mbox; 799 struct cmdq_init init = {0}; 800 801 cmdq = &rcfw->cmdq; 802 creq = &rcfw->creq; 803 mbox = &cmdq->cmdq_mbox; 804 805 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 806 init.cmdq_size_cmdq_lvl = 807 cpu_to_le16(((rcfw->cmdq_depth << 808 CMDQ_INIT_CMDQ_SIZE_SFT) & 809 CMDQ_INIT_CMDQ_SIZE_MASK) | 810 ((cmdq->hwq.level << 811 CMDQ_INIT_CMDQ_LVL_SFT) & 812 CMDQ_INIT_CMDQ_LVL_MASK)); 813 init.creq_ring_id = cpu_to_le16(creq->ring_id); 814 /* Write to the Bono mailbox register */ 815 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4); 816} 817 818int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 819 int msix_vector, 820 int cp_bar_reg_off, int virt_fn, 821 aeq_handler_t aeq_handler) 822{ 823 struct bnxt_qplib_cmdq_ctx *cmdq; 824 struct bnxt_qplib_creq_ctx *creq; 825 int rc; 826 827 cmdq = &rcfw->cmdq; 828 creq = &rcfw->creq; 829 830 /* Clear to defaults */ 831 832 cmdq->seq_num = 0; 833 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 834 init_waitqueue_head(&cmdq->waitq); 835 836 creq->stats.creq_qp_event_processed = 0; 837 creq->stats.creq_func_event_processed = 0; 838 creq->aeq_handler = aeq_handler; 839 840 rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn); 841 if (rc) 842 return rc; 843 844 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off); 845 if (rc) 846 return rc; 847 848 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true); 849 if (rc) { 850 dev_err(&rcfw->pdev->dev, 851 "Failed to request IRQ for CREQ rc = 0x%x\n", rc); 852 bnxt_qplib_disable_rcfw_channel(rcfw); 853 return rc; 854 } 855 856 bnxt_qplib_start_rcfw(rcfw); 857 858 return 0; 859} 860 861struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 862 struct bnxt_qplib_rcfw *rcfw, 863 u32 size) 864{ 865 struct bnxt_qplib_rcfw_sbuf *sbuf; 866 867 sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC); 868 if (!sbuf) 869 return NULL; 870 871 sbuf->size = size; 872 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size, 873 &sbuf->dma_addr, GFP_ATOMIC); 874 if (!sbuf->sb) 875 goto bail; 876 877 return sbuf; 878bail: 879 kfree(sbuf); 880 return NULL; 881} 882 883void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 884 struct bnxt_qplib_rcfw_sbuf *sbuf) 885{ 886 if (sbuf->sb) 887 dma_free_coherent(&rcfw->pdev->dev, sbuf->size, 888 sbuf->sb, sbuf->dma_addr); 889 kfree(sbuf); 890} 891