1/* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39#include <linux/interrupt.h> 40#include <linux/types.h> 41#include <linux/pci.h> 42#include <linux/netdevice.h> 43#include <linux/if_ether.h> 44 45#include <rdma/ib_verbs.h> 46#include <rdma/ib_user_verbs.h> 47#include <rdma/ib_umem.h> 48#include <rdma/ib_addr.h> 49#include <rdma/ib_mad.h> 50#include <rdma/ib_cache.h> 51#include <rdma/uverbs_ioctl.h> 52 53#include "bnxt_ulp.h" 54 55#include "roce_hsi.h" 56#include "qplib_res.h" 57#include "qplib_sp.h" 58#include "qplib_fp.h" 59#include "qplib_rcfw.h" 60 61#include "bnxt_re.h" 62#include "ib_verbs.h" 63#include <rdma/bnxt_re-abi.h> 64 65static int __from_ib_access_flags(int iflags) 66{ 67 int qflags = 0; 68 69 if (iflags & IB_ACCESS_LOCAL_WRITE) 70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 71 if (iflags & IB_ACCESS_REMOTE_READ) 72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 73 if (iflags & IB_ACCESS_REMOTE_WRITE) 74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 75 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 77 if (iflags & IB_ACCESS_MW_BIND) 78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 79 if (iflags & IB_ZERO_BASED) 80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 81 if (iflags & IB_ACCESS_ON_DEMAND) 82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 83 return qflags; 84}; 85 86static enum ib_access_flags __to_ib_access_flags(int qflags) 87{ 88 enum ib_access_flags iflags = 0; 89 90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 91 iflags |= IB_ACCESS_LOCAL_WRITE; 92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 93 iflags |= IB_ACCESS_REMOTE_WRITE; 94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 95 iflags |= IB_ACCESS_REMOTE_READ; 96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 97 iflags |= IB_ACCESS_REMOTE_ATOMIC; 98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 99 iflags |= IB_ACCESS_MW_BIND; 100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 101 iflags |= IB_ZERO_BASED; 102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 103 iflags |= IB_ACCESS_ON_DEMAND; 104 return iflags; 105}; 106 107static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 108 struct bnxt_qplib_sge *sg_list, int num) 109{ 110 int i, total = 0; 111 112 for (i = 0; i < num; i++) { 113 sg_list[i].addr = ib_sg_list[i].addr; 114 sg_list[i].lkey = ib_sg_list[i].lkey; 115 sg_list[i].size = ib_sg_list[i].length; 116 total += sg_list[i].size; 117 } 118 return total; 119} 120 121/* Device */ 122int bnxt_re_query_device(struct ib_device *ibdev, 123 struct ib_device_attr *ib_attr, 124 struct ib_udata *udata) 125{ 126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 128 129 memset(ib_attr, 0, sizeof(*ib_attr)); 130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 131 min(sizeof(dev_attr->fw_ver), 132 sizeof(ib_attr->fw_ver))); 133 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 134 (u8 *)&ib_attr->sys_image_guid); 135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M; 137 138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 141 ib_attr->max_qp = dev_attr->max_qp; 142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 143 ib_attr->device_cap_flags = 144 IB_DEVICE_CURR_QP_STATE_MOD 145 | IB_DEVICE_RC_RNR_NAK_GEN 146 | IB_DEVICE_SHUTDOWN_PORT 147 | IB_DEVICE_SYS_IMAGE_GUID 148 | IB_DEVICE_LOCAL_DMA_LKEY 149 | IB_DEVICE_RESIZE_MAX_WR 150 | IB_DEVICE_PORT_ACTIVE_EVENT 151 | IB_DEVICE_N_NOTIFY_CQ 152 | IB_DEVICE_MEM_WINDOW 153 | IB_DEVICE_MEM_WINDOW_TYPE_2B 154 | IB_DEVICE_MEM_MGT_EXTENSIONS; 155 ib_attr->max_send_sge = dev_attr->max_qp_sges; 156 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 157 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 158 ib_attr->max_cq = dev_attr->max_cq; 159 ib_attr->max_cqe = dev_attr->max_cq_wqes; 160 ib_attr->max_mr = dev_attr->max_mr; 161 ib_attr->max_pd = dev_attr->max_pd; 162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 164 ib_attr->atomic_cap = IB_ATOMIC_NONE; 165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 166 167 ib_attr->max_ee_rd_atom = 0; 168 ib_attr->max_res_rd_atom = 0; 169 ib_attr->max_ee_init_rd_atom = 0; 170 ib_attr->max_ee = 0; 171 ib_attr->max_rdd = 0; 172 ib_attr->max_mw = dev_attr->max_mw; 173 ib_attr->max_raw_ipv6_qp = 0; 174 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 175 ib_attr->max_mcast_grp = 0; 176 ib_attr->max_mcast_qp_attach = 0; 177 ib_attr->max_total_mcast_qp_attach = 0; 178 ib_attr->max_ah = dev_attr->max_ah; 179 180 ib_attr->max_srq = dev_attr->max_srq; 181 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 182 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 183 184 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 185 186 ib_attr->max_pkeys = 1; 187 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 188 return 0; 189} 190 191/* Port */ 192int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 193 struct ib_port_attr *port_attr) 194{ 195 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 196 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 197 198 memset(port_attr, 0, sizeof(*port_attr)); 199 200 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 201 port_attr->state = IB_PORT_ACTIVE; 202 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 203 } else { 204 port_attr->state = IB_PORT_DOWN; 205 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 206 } 207 port_attr->max_mtu = IB_MTU_4096; 208 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 209 port_attr->gid_tbl_len = dev_attr->max_sgid; 210 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 211 IB_PORT_DEVICE_MGMT_SUP | 212 IB_PORT_VENDOR_CLASS_SUP; 213 port_attr->ip_gids = true; 214 215 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 216 port_attr->bad_pkey_cntr = 0; 217 port_attr->qkey_viol_cntr = 0; 218 port_attr->pkey_tbl_len = dev_attr->max_pkey; 219 port_attr->lid = 0; 220 port_attr->sm_lid = 0; 221 port_attr->lmc = 0; 222 port_attr->max_vl_num = 4; 223 port_attr->sm_sl = 0; 224 port_attr->subnet_timeout = 0; 225 port_attr->init_type_reply = 0; 226 port_attr->active_speed = rdev->active_speed; 227 port_attr->active_width = rdev->active_width; 228 229 return 0; 230} 231 232int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 233 struct ib_port_immutable *immutable) 234{ 235 struct ib_port_attr port_attr; 236 237 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 238 return -EINVAL; 239 240 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 241 immutable->gid_tbl_len = port_attr.gid_tbl_len; 242 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 243 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 244 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 245 return 0; 246} 247 248void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 249{ 250 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 251 252 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 253 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 254 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 255} 256 257int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 258 u16 index, u16 *pkey) 259{ 260 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 261 262 /* Ignore port_num */ 263 264 memset(pkey, 0, sizeof(*pkey)); 265 return bnxt_qplib_get_pkey(&rdev->qplib_res, 266 &rdev->qplib_res.pkey_tbl, index, pkey); 267} 268 269int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 270 int index, union ib_gid *gid) 271{ 272 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 273 int rc = 0; 274 275 /* Ignore port_num */ 276 memset(gid, 0, sizeof(*gid)); 277 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 278 &rdev->qplib_res.sgid_tbl, index, 279 (struct bnxt_qplib_gid *)gid); 280 return rc; 281} 282 283int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 284{ 285 int rc = 0; 286 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 287 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 288 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 289 struct bnxt_qplib_gid *gid_to_del; 290 u16 vlan_id = 0xFFFF; 291 292 /* Delete the entry from the hardware */ 293 ctx = *context; 294 if (!ctx) 295 return -EINVAL; 296 297 if (sgid_tbl && sgid_tbl->active) { 298 if (ctx->idx >= sgid_tbl->max) 299 return -EINVAL; 300 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 301 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 302 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 303 * or via the ib_unregister_device path. In the former case QP1 304 * may not be destroyed yet, in which case just return as FW 305 * needs that entry to be present and will fail it's deletion. 306 * We could get invoked again after QP1 is destroyed OR get an 307 * ADD_GID call with a different GID value for the same index 308 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 309 */ 310 if (ctx->idx == 0 && 311 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 312 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 313 ibdev_dbg(&rdev->ibdev, 314 "Trying to delete GID0 while QP1 is alive\n"); 315 return -EFAULT; 316 } 317 ctx->refcnt--; 318 if (!ctx->refcnt) { 319 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 320 vlan_id, true); 321 if (rc) { 322 ibdev_err(&rdev->ibdev, 323 "Failed to remove GID: %#x", rc); 324 } else { 325 ctx_tbl = sgid_tbl->ctx; 326 ctx_tbl[ctx->idx] = NULL; 327 kfree(ctx); 328 } 329 } 330 } else { 331 return -EINVAL; 332 } 333 return rc; 334} 335 336int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 337{ 338 int rc; 339 u32 tbl_idx = 0; 340 u16 vlan_id = 0xFFFF; 341 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 342 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 343 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 344 345 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 346 if (rc) 347 return rc; 348 349 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 350 rdev->qplib_res.netdev->dev_addr, 351 vlan_id, true, &tbl_idx); 352 if (rc == -EALREADY) { 353 ctx_tbl = sgid_tbl->ctx; 354 ctx_tbl[tbl_idx]->refcnt++; 355 *context = ctx_tbl[tbl_idx]; 356 return 0; 357 } 358 359 if (rc < 0) { 360 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 361 return rc; 362 } 363 364 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 365 if (!ctx) 366 return -ENOMEM; 367 ctx_tbl = sgid_tbl->ctx; 368 ctx->idx = tbl_idx; 369 ctx->refcnt = 1; 370 ctx_tbl[tbl_idx] = ctx; 371 *context = ctx; 372 373 return rc; 374} 375 376enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 377 u8 port_num) 378{ 379 return IB_LINK_LAYER_ETHERNET; 380} 381 382#define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 383 384static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 385{ 386 struct bnxt_re_fence_data *fence = &pd->fence; 387 struct ib_mr *ib_mr = &fence->mr->ib_mr; 388 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 389 390 memset(wqe, 0, sizeof(*wqe)); 391 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 392 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 393 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 394 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 395 wqe->bind.zero_based = false; 396 wqe->bind.parent_l_key = ib_mr->lkey; 397 wqe->bind.va = (u64)(unsigned long)fence->va; 398 wqe->bind.length = fence->size; 399 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 400 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 401 402 /* Save the initial rkey in fence structure for now; 403 * wqe->bind.r_key will be set at (re)bind time. 404 */ 405 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 406} 407 408static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 409{ 410 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 411 qplib_qp); 412 struct ib_pd *ib_pd = qp->ib_qp.pd; 413 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 414 struct bnxt_re_fence_data *fence = &pd->fence; 415 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 416 struct bnxt_qplib_swqe wqe; 417 int rc; 418 419 memcpy(&wqe, fence_wqe, sizeof(wqe)); 420 wqe.bind.r_key = fence->bind_rkey; 421 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 422 423 ibdev_dbg(&qp->rdev->ibdev, 424 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 425 wqe.bind.r_key, qp->qplib_qp.id, pd); 426 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 427 if (rc) { 428 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 429 return rc; 430 } 431 bnxt_qplib_post_send_db(&qp->qplib_qp); 432 433 return rc; 434} 435 436static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 437{ 438 struct bnxt_re_fence_data *fence = &pd->fence; 439 struct bnxt_re_dev *rdev = pd->rdev; 440 struct device *dev = &rdev->en_dev->pdev->dev; 441 struct bnxt_re_mr *mr = fence->mr; 442 443 if (fence->mw) { 444 bnxt_re_dealloc_mw(fence->mw); 445 fence->mw = NULL; 446 } 447 if (mr) { 448 if (mr->ib_mr.rkey) 449 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 450 true); 451 if (mr->ib_mr.lkey) 452 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 453 kfree(mr); 454 fence->mr = NULL; 455 } 456 if (fence->dma_addr) { 457 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 458 DMA_BIDIRECTIONAL); 459 fence->dma_addr = 0; 460 } 461} 462 463static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 464{ 465 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 466 struct bnxt_re_fence_data *fence = &pd->fence; 467 struct bnxt_re_dev *rdev = pd->rdev; 468 struct device *dev = &rdev->en_dev->pdev->dev; 469 struct bnxt_re_mr *mr = NULL; 470 dma_addr_t dma_addr = 0; 471 struct ib_mw *mw; 472 int rc; 473 474 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 475 DMA_BIDIRECTIONAL); 476 rc = dma_mapping_error(dev, dma_addr); 477 if (rc) { 478 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 479 rc = -EIO; 480 fence->dma_addr = 0; 481 goto fail; 482 } 483 fence->dma_addr = dma_addr; 484 485 /* Allocate a MR */ 486 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 487 if (!mr) { 488 rc = -ENOMEM; 489 goto fail; 490 } 491 fence->mr = mr; 492 mr->rdev = rdev; 493 mr->qplib_mr.pd = &pd->qplib_pd; 494 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 495 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 496 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 497 if (rc) { 498 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 499 goto fail; 500 } 501 502 /* Register MR */ 503 mr->ib_mr.lkey = mr->qplib_mr.lkey; 504 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 505 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 506 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 507 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 508 if (rc) { 509 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 510 goto fail; 511 } 512 mr->ib_mr.rkey = mr->qplib_mr.rkey; 513 514 /* Create a fence MW only for kernel consumers */ 515 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 516 if (IS_ERR(mw)) { 517 ibdev_err(&rdev->ibdev, 518 "Failed to create fence-MW for PD: %p\n", pd); 519 rc = PTR_ERR(mw); 520 goto fail; 521 } 522 fence->mw = mw; 523 524 bnxt_re_create_fence_wqe(pd); 525 return 0; 526 527fail: 528 bnxt_re_destroy_fence_mr(pd); 529 return rc; 530} 531 532/* Protection Domains */ 533int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 534{ 535 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 536 struct bnxt_re_dev *rdev = pd->rdev; 537 538 bnxt_re_destroy_fence_mr(pd); 539 540 if (pd->qplib_pd.id) 541 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 542 &pd->qplib_pd); 543 return 0; 544} 545 546int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 547{ 548 struct ib_device *ibdev = ibpd->device; 549 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 550 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 551 udata, struct bnxt_re_ucontext, ib_uctx); 552 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 553 int rc; 554 555 pd->rdev = rdev; 556 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 557 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 558 rc = -ENOMEM; 559 goto fail; 560 } 561 562 if (udata) { 563 struct bnxt_re_pd_resp resp; 564 565 if (!ucntx->dpi.dbr) { 566 /* Allocate DPI in alloc_pd to avoid failing of 567 * ibv_devinfo and family of application when DPIs 568 * are depleted. 569 */ 570 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 571 &ucntx->dpi, ucntx)) { 572 rc = -ENOMEM; 573 goto dbfail; 574 } 575 } 576 577 resp.pdid = pd->qplib_pd.id; 578 /* Still allow mapping this DBR to the new user PD. */ 579 resp.dpi = ucntx->dpi.dpi; 580 resp.dbr = (u64)ucntx->dpi.umdbr; 581 582 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 583 if (rc) { 584 ibdev_err(&rdev->ibdev, 585 "Failed to copy user response\n"); 586 goto dbfail; 587 } 588 } 589 590 if (!udata) 591 if (bnxt_re_create_fence_mr(pd)) 592 ibdev_warn(&rdev->ibdev, 593 "Failed to create Fence-MR\n"); 594 return 0; 595dbfail: 596 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 597 &pd->qplib_pd); 598fail: 599 return rc; 600} 601 602/* Address Handles */ 603int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 604{ 605 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 606 struct bnxt_re_dev *rdev = ah->rdev; 607 608 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, 609 !(flags & RDMA_DESTROY_AH_SLEEPABLE)); 610 return 0; 611} 612 613static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 614{ 615 u8 nw_type; 616 617 switch (ntype) { 618 case RDMA_NETWORK_IPV4: 619 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 620 break; 621 case RDMA_NETWORK_IPV6: 622 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 623 break; 624 default: 625 nw_type = CMDQ_CREATE_AH_TYPE_V1; 626 break; 627 } 628 return nw_type; 629} 630 631int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 632 struct ib_udata *udata) 633{ 634 struct ib_pd *ib_pd = ib_ah->pd; 635 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 636 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 637 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 638 struct bnxt_re_dev *rdev = pd->rdev; 639 const struct ib_gid_attr *sgid_attr; 640 struct bnxt_re_gid_ctx *ctx; 641 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 642 u8 nw_type; 643 int rc; 644 645 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 646 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 647 return -EINVAL; 648 } 649 650 ah->rdev = rdev; 651 ah->qplib_ah.pd = &pd->qplib_pd; 652 653 /* Supply the configuration for the HW */ 654 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 655 sizeof(union ib_gid)); 656 sgid_attr = grh->sgid_attr; 657 /* Get the HW context of the GID. The reference 658 * of GID table entry is already taken by the caller. 659 */ 660 ctx = rdma_read_gid_hw_context(sgid_attr); 661 ah->qplib_ah.sgid_index = ctx->idx; 662 ah->qplib_ah.host_sgid_index = grh->sgid_index; 663 ah->qplib_ah.traffic_class = grh->traffic_class; 664 ah->qplib_ah.flow_label = grh->flow_label; 665 ah->qplib_ah.hop_limit = grh->hop_limit; 666 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 667 668 /* Get network header type for this GID */ 669 nw_type = rdma_gid_attr_network_type(sgid_attr); 670 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 671 672 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 673 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 674 !(init_attr->flags & 675 RDMA_CREATE_AH_SLEEPABLE)); 676 if (rc) { 677 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 678 return rc; 679 } 680 681 /* Write AVID to shared page. */ 682 if (udata) { 683 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 684 udata, struct bnxt_re_ucontext, ib_uctx); 685 unsigned long flag; 686 u32 *wrptr; 687 688 spin_lock_irqsave(&uctx->sh_lock, flag); 689 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 690 *wrptr = ah->qplib_ah.id; 691 wmb(); /* make sure cache is updated. */ 692 spin_unlock_irqrestore(&uctx->sh_lock, flag); 693 } 694 695 return 0; 696} 697 698int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 699{ 700 return 0; 701} 702 703int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 704{ 705 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 706 707 ah_attr->type = ib_ah->type; 708 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 709 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 710 rdma_ah_set_grh(ah_attr, NULL, 0, 711 ah->qplib_ah.host_sgid_index, 712 0, ah->qplib_ah.traffic_class); 713 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 714 rdma_ah_set_port_num(ah_attr, 1); 715 rdma_ah_set_static_rate(ah_attr, 0); 716 return 0; 717} 718 719unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 720 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 721{ 722 unsigned long flags; 723 724 spin_lock_irqsave(&qp->scq->cq_lock, flags); 725 if (qp->rcq != qp->scq) 726 spin_lock(&qp->rcq->cq_lock); 727 else 728 __acquire(&qp->rcq->cq_lock); 729 730 return flags; 731} 732 733void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 734 unsigned long flags) 735 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 736{ 737 if (qp->rcq != qp->scq) 738 spin_unlock(&qp->rcq->cq_lock); 739 else 740 __release(&qp->rcq->cq_lock); 741 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 742} 743 744static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 745{ 746 struct bnxt_re_qp *gsi_sqp; 747 struct bnxt_re_ah *gsi_sah; 748 struct bnxt_re_dev *rdev; 749 int rc = 0; 750 751 rdev = qp->rdev; 752 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 753 gsi_sah = rdev->gsi_ctx.gsi_sah; 754 755 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 756 bnxt_qplib_destroy_ah(&rdev->qplib_res, 757 &gsi_sah->qplib_ah, 758 true); 759 bnxt_qplib_clean_qp(&qp->qplib_qp); 760 761 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 762 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 763 if (rc) { 764 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 765 goto fail; 766 } 767 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 768 769 /* remove from active qp list */ 770 mutex_lock(&rdev->qp_lock); 771 list_del(&gsi_sqp->list); 772 mutex_unlock(&rdev->qp_lock); 773 atomic_dec(&rdev->qp_count); 774 775 kfree(rdev->gsi_ctx.sqp_tbl); 776 kfree(gsi_sah); 777 kfree(gsi_sqp); 778 rdev->gsi_ctx.gsi_sqp = NULL; 779 rdev->gsi_ctx.gsi_sah = NULL; 780 rdev->gsi_ctx.sqp_tbl = NULL; 781 782 return 0; 783fail: 784 return rc; 785} 786 787/* Queue Pairs */ 788int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 789{ 790 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 791 struct bnxt_re_dev *rdev = qp->rdev; 792 unsigned int flags; 793 int rc; 794 795 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 796 797 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 798 if (rc) { 799 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 800 return rc; 801 } 802 803 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 804 flags = bnxt_re_lock_cqs(qp); 805 bnxt_qplib_clean_qp(&qp->qplib_qp); 806 bnxt_re_unlock_cqs(qp, flags); 807 } 808 809 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 810 811 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 812 rc = bnxt_re_destroy_gsi_sqp(qp); 813 if (rc) 814 goto sh_fail; 815 } 816 817 mutex_lock(&rdev->qp_lock); 818 list_del(&qp->list); 819 mutex_unlock(&rdev->qp_lock); 820 atomic_dec(&rdev->qp_count); 821 822 ib_umem_release(qp->rumem); 823 ib_umem_release(qp->sumem); 824 825 kfree(qp); 826 return 0; 827sh_fail: 828 return rc; 829} 830 831static u8 __from_ib_qp_type(enum ib_qp_type type) 832{ 833 switch (type) { 834 case IB_QPT_GSI: 835 return CMDQ_CREATE_QP1_TYPE_GSI; 836 case IB_QPT_RC: 837 return CMDQ_CREATE_QP_TYPE_RC; 838 case IB_QPT_UD: 839 return CMDQ_CREATE_QP_TYPE_UD; 840 default: 841 return IB_QPT_MAX; 842 } 843} 844 845static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 846 int rsge, int max) 847{ 848 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 849 rsge = max; 850 return bnxt_re_get_rwqe_size(rsge); 851} 852 853static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 854{ 855 u16 wqe_size, calc_ils; 856 857 wqe_size = bnxt_re_get_swqe_size(nsge); 858 if (ilsize) { 859 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 860 wqe_size = max_t(u16, calc_ils, wqe_size); 861 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 862 } 863 return wqe_size; 864} 865 866static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 867 struct ib_qp_init_attr *init_attr) 868{ 869 struct bnxt_qplib_dev_attr *dev_attr; 870 struct bnxt_qplib_qp *qplqp; 871 struct bnxt_re_dev *rdev; 872 struct bnxt_qplib_q *sq; 873 int align, ilsize; 874 875 rdev = qp->rdev; 876 qplqp = &qp->qplib_qp; 877 sq = &qplqp->sq; 878 dev_attr = &rdev->dev_attr; 879 880 align = sizeof(struct sq_send_hdr); 881 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 882 883 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 884 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 885 return -EINVAL; 886 /* For gen p4 and gen p5 backward compatibility mode 887 * wqe size is fixed to 128 bytes 888 */ 889 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) && 890 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 891 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges); 892 893 if (init_attr->cap.max_inline_data) { 894 qplqp->max_inline_data = sq->wqe_size - 895 sizeof(struct sq_send_hdr); 896 init_attr->cap.max_inline_data = qplqp->max_inline_data; 897 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 898 sq->max_sge = qplqp->max_inline_data / 899 sizeof(struct sq_sge); 900 } 901 902 return 0; 903} 904 905static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 906 struct bnxt_re_qp *qp, struct ib_udata *udata) 907{ 908 struct bnxt_qplib_qp *qplib_qp; 909 struct bnxt_re_ucontext *cntx; 910 struct bnxt_re_qp_req ureq; 911 int bytes = 0, psn_sz; 912 struct ib_umem *umem; 913 int psn_nume; 914 915 qplib_qp = &qp->qplib_qp; 916 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, 917 ib_uctx); 918 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 919 return -EFAULT; 920 921 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 922 /* Consider mapping PSN search memory only for RC QPs. */ 923 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 924 psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ? 925 sizeof(struct sq_psn_search_ext) : 926 sizeof(struct sq_psn_search); 927 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 928 qplib_qp->sq.max_wqe : 929 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 930 sizeof(struct bnxt_qplib_sge)); 931 bytes += (psn_nume * psn_sz); 932 } 933 934 bytes = PAGE_ALIGN(bytes); 935 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes, 936 IB_ACCESS_LOCAL_WRITE); 937 if (IS_ERR(umem)) 938 return PTR_ERR(umem); 939 940 qp->sumem = umem; 941 qplib_qp->sq.sg_info.umem = umem; 942 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 943 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 944 qplib_qp->qp_handle = ureq.qp_handle; 945 946 if (!qp->qplib_qp.srq) { 947 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 948 bytes = PAGE_ALIGN(bytes); 949 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes, 950 IB_ACCESS_LOCAL_WRITE); 951 if (IS_ERR(umem)) 952 goto rqfail; 953 qp->rumem = umem; 954 qplib_qp->rq.sg_info.umem = umem; 955 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 956 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 957 } 958 959 qplib_qp->dpi = &cntx->dpi; 960 return 0; 961rqfail: 962 ib_umem_release(qp->sumem); 963 qp->sumem = NULL; 964 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 965 966 return PTR_ERR(umem); 967} 968 969static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 970 (struct bnxt_re_pd *pd, 971 struct bnxt_qplib_res *qp1_res, 972 struct bnxt_qplib_qp *qp1_qp) 973{ 974 struct bnxt_re_dev *rdev = pd->rdev; 975 struct bnxt_re_ah *ah; 976 union ib_gid sgid; 977 int rc; 978 979 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 980 if (!ah) 981 return NULL; 982 983 ah->rdev = rdev; 984 ah->qplib_ah.pd = &pd->qplib_pd; 985 986 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 987 if (rc) 988 goto fail; 989 990 /* supply the dgid data same as sgid */ 991 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 992 sizeof(union ib_gid)); 993 ah->qplib_ah.sgid_index = 0; 994 995 ah->qplib_ah.traffic_class = 0; 996 ah->qplib_ah.flow_label = 0; 997 ah->qplib_ah.hop_limit = 1; 998 ah->qplib_ah.sl = 0; 999 /* Have DMAC same as SMAC */ 1000 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1001 1002 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1003 if (rc) { 1004 ibdev_err(&rdev->ibdev, 1005 "Failed to allocate HW AH for Shadow QP"); 1006 goto fail; 1007 } 1008 1009 return ah; 1010 1011fail: 1012 kfree(ah); 1013 return NULL; 1014} 1015 1016static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1017 (struct bnxt_re_pd *pd, 1018 struct bnxt_qplib_res *qp1_res, 1019 struct bnxt_qplib_qp *qp1_qp) 1020{ 1021 struct bnxt_re_dev *rdev = pd->rdev; 1022 struct bnxt_re_qp *qp; 1023 int rc; 1024 1025 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1026 if (!qp) 1027 return NULL; 1028 1029 qp->rdev = rdev; 1030 1031 /* Initialize the shadow QP structure from the QP1 values */ 1032 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1033 1034 qp->qplib_qp.pd = &pd->qplib_pd; 1035 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1036 qp->qplib_qp.type = IB_QPT_UD; 1037 1038 qp->qplib_qp.max_inline_data = 0; 1039 qp->qplib_qp.sig_type = true; 1040 1041 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1042 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1043 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1044 qp->qplib_qp.sq.max_sge = 2; 1045 /* Q full delta can be 1 since it is internal QP */ 1046 qp->qplib_qp.sq.q_full_delta = 1; 1047 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1048 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1049 1050 qp->qplib_qp.scq = qp1_qp->scq; 1051 qp->qplib_qp.rcq = qp1_qp->rcq; 1052 1053 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1054 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1055 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1056 /* Q full delta can be 1 since it is internal QP */ 1057 qp->qplib_qp.rq.q_full_delta = 1; 1058 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1059 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1060 1061 qp->qplib_qp.mtu = qp1_qp->mtu; 1062 1063 qp->qplib_qp.sq_hdr_buf_size = 0; 1064 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1065 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1066 1067 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1068 if (rc) 1069 goto fail; 1070 1071 spin_lock_init(&qp->sq_lock); 1072 INIT_LIST_HEAD(&qp->list); 1073 mutex_lock(&rdev->qp_lock); 1074 list_add_tail(&qp->list, &rdev->qp_list); 1075 atomic_inc(&rdev->qp_count); 1076 mutex_unlock(&rdev->qp_lock); 1077 return qp; 1078fail: 1079 kfree(qp); 1080 return NULL; 1081} 1082 1083static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1084 struct ib_qp_init_attr *init_attr) 1085{ 1086 struct bnxt_qplib_dev_attr *dev_attr; 1087 struct bnxt_qplib_qp *qplqp; 1088 struct bnxt_re_dev *rdev; 1089 struct bnxt_qplib_q *rq; 1090 int entries; 1091 1092 rdev = qp->rdev; 1093 qplqp = &qp->qplib_qp; 1094 rq = &qplqp->rq; 1095 dev_attr = &rdev->dev_attr; 1096 1097 if (init_attr->srq) { 1098 struct bnxt_re_srq *srq; 1099 1100 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1101 if (!srq) { 1102 ibdev_err(&rdev->ibdev, "SRQ not found"); 1103 return -EINVAL; 1104 } 1105 qplqp->srq = &srq->qplib_srq; 1106 rq->max_wqe = 0; 1107 } else { 1108 rq->max_sge = init_attr->cap.max_recv_sge; 1109 if (rq->max_sge > dev_attr->max_qp_sges) 1110 rq->max_sge = dev_attr->max_qp_sges; 1111 init_attr->cap.max_recv_sge = rq->max_sge; 1112 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1113 dev_attr->max_qp_sges); 1114 /* Allocate 1 more than what's provided so posting max doesn't 1115 * mean empty. 1116 */ 1117 entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1); 1118 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1119 rq->q_full_delta = 0; 1120 rq->sg_info.pgsize = PAGE_SIZE; 1121 rq->sg_info.pgshft = PAGE_SHIFT; 1122 } 1123 1124 return 0; 1125} 1126 1127static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1128{ 1129 struct bnxt_qplib_dev_attr *dev_attr; 1130 struct bnxt_qplib_qp *qplqp; 1131 struct bnxt_re_dev *rdev; 1132 1133 rdev = qp->rdev; 1134 qplqp = &qp->qplib_qp; 1135 dev_attr = &rdev->dev_attr; 1136 1137 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) { 1138 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1139 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1140 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1141 qplqp->rq.max_sge = 6; 1142 } 1143} 1144 1145static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1146 struct ib_qp_init_attr *init_attr, 1147 struct ib_udata *udata) 1148{ 1149 struct bnxt_qplib_dev_attr *dev_attr; 1150 struct bnxt_qplib_qp *qplqp; 1151 struct bnxt_re_dev *rdev; 1152 struct bnxt_qplib_q *sq; 1153 int entries; 1154 int diff; 1155 int rc; 1156 1157 rdev = qp->rdev; 1158 qplqp = &qp->qplib_qp; 1159 sq = &qplqp->sq; 1160 dev_attr = &rdev->dev_attr; 1161 1162 sq->max_sge = init_attr->cap.max_send_sge; 1163 if (sq->max_sge > dev_attr->max_qp_sges) { 1164 sq->max_sge = dev_attr->max_qp_sges; 1165 init_attr->cap.max_send_sge = sq->max_sge; 1166 } 1167 1168 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1169 if (rc) 1170 return rc; 1171 1172 entries = init_attr->cap.max_send_wr; 1173 /* Allocate 128 + 1 more than what's provided */ 1174 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1175 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1176 entries = roundup_pow_of_two(entries + diff + 1); 1177 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1178 sq->q_full_delta = diff + 1; 1179 /* 1180 * Reserving one slot for Phantom WQE. Application can 1181 * post one extra entry in this case. But allowing this to avoid 1182 * unexpected Queue full condition 1183 */ 1184 qplqp->sq.q_full_delta -= 1; 1185 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1186 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1187 1188 return 0; 1189} 1190 1191static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1192 struct ib_qp_init_attr *init_attr) 1193{ 1194 struct bnxt_qplib_dev_attr *dev_attr; 1195 struct bnxt_qplib_qp *qplqp; 1196 struct bnxt_re_dev *rdev; 1197 int entries; 1198 1199 rdev = qp->rdev; 1200 qplqp = &qp->qplib_qp; 1201 dev_attr = &rdev->dev_attr; 1202 1203 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) { 1204 entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1); 1205 qplqp->sq.max_wqe = min_t(u32, entries, 1206 dev_attr->max_qp_wqes + 1); 1207 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1208 init_attr->cap.max_send_wr; 1209 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1210 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1211 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1212 } 1213} 1214 1215static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1216 struct ib_qp_init_attr *init_attr) 1217{ 1218 struct bnxt_qplib_chip_ctx *chip_ctx; 1219 int qptype; 1220 1221 chip_ctx = rdev->chip_ctx; 1222 1223 qptype = __from_ib_qp_type(init_attr->qp_type); 1224 if (qptype == IB_QPT_MAX) { 1225 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1226 qptype = -EOPNOTSUPP; 1227 goto out; 1228 } 1229 1230 if (bnxt_qplib_is_chip_gen_p5(chip_ctx) && 1231 init_attr->qp_type == IB_QPT_GSI) 1232 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1233out: 1234 return qptype; 1235} 1236 1237static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1238 struct ib_qp_init_attr *init_attr, 1239 struct ib_udata *udata) 1240{ 1241 struct bnxt_qplib_dev_attr *dev_attr; 1242 struct bnxt_qplib_qp *qplqp; 1243 struct bnxt_re_dev *rdev; 1244 struct bnxt_re_cq *cq; 1245 int rc = 0, qptype; 1246 1247 rdev = qp->rdev; 1248 qplqp = &qp->qplib_qp; 1249 dev_attr = &rdev->dev_attr; 1250 1251 /* Setup misc params */ 1252 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1253 qplqp->pd = &pd->qplib_pd; 1254 qplqp->qp_handle = (u64)qplqp; 1255 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1256 qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1257 true : false); 1258 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1259 if (qptype < 0) { 1260 rc = qptype; 1261 goto out; 1262 } 1263 qplqp->type = (u8)qptype; 1264 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode; 1265 1266 if (init_attr->qp_type == IB_QPT_RC) { 1267 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1268 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1269 } 1270 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1271 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1272 if (init_attr->create_flags) 1273 ibdev_dbg(&rdev->ibdev, 1274 "QP create flags 0x%x not supported", 1275 init_attr->create_flags); 1276 1277 /* Setup CQs */ 1278 if (init_attr->send_cq) { 1279 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1280 if (!cq) { 1281 ibdev_err(&rdev->ibdev, "Send CQ not found"); 1282 rc = -EINVAL; 1283 goto out; 1284 } 1285 qplqp->scq = &cq->qplib_cq; 1286 qp->scq = cq; 1287 } 1288 1289 if (init_attr->recv_cq) { 1290 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1291 if (!cq) { 1292 ibdev_err(&rdev->ibdev, "Receive CQ not found"); 1293 rc = -EINVAL; 1294 goto out; 1295 } 1296 qplqp->rcq = &cq->qplib_cq; 1297 qp->rcq = cq; 1298 } 1299 1300 /* Setup RQ/SRQ */ 1301 rc = bnxt_re_init_rq_attr(qp, init_attr); 1302 if (rc) 1303 goto out; 1304 if (init_attr->qp_type == IB_QPT_GSI) 1305 bnxt_re_adjust_gsi_rq_attr(qp); 1306 1307 /* Setup SQ */ 1308 rc = bnxt_re_init_sq_attr(qp, init_attr, udata); 1309 if (rc) 1310 goto out; 1311 if (init_attr->qp_type == IB_QPT_GSI) 1312 bnxt_re_adjust_gsi_sq_attr(qp, init_attr); 1313 1314 if (udata) /* This will update DPI and qp_handle */ 1315 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1316out: 1317 return rc; 1318} 1319 1320static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1321 struct bnxt_re_pd *pd) 1322{ 1323 struct bnxt_re_sqp_entries *sqp_tbl = NULL; 1324 struct bnxt_re_dev *rdev; 1325 struct bnxt_re_qp *sqp; 1326 struct bnxt_re_ah *sah; 1327 int rc = 0; 1328 1329 rdev = qp->rdev; 1330 /* Create a shadow QP to handle the QP1 traffic */ 1331 sqp_tbl = kzalloc(sizeof(*sqp_tbl) * BNXT_RE_MAX_GSI_SQP_ENTRIES, 1332 GFP_KERNEL); 1333 if (!sqp_tbl) 1334 return -ENOMEM; 1335 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1336 1337 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1338 if (!sqp) { 1339 rc = -ENODEV; 1340 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1341 goto out; 1342 } 1343 rdev->gsi_ctx.gsi_sqp = sqp; 1344 1345 sqp->rcq = qp->rcq; 1346 sqp->scq = qp->scq; 1347 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1348 &qp->qplib_qp); 1349 if (!sah) { 1350 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1351 &sqp->qplib_qp); 1352 rc = -ENODEV; 1353 ibdev_err(&rdev->ibdev, 1354 "Failed to create AH entry for ShadowQP"); 1355 goto out; 1356 } 1357 rdev->gsi_ctx.gsi_sah = sah; 1358 1359 return 0; 1360out: 1361 kfree(sqp_tbl); 1362 return rc; 1363} 1364 1365static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1366 struct ib_qp_init_attr *init_attr) 1367{ 1368 struct bnxt_re_dev *rdev; 1369 struct bnxt_qplib_qp *qplqp; 1370 int rc = 0; 1371 1372 rdev = qp->rdev; 1373 qplqp = &qp->qplib_qp; 1374 1375 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1376 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1377 1378 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1379 if (rc) { 1380 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1381 goto out; 1382 } 1383 1384 rc = bnxt_re_create_shadow_gsi(qp, pd); 1385out: 1386 return rc; 1387} 1388 1389static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1390 struct ib_qp_init_attr *init_attr, 1391 struct bnxt_qplib_dev_attr *dev_attr) 1392{ 1393 bool rc = true; 1394 1395 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1396 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1397 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1398 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1399 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1400 ibdev_err(&rdev->ibdev, 1401 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1402 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1403 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1404 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1405 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1406 init_attr->cap.max_inline_data, 1407 dev_attr->max_inline_data); 1408 rc = false; 1409 } 1410 return rc; 1411} 1412 1413struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 1414 struct ib_qp_init_attr *qp_init_attr, 1415 struct ib_udata *udata) 1416{ 1417 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1418 struct bnxt_re_dev *rdev = pd->rdev; 1419 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1420 struct bnxt_re_qp *qp; 1421 int rc; 1422 1423 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1424 if (!rc) { 1425 rc = -EINVAL; 1426 goto exit; 1427 } 1428 1429 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1430 if (!qp) { 1431 rc = -ENOMEM; 1432 goto exit; 1433 } 1434 qp->rdev = rdev; 1435 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata); 1436 if (rc) 1437 goto fail; 1438 1439 if (qp_init_attr->qp_type == IB_QPT_GSI && 1440 !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) { 1441 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1442 if (rc == -ENODEV) 1443 goto qp_destroy; 1444 if (rc) 1445 goto fail; 1446 } else { 1447 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1448 if (rc) { 1449 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1450 goto free_umem; 1451 } 1452 if (udata) { 1453 struct bnxt_re_qp_resp resp; 1454 1455 resp.qpid = qp->qplib_qp.id; 1456 resp.rsvd = 0; 1457 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1458 if (rc) { 1459 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1460 goto qp_destroy; 1461 } 1462 } 1463 } 1464 1465 qp->ib_qp.qp_num = qp->qplib_qp.id; 1466 if (qp_init_attr->qp_type == IB_QPT_GSI) 1467 rdev->gsi_ctx.gsi_qp = qp; 1468 spin_lock_init(&qp->sq_lock); 1469 spin_lock_init(&qp->rq_lock); 1470 INIT_LIST_HEAD(&qp->list); 1471 mutex_lock(&rdev->qp_lock); 1472 list_add_tail(&qp->list, &rdev->qp_list); 1473 mutex_unlock(&rdev->qp_lock); 1474 atomic_inc(&rdev->qp_count); 1475 1476 return &qp->ib_qp; 1477qp_destroy: 1478 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1479free_umem: 1480 ib_umem_release(qp->rumem); 1481 ib_umem_release(qp->sumem); 1482fail: 1483 kfree(qp); 1484exit: 1485 return ERR_PTR(rc); 1486} 1487 1488static u8 __from_ib_qp_state(enum ib_qp_state state) 1489{ 1490 switch (state) { 1491 case IB_QPS_RESET: 1492 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1493 case IB_QPS_INIT: 1494 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1495 case IB_QPS_RTR: 1496 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1497 case IB_QPS_RTS: 1498 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1499 case IB_QPS_SQD: 1500 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1501 case IB_QPS_SQE: 1502 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1503 case IB_QPS_ERR: 1504 default: 1505 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1506 } 1507} 1508 1509static enum ib_qp_state __to_ib_qp_state(u8 state) 1510{ 1511 switch (state) { 1512 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1513 return IB_QPS_RESET; 1514 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1515 return IB_QPS_INIT; 1516 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1517 return IB_QPS_RTR; 1518 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1519 return IB_QPS_RTS; 1520 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1521 return IB_QPS_SQD; 1522 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1523 return IB_QPS_SQE; 1524 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1525 default: 1526 return IB_QPS_ERR; 1527 } 1528} 1529 1530static u32 __from_ib_mtu(enum ib_mtu mtu) 1531{ 1532 switch (mtu) { 1533 case IB_MTU_256: 1534 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1535 case IB_MTU_512: 1536 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1537 case IB_MTU_1024: 1538 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1539 case IB_MTU_2048: 1540 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1541 case IB_MTU_4096: 1542 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1543 default: 1544 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1545 } 1546} 1547 1548static enum ib_mtu __to_ib_mtu(u32 mtu) 1549{ 1550 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1551 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1552 return IB_MTU_256; 1553 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1554 return IB_MTU_512; 1555 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1556 return IB_MTU_1024; 1557 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1558 return IB_MTU_2048; 1559 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1560 return IB_MTU_4096; 1561 default: 1562 return IB_MTU_2048; 1563 } 1564} 1565 1566/* Shared Receive Queues */ 1567int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1568{ 1569 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1570 ib_srq); 1571 struct bnxt_re_dev *rdev = srq->rdev; 1572 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1573 struct bnxt_qplib_nq *nq = NULL; 1574 1575 if (qplib_srq->cq) 1576 nq = qplib_srq->cq->nq; 1577 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1578 ib_umem_release(srq->umem); 1579 atomic_dec(&rdev->srq_count); 1580 if (nq) 1581 nq->budget--; 1582 return 0; 1583} 1584 1585static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1586 struct bnxt_re_pd *pd, 1587 struct bnxt_re_srq *srq, 1588 struct ib_udata *udata) 1589{ 1590 struct bnxt_re_srq_req ureq; 1591 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1592 struct ib_umem *umem; 1593 int bytes = 0; 1594 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1595 udata, struct bnxt_re_ucontext, ib_uctx); 1596 1597 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1598 return -EFAULT; 1599 1600 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1601 bytes = PAGE_ALIGN(bytes); 1602 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1603 IB_ACCESS_LOCAL_WRITE); 1604 if (IS_ERR(umem)) 1605 return PTR_ERR(umem); 1606 1607 srq->umem = umem; 1608 qplib_srq->sg_info.umem = umem; 1609 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1610 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1611 qplib_srq->srq_handle = ureq.srq_handle; 1612 qplib_srq->dpi = &cntx->dpi; 1613 1614 return 0; 1615} 1616 1617int bnxt_re_create_srq(struct ib_srq *ib_srq, 1618 struct ib_srq_init_attr *srq_init_attr, 1619 struct ib_udata *udata) 1620{ 1621 struct bnxt_qplib_dev_attr *dev_attr; 1622 struct bnxt_qplib_nq *nq = NULL; 1623 struct bnxt_re_dev *rdev; 1624 struct bnxt_re_srq *srq; 1625 struct bnxt_re_pd *pd; 1626 struct ib_pd *ib_pd; 1627 int rc, entries; 1628 1629 ib_pd = ib_srq->pd; 1630 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1631 rdev = pd->rdev; 1632 dev_attr = &rdev->dev_attr; 1633 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1634 1635 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1636 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1637 rc = -EINVAL; 1638 goto exit; 1639 } 1640 1641 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1642 rc = -EOPNOTSUPP; 1643 goto exit; 1644 } 1645 1646 srq->rdev = rdev; 1647 srq->qplib_srq.pd = &pd->qplib_pd; 1648 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1649 /* Allocate 1 more than what's provided so posting max doesn't 1650 * mean empty 1651 */ 1652 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1); 1653 if (entries > dev_attr->max_srq_wqes + 1) 1654 entries = dev_attr->max_srq_wqes + 1; 1655 srq->qplib_srq.max_wqe = entries; 1656 1657 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1658 /* 128 byte wqe size for SRQ . So use max sges */ 1659 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1660 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1661 srq->srq_limit = srq_init_attr->attr.srq_limit; 1662 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1663 nq = &rdev->nq[0]; 1664 1665 if (udata) { 1666 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1667 if (rc) 1668 goto fail; 1669 } 1670 1671 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1672 if (rc) { 1673 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1674 goto fail; 1675 } 1676 1677 if (udata) { 1678 struct bnxt_re_srq_resp resp; 1679 1680 resp.srqid = srq->qplib_srq.id; 1681 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1682 if (rc) { 1683 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1684 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1685 &srq->qplib_srq); 1686 goto fail; 1687 } 1688 } 1689 if (nq) 1690 nq->budget++; 1691 atomic_inc(&rdev->srq_count); 1692 spin_lock_init(&srq->lock); 1693 1694 return 0; 1695 1696fail: 1697 ib_umem_release(srq->umem); 1698exit: 1699 return rc; 1700} 1701 1702int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1703 enum ib_srq_attr_mask srq_attr_mask, 1704 struct ib_udata *udata) 1705{ 1706 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1707 ib_srq); 1708 struct bnxt_re_dev *rdev = srq->rdev; 1709 int rc; 1710 1711 switch (srq_attr_mask) { 1712 case IB_SRQ_MAX_WR: 1713 /* SRQ resize is not supported */ 1714 break; 1715 case IB_SRQ_LIMIT: 1716 /* Change the SRQ threshold */ 1717 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1718 return -EINVAL; 1719 1720 srq->qplib_srq.threshold = srq_attr->srq_limit; 1721 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1722 if (rc) { 1723 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1724 return rc; 1725 } 1726 /* On success, update the shadow */ 1727 srq->srq_limit = srq_attr->srq_limit; 1728 /* No need to Build and send response back to udata */ 1729 break; 1730 default: 1731 ibdev_err(&rdev->ibdev, 1732 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1733 return -EINVAL; 1734 } 1735 return 0; 1736} 1737 1738int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1739{ 1740 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1741 ib_srq); 1742 struct bnxt_re_srq tsrq; 1743 struct bnxt_re_dev *rdev = srq->rdev; 1744 int rc; 1745 1746 /* Get live SRQ attr */ 1747 tsrq.qplib_srq.id = srq->qplib_srq.id; 1748 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1749 if (rc) { 1750 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1751 return rc; 1752 } 1753 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1754 srq_attr->max_sge = srq->qplib_srq.max_sge; 1755 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1756 1757 return 0; 1758} 1759 1760int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1761 const struct ib_recv_wr **bad_wr) 1762{ 1763 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1764 ib_srq); 1765 struct bnxt_qplib_swqe wqe; 1766 unsigned long flags; 1767 int rc = 0; 1768 1769 spin_lock_irqsave(&srq->lock, flags); 1770 while (wr) { 1771 /* Transcribe each ib_recv_wr to qplib_swqe */ 1772 wqe.num_sge = wr->num_sge; 1773 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1774 wqe.wr_id = wr->wr_id; 1775 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1776 1777 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1778 if (rc) { 1779 *bad_wr = wr; 1780 break; 1781 } 1782 wr = wr->next; 1783 } 1784 spin_unlock_irqrestore(&srq->lock, flags); 1785 1786 return rc; 1787} 1788static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1789 struct bnxt_re_qp *qp1_qp, 1790 int qp_attr_mask) 1791{ 1792 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 1793 int rc = 0; 1794 1795 if (qp_attr_mask & IB_QP_STATE) { 1796 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1797 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1798 } 1799 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1800 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1801 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1802 } 1803 1804 if (qp_attr_mask & IB_QP_QKEY) { 1805 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1806 /* Using a Random QKEY */ 1807 qp->qplib_qp.qkey = 0x81818181; 1808 } 1809 if (qp_attr_mask & IB_QP_SQ_PSN) { 1810 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1811 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1812 } 1813 1814 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1815 if (rc) 1816 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 1817 return rc; 1818} 1819 1820int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1821 int qp_attr_mask, struct ib_udata *udata) 1822{ 1823 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1824 struct bnxt_re_dev *rdev = qp->rdev; 1825 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1826 enum ib_qp_state curr_qp_state, new_qp_state; 1827 int rc, entries; 1828 unsigned int flags; 1829 u8 nw_type; 1830 1831 qp->qplib_qp.modify_flags = 0; 1832 if (qp_attr_mask & IB_QP_STATE) { 1833 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1834 new_qp_state = qp_attr->qp_state; 1835 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1836 ib_qp->qp_type, qp_attr_mask)) { 1837 ibdev_err(&rdev->ibdev, 1838 "Invalid attribute mask: %#x specified ", 1839 qp_attr_mask); 1840 ibdev_err(&rdev->ibdev, 1841 "for qpn: %#x type: %#x", 1842 ib_qp->qp_num, ib_qp->qp_type); 1843 ibdev_err(&rdev->ibdev, 1844 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1845 curr_qp_state, new_qp_state); 1846 return -EINVAL; 1847 } 1848 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1849 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1850 1851 if (!qp->sumem && 1852 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1853 ibdev_dbg(&rdev->ibdev, 1854 "Move QP = %p to flush list\n", qp); 1855 flags = bnxt_re_lock_cqs(qp); 1856 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1857 bnxt_re_unlock_cqs(qp, flags); 1858 } 1859 if (!qp->sumem && 1860 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1861 ibdev_dbg(&rdev->ibdev, 1862 "Move QP = %p out of flush list\n", qp); 1863 flags = bnxt_re_lock_cqs(qp); 1864 bnxt_qplib_clean_qp(&qp->qplib_qp); 1865 bnxt_re_unlock_cqs(qp, flags); 1866 } 1867 } 1868 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1869 qp->qplib_qp.modify_flags |= 1870 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1871 qp->qplib_qp.en_sqd_async_notify = true; 1872 } 1873 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1874 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1875 qp->qplib_qp.access = 1876 __from_ib_access_flags(qp_attr->qp_access_flags); 1877 /* LOCAL_WRITE access must be set to allow RC receive */ 1878 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1879 /* Temp: Set all params on QP as of now */ 1880 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 1881 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 1882 } 1883 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1884 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1885 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1886 } 1887 if (qp_attr_mask & IB_QP_QKEY) { 1888 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1889 qp->qplib_qp.qkey = qp_attr->qkey; 1890 } 1891 if (qp_attr_mask & IB_QP_AV) { 1892 const struct ib_global_route *grh = 1893 rdma_ah_read_grh(&qp_attr->ah_attr); 1894 const struct ib_gid_attr *sgid_attr; 1895 struct bnxt_re_gid_ctx *ctx; 1896 1897 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1898 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1899 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1900 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1901 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1902 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1903 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1904 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1905 sizeof(qp->qplib_qp.ah.dgid.data)); 1906 qp->qplib_qp.ah.flow_label = grh->flow_label; 1907 sgid_attr = grh->sgid_attr; 1908 /* Get the HW context of the GID. The reference 1909 * of GID table entry is already taken by the caller. 1910 */ 1911 ctx = rdma_read_gid_hw_context(sgid_attr); 1912 qp->qplib_qp.ah.sgid_index = ctx->idx; 1913 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1914 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1915 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1916 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1917 ether_addr_copy(qp->qplib_qp.ah.dmac, 1918 qp_attr->ah_attr.roce.dmac); 1919 1920 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 1921 &qp->qplib_qp.smac[0]); 1922 if (rc) 1923 return rc; 1924 1925 nw_type = rdma_gid_attr_network_type(sgid_attr); 1926 switch (nw_type) { 1927 case RDMA_NETWORK_IPV4: 1928 qp->qplib_qp.nw_type = 1929 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1930 break; 1931 case RDMA_NETWORK_IPV6: 1932 qp->qplib_qp.nw_type = 1933 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1934 break; 1935 default: 1936 qp->qplib_qp.nw_type = 1937 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1938 break; 1939 } 1940 } 1941 1942 if (qp_attr_mask & IB_QP_PATH_MTU) { 1943 qp->qplib_qp.modify_flags |= 1944 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1945 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1946 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 1947 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1948 qp->qplib_qp.modify_flags |= 1949 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1950 qp->qplib_qp.path_mtu = 1951 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1952 qp->qplib_qp.mtu = 1953 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1954 } 1955 1956 if (qp_attr_mask & IB_QP_TIMEOUT) { 1957 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1958 qp->qplib_qp.timeout = qp_attr->timeout; 1959 } 1960 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1961 qp->qplib_qp.modify_flags |= 1962 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1963 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1964 } 1965 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1966 qp->qplib_qp.modify_flags |= 1967 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1968 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1969 } 1970 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1971 qp->qplib_qp.modify_flags |= 1972 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1973 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1974 } 1975 if (qp_attr_mask & IB_QP_RQ_PSN) { 1976 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1977 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1978 } 1979 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1980 qp->qplib_qp.modify_flags |= 1981 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1982 /* Cap the max_rd_atomic to device max */ 1983 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1984 dev_attr->max_qp_rd_atom); 1985 } 1986 if (qp_attr_mask & IB_QP_SQ_PSN) { 1987 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1988 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1989 } 1990 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1991 if (qp_attr->max_dest_rd_atomic > 1992 dev_attr->max_qp_init_rd_atom) { 1993 ibdev_err(&rdev->ibdev, 1994 "max_dest_rd_atomic requested%d is > dev_max%d", 1995 qp_attr->max_dest_rd_atomic, 1996 dev_attr->max_qp_init_rd_atom); 1997 return -EINVAL; 1998 } 1999 2000 qp->qplib_qp.modify_flags |= 2001 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2002 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2003 } 2004 if (qp_attr_mask & IB_QP_CAP) { 2005 qp->qplib_qp.modify_flags |= 2006 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2007 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2008 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2009 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2010 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2011 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2012 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2013 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2014 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2015 (qp_attr->cap.max_inline_data >= 2016 dev_attr->max_inline_data)) { 2017 ibdev_err(&rdev->ibdev, 2018 "Create QP failed - max exceeded"); 2019 return -EINVAL; 2020 } 2021 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 2022 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2023 dev_attr->max_qp_wqes + 1); 2024 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2025 qp_attr->cap.max_send_wr; 2026 /* 2027 * Reserving one slot for Phantom WQE. Some application can 2028 * post one extra entry in this case. Allowing this to avoid 2029 * unexpected Queue full condition 2030 */ 2031 qp->qplib_qp.sq.q_full_delta -= 1; 2032 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2033 if (qp->qplib_qp.rq.max_wqe) { 2034 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 2035 qp->qplib_qp.rq.max_wqe = 2036 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2037 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2038 qp_attr->cap.max_recv_wr; 2039 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2040 } else { 2041 /* SRQ was used prior, just ignore the RQ caps */ 2042 } 2043 } 2044 if (qp_attr_mask & IB_QP_DEST_QPN) { 2045 qp->qplib_qp.modify_flags |= 2046 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2047 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2048 } 2049 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2050 if (rc) { 2051 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2052 return rc; 2053 } 2054 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2055 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2056 return rc; 2057} 2058 2059int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2060 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2061{ 2062 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2063 struct bnxt_re_dev *rdev = qp->rdev; 2064 struct bnxt_qplib_qp *qplib_qp; 2065 int rc; 2066 2067 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2068 if (!qplib_qp) 2069 return -ENOMEM; 2070 2071 qplib_qp->id = qp->qplib_qp.id; 2072 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2073 2074 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2075 if (rc) { 2076 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2077 goto out; 2078 } 2079 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2080 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2081 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2082 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 2083 qp_attr->pkey_index = qplib_qp->pkey_index; 2084 qp_attr->qkey = qplib_qp->qkey; 2085 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2086 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2087 qplib_qp->ah.host_sgid_index, 2088 qplib_qp->ah.hop_limit, 2089 qplib_qp->ah.traffic_class); 2090 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2091 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2092 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2093 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2094 qp_attr->timeout = qplib_qp->timeout; 2095 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2096 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2097 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2098 qp_attr->rq_psn = qplib_qp->rq.psn; 2099 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2100 qp_attr->sq_psn = qplib_qp->sq.psn; 2101 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2102 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2103 IB_SIGNAL_REQ_WR; 2104 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2105 2106 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2107 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2108 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2109 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2110 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2111 qp_init_attr->cap = qp_attr->cap; 2112 2113out: 2114 kfree(qplib_qp); 2115 return rc; 2116} 2117 2118/* Routine for sending QP1 packets for RoCE V1 an V2 2119 */ 2120static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2121 const struct ib_send_wr *wr, 2122 struct bnxt_qplib_swqe *wqe, 2123 int payload_size) 2124{ 2125 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2126 ib_ah); 2127 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2128 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2129 struct bnxt_qplib_sge sge; 2130 u8 nw_type; 2131 u16 ether_type; 2132 union ib_gid dgid; 2133 bool is_eth = false; 2134 bool is_vlan = false; 2135 bool is_grh = false; 2136 bool is_udp = false; 2137 u8 ip_version = 0; 2138 u16 vlan_id = 0xFFFF; 2139 void *buf; 2140 int i, rc = 0; 2141 2142 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2143 2144 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2145 if (rc) 2146 return rc; 2147 2148 /* Get network header type for this GID */ 2149 nw_type = rdma_gid_attr_network_type(sgid_attr); 2150 switch (nw_type) { 2151 case RDMA_NETWORK_IPV4: 2152 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2153 break; 2154 case RDMA_NETWORK_IPV6: 2155 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2156 break; 2157 default: 2158 nw_type = BNXT_RE_ROCE_V1_PACKET; 2159 break; 2160 } 2161 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2162 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2163 if (is_udp) { 2164 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2165 ip_version = 4; 2166 ether_type = ETH_P_IP; 2167 } else { 2168 ip_version = 6; 2169 ether_type = ETH_P_IPV6; 2170 } 2171 is_grh = false; 2172 } else { 2173 ether_type = ETH_P_IBOE; 2174 is_grh = true; 2175 } 2176 2177 is_eth = true; 2178 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 2179 2180 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2181 ip_version, is_udp, 0, &qp->qp1_hdr); 2182 2183 /* ETH */ 2184 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2185 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2186 2187 /* For vlan, check the sgid for vlan existence */ 2188 2189 if (!is_vlan) { 2190 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2191 } else { 2192 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2193 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2194 } 2195 2196 if (is_grh || (ip_version == 6)) { 2197 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2198 sizeof(sgid_attr->gid)); 2199 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2200 sizeof(sgid_attr->gid)); 2201 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2202 } 2203 2204 if (ip_version == 4) { 2205 qp->qp1_hdr.ip4.tos = 0; 2206 qp->qp1_hdr.ip4.id = 0; 2207 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2208 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2209 2210 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2211 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2212 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2213 } 2214 2215 if (is_udp) { 2216 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2217 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2218 qp->qp1_hdr.udp.csum = 0; 2219 } 2220 2221 /* BTH */ 2222 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2223 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2224 qp->qp1_hdr.immediate_present = 1; 2225 } else { 2226 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2227 } 2228 if (wr->send_flags & IB_SEND_SOLICITED) 2229 qp->qp1_hdr.bth.solicited_event = 1; 2230 /* pad_count */ 2231 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2232 2233 /* P_key for QP1 is for all members */ 2234 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2235 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2236 qp->qp1_hdr.bth.ack_req = 0; 2237 qp->send_psn++; 2238 qp->send_psn &= BTH_PSN_MASK; 2239 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2240 /* DETH */ 2241 /* Use the priviledged Q_Key for QP1 */ 2242 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2243 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2244 2245 /* Pack the QP1 to the transmit buffer */ 2246 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2247 if (buf) { 2248 ib_ud_header_pack(&qp->qp1_hdr, buf); 2249 for (i = wqe->num_sge; i; i--) { 2250 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2251 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2252 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2253 } 2254 2255 /* 2256 * Max Header buf size for IPV6 RoCE V2 is 86, 2257 * which is same as the QP1 SQ header buffer. 2258 * Header buf size for IPV4 RoCE V2 can be 66. 2259 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2260 * Subtract 20 bytes from QP1 SQ header buf size 2261 */ 2262 if (is_udp && ip_version == 4) 2263 sge.size -= 20; 2264 /* 2265 * Max Header buf size for RoCE V1 is 78. 2266 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2267 * Subtract 8 bytes from QP1 SQ header buf size 2268 */ 2269 if (!is_udp) 2270 sge.size -= 8; 2271 2272 /* Subtract 4 bytes for non vlan packets */ 2273 if (!is_vlan) 2274 sge.size -= 4; 2275 2276 wqe->sg_list[0].addr = sge.addr; 2277 wqe->sg_list[0].lkey = sge.lkey; 2278 wqe->sg_list[0].size = sge.size; 2279 wqe->num_sge++; 2280 2281 } else { 2282 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2283 rc = -ENOMEM; 2284 } 2285 return rc; 2286} 2287 2288/* For the MAD layer, it only provides the recv SGE the size of 2289 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2290 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2291 * receive packet (334 bytes) with no VLAN and then copy the GRH 2292 * and the MAD datagram out to the provided SGE. 2293 */ 2294static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2295 const struct ib_recv_wr *wr, 2296 struct bnxt_qplib_swqe *wqe, 2297 int payload_size) 2298{ 2299 struct bnxt_re_sqp_entries *sqp_entry; 2300 struct bnxt_qplib_sge ref, sge; 2301 struct bnxt_re_dev *rdev; 2302 u32 rq_prod_index; 2303 2304 rdev = qp->rdev; 2305 2306 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2307 2308 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2309 return -ENOMEM; 2310 2311 /* Create 1 SGE to receive the entire 2312 * ethernet packet 2313 */ 2314 /* Save the reference from ULP */ 2315 ref.addr = wqe->sg_list[0].addr; 2316 ref.lkey = wqe->sg_list[0].lkey; 2317 ref.size = wqe->sg_list[0].size; 2318 2319 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2320 2321 /* SGE 1 */ 2322 wqe->sg_list[0].addr = sge.addr; 2323 wqe->sg_list[0].lkey = sge.lkey; 2324 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2325 sge.size -= wqe->sg_list[0].size; 2326 2327 sqp_entry->sge.addr = ref.addr; 2328 sqp_entry->sge.lkey = ref.lkey; 2329 sqp_entry->sge.size = ref.size; 2330 /* Store the wrid for reporting completion */ 2331 sqp_entry->wrid = wqe->wr_id; 2332 /* change the wqe->wrid to table index */ 2333 wqe->wr_id = rq_prod_index; 2334 return 0; 2335} 2336 2337static int is_ud_qp(struct bnxt_re_qp *qp) 2338{ 2339 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2340 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2341} 2342 2343static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2344 const struct ib_send_wr *wr, 2345 struct bnxt_qplib_swqe *wqe) 2346{ 2347 struct bnxt_re_ah *ah = NULL; 2348 2349 if (is_ud_qp(qp)) { 2350 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2351 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2352 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2353 wqe->send.avid = ah->qplib_ah.id; 2354 } 2355 switch (wr->opcode) { 2356 case IB_WR_SEND: 2357 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2358 break; 2359 case IB_WR_SEND_WITH_IMM: 2360 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2361 wqe->send.imm_data = wr->ex.imm_data; 2362 break; 2363 case IB_WR_SEND_WITH_INV: 2364 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2365 wqe->send.inv_key = wr->ex.invalidate_rkey; 2366 break; 2367 default: 2368 return -EINVAL; 2369 } 2370 if (wr->send_flags & IB_SEND_SIGNALED) 2371 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2372 if (wr->send_flags & IB_SEND_FENCE) 2373 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2374 if (wr->send_flags & IB_SEND_SOLICITED) 2375 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2376 if (wr->send_flags & IB_SEND_INLINE) 2377 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2378 2379 return 0; 2380} 2381 2382static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2383 struct bnxt_qplib_swqe *wqe) 2384{ 2385 switch (wr->opcode) { 2386 case IB_WR_RDMA_WRITE: 2387 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2388 break; 2389 case IB_WR_RDMA_WRITE_WITH_IMM: 2390 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2391 wqe->rdma.imm_data = wr->ex.imm_data; 2392 break; 2393 case IB_WR_RDMA_READ: 2394 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2395 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2396 break; 2397 default: 2398 return -EINVAL; 2399 } 2400 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2401 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2402 if (wr->send_flags & IB_SEND_SIGNALED) 2403 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2404 if (wr->send_flags & IB_SEND_FENCE) 2405 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2406 if (wr->send_flags & IB_SEND_SOLICITED) 2407 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2408 if (wr->send_flags & IB_SEND_INLINE) 2409 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2410 2411 return 0; 2412} 2413 2414static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2415 struct bnxt_qplib_swqe *wqe) 2416{ 2417 switch (wr->opcode) { 2418 case IB_WR_ATOMIC_CMP_AND_SWP: 2419 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2420 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2421 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2422 break; 2423 case IB_WR_ATOMIC_FETCH_AND_ADD: 2424 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2425 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2426 break; 2427 default: 2428 return -EINVAL; 2429 } 2430 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2431 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2432 if (wr->send_flags & IB_SEND_SIGNALED) 2433 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2434 if (wr->send_flags & IB_SEND_FENCE) 2435 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2436 if (wr->send_flags & IB_SEND_SOLICITED) 2437 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2438 return 0; 2439} 2440 2441static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2442 struct bnxt_qplib_swqe *wqe) 2443{ 2444 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2445 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2446 2447 /* Need unconditional fence for local invalidate 2448 * opcode to work as expected. 2449 */ 2450 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2451 2452 if (wr->send_flags & IB_SEND_SIGNALED) 2453 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2454 if (wr->send_flags & IB_SEND_SOLICITED) 2455 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2456 2457 return 0; 2458} 2459 2460static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2461 struct bnxt_qplib_swqe *wqe) 2462{ 2463 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2464 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2465 int access = wr->access; 2466 2467 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2468 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2469 wqe->frmr.page_list = mr->pages; 2470 wqe->frmr.page_list_len = mr->npages; 2471 wqe->frmr.levels = qplib_frpl->hwq.level; 2472 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2473 2474 /* Need unconditional fence for reg_mr 2475 * opcode to function as expected. 2476 */ 2477 2478 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2479 2480 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2481 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2482 2483 if (access & IB_ACCESS_LOCAL_WRITE) 2484 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2485 if (access & IB_ACCESS_REMOTE_READ) 2486 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2487 if (access & IB_ACCESS_REMOTE_WRITE) 2488 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2489 if (access & IB_ACCESS_REMOTE_ATOMIC) 2490 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2491 if (access & IB_ACCESS_MW_BIND) 2492 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2493 2494 wqe->frmr.l_key = wr->key; 2495 wqe->frmr.length = wr->mr->length; 2496 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 2497 wqe->frmr.va = wr->mr->iova; 2498 return 0; 2499} 2500 2501static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2502 const struct ib_send_wr *wr, 2503 struct bnxt_qplib_swqe *wqe) 2504{ 2505 /* Copy the inline data to the data field */ 2506 u8 *in_data; 2507 u32 i, sge_len; 2508 void *sge_addr; 2509 2510 in_data = wqe->inline_data; 2511 for (i = 0; i < wr->num_sge; i++) { 2512 sge_addr = (void *)(unsigned long) 2513 wr->sg_list[i].addr; 2514 sge_len = wr->sg_list[i].length; 2515 2516 if ((sge_len + wqe->inline_len) > 2517 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2518 ibdev_err(&rdev->ibdev, 2519 "Inline data size requested > supported value"); 2520 return -EINVAL; 2521 } 2522 sge_len = wr->sg_list[i].length; 2523 2524 memcpy(in_data, sge_addr, sge_len); 2525 in_data += wr->sg_list[i].length; 2526 wqe->inline_len += wr->sg_list[i].length; 2527 } 2528 return wqe->inline_len; 2529} 2530 2531static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2532 const struct ib_send_wr *wr, 2533 struct bnxt_qplib_swqe *wqe) 2534{ 2535 int payload_sz = 0; 2536 2537 if (wr->send_flags & IB_SEND_INLINE) 2538 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2539 else 2540 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2541 wqe->num_sge); 2542 2543 return payload_sz; 2544} 2545 2546static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2547{ 2548 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2549 qp->ib_qp.qp_type == IB_QPT_GSI || 2550 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2551 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2552 int qp_attr_mask; 2553 struct ib_qp_attr qp_attr; 2554 2555 qp_attr_mask = IB_QP_STATE; 2556 qp_attr.qp_state = IB_QPS_RTS; 2557 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2558 qp->qplib_qp.wqe_cnt = 0; 2559 } 2560} 2561 2562static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2563 struct bnxt_re_qp *qp, 2564 const struct ib_send_wr *wr) 2565{ 2566 int rc = 0, payload_sz = 0; 2567 unsigned long flags; 2568 2569 spin_lock_irqsave(&qp->sq_lock, flags); 2570 while (wr) { 2571 struct bnxt_qplib_swqe wqe = {}; 2572 2573 /* Common */ 2574 wqe.num_sge = wr->num_sge; 2575 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2576 ibdev_err(&rdev->ibdev, 2577 "Limit exceeded for Send SGEs"); 2578 rc = -EINVAL; 2579 goto bad; 2580 } 2581 2582 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2583 if (payload_sz < 0) { 2584 rc = -EINVAL; 2585 goto bad; 2586 } 2587 wqe.wr_id = wr->wr_id; 2588 2589 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2590 2591 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2592 if (!rc) 2593 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2594bad: 2595 if (rc) { 2596 ibdev_err(&rdev->ibdev, 2597 "Post send failed opcode = %#x rc = %d", 2598 wr->opcode, rc); 2599 break; 2600 } 2601 wr = wr->next; 2602 } 2603 bnxt_qplib_post_send_db(&qp->qplib_qp); 2604 bnxt_ud_qp_hw_stall_workaround(qp); 2605 spin_unlock_irqrestore(&qp->sq_lock, flags); 2606 return rc; 2607} 2608 2609int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2610 const struct ib_send_wr **bad_wr) 2611{ 2612 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2613 struct bnxt_qplib_swqe wqe; 2614 int rc = 0, payload_sz = 0; 2615 unsigned long flags; 2616 2617 spin_lock_irqsave(&qp->sq_lock, flags); 2618 while (wr) { 2619 /* House keeping */ 2620 memset(&wqe, 0, sizeof(wqe)); 2621 2622 /* Common */ 2623 wqe.num_sge = wr->num_sge; 2624 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2625 ibdev_err(&qp->rdev->ibdev, 2626 "Limit exceeded for Send SGEs"); 2627 rc = -EINVAL; 2628 goto bad; 2629 } 2630 2631 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2632 if (payload_sz < 0) { 2633 rc = -EINVAL; 2634 goto bad; 2635 } 2636 wqe.wr_id = wr->wr_id; 2637 2638 switch (wr->opcode) { 2639 case IB_WR_SEND: 2640 case IB_WR_SEND_WITH_IMM: 2641 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2642 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2643 payload_sz); 2644 if (rc) 2645 goto bad; 2646 wqe.rawqp1.lflags |= 2647 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2648 } 2649 switch (wr->send_flags) { 2650 case IB_SEND_IP_CSUM: 2651 wqe.rawqp1.lflags |= 2652 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2653 break; 2654 default: 2655 break; 2656 } 2657 fallthrough; 2658 case IB_WR_SEND_WITH_INV: 2659 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2660 break; 2661 case IB_WR_RDMA_WRITE: 2662 case IB_WR_RDMA_WRITE_WITH_IMM: 2663 case IB_WR_RDMA_READ: 2664 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2665 break; 2666 case IB_WR_ATOMIC_CMP_AND_SWP: 2667 case IB_WR_ATOMIC_FETCH_AND_ADD: 2668 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2669 break; 2670 case IB_WR_RDMA_READ_WITH_INV: 2671 ibdev_err(&qp->rdev->ibdev, 2672 "RDMA Read with Invalidate is not supported"); 2673 rc = -EINVAL; 2674 goto bad; 2675 case IB_WR_LOCAL_INV: 2676 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2677 break; 2678 case IB_WR_REG_MR: 2679 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2680 break; 2681 default: 2682 /* Unsupported WRs */ 2683 ibdev_err(&qp->rdev->ibdev, 2684 "WR (%#x) is not supported", wr->opcode); 2685 rc = -EINVAL; 2686 goto bad; 2687 } 2688 if (!rc) 2689 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2690bad: 2691 if (rc) { 2692 ibdev_err(&qp->rdev->ibdev, 2693 "post_send failed op:%#x qps = %#x rc = %d\n", 2694 wr->opcode, qp->qplib_qp.state, rc); 2695 *bad_wr = wr; 2696 break; 2697 } 2698 wr = wr->next; 2699 } 2700 bnxt_qplib_post_send_db(&qp->qplib_qp); 2701 bnxt_ud_qp_hw_stall_workaround(qp); 2702 spin_unlock_irqrestore(&qp->sq_lock, flags); 2703 2704 return rc; 2705} 2706 2707static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2708 struct bnxt_re_qp *qp, 2709 const struct ib_recv_wr *wr) 2710{ 2711 struct bnxt_qplib_swqe wqe; 2712 int rc = 0; 2713 2714 memset(&wqe, 0, sizeof(wqe)); 2715 while (wr) { 2716 /* House keeping */ 2717 memset(&wqe, 0, sizeof(wqe)); 2718 2719 /* Common */ 2720 wqe.num_sge = wr->num_sge; 2721 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2722 ibdev_err(&rdev->ibdev, 2723 "Limit exceeded for Receive SGEs"); 2724 rc = -EINVAL; 2725 break; 2726 } 2727 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2728 wqe.wr_id = wr->wr_id; 2729 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2730 2731 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2732 if (rc) 2733 break; 2734 2735 wr = wr->next; 2736 } 2737 if (!rc) 2738 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2739 return rc; 2740} 2741 2742int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2743 const struct ib_recv_wr **bad_wr) 2744{ 2745 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2746 struct bnxt_qplib_swqe wqe; 2747 int rc = 0, payload_sz = 0; 2748 unsigned long flags; 2749 u32 count = 0; 2750 2751 spin_lock_irqsave(&qp->rq_lock, flags); 2752 while (wr) { 2753 /* House keeping */ 2754 memset(&wqe, 0, sizeof(wqe)); 2755 2756 /* Common */ 2757 wqe.num_sge = wr->num_sge; 2758 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2759 ibdev_err(&qp->rdev->ibdev, 2760 "Limit exceeded for Receive SGEs"); 2761 rc = -EINVAL; 2762 *bad_wr = wr; 2763 break; 2764 } 2765 2766 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2767 wr->num_sge); 2768 wqe.wr_id = wr->wr_id; 2769 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2770 2771 if (ib_qp->qp_type == IB_QPT_GSI && 2772 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2773 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2774 payload_sz); 2775 if (!rc) 2776 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2777 if (rc) { 2778 *bad_wr = wr; 2779 break; 2780 } 2781 2782 /* Ring DB if the RQEs posted reaches a threshold value */ 2783 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2784 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2785 count = 0; 2786 } 2787 2788 wr = wr->next; 2789 } 2790 2791 if (count) 2792 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2793 2794 spin_unlock_irqrestore(&qp->rq_lock, flags); 2795 2796 return rc; 2797} 2798 2799/* Completion Queues */ 2800int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2801{ 2802 struct bnxt_re_cq *cq; 2803 struct bnxt_qplib_nq *nq; 2804 struct bnxt_re_dev *rdev; 2805 2806 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2807 rdev = cq->rdev; 2808 nq = cq->qplib_cq.nq; 2809 2810 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2811 ib_umem_release(cq->umem); 2812 2813 atomic_dec(&rdev->cq_count); 2814 nq->budget--; 2815 kfree(cq->cql); 2816 return 0; 2817} 2818 2819int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2820 struct ib_udata *udata) 2821{ 2822 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2823 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2824 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2825 int rc, entries; 2826 int cqe = attr->cqe; 2827 struct bnxt_qplib_nq *nq = NULL; 2828 unsigned int nq_alloc_cnt; 2829 2830 /* Validate CQ fields */ 2831 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2832 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 2833 return -EINVAL; 2834 } 2835 2836 cq->rdev = rdev; 2837 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2838 2839 entries = roundup_pow_of_two(cqe + 1); 2840 if (entries > dev_attr->max_cq_wqes + 1) 2841 entries = dev_attr->max_cq_wqes + 1; 2842 2843 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 2844 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 2845 if (udata) { 2846 struct bnxt_re_cq_req req; 2847 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 2848 udata, struct bnxt_re_ucontext, ib_uctx); 2849 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2850 rc = -EFAULT; 2851 goto fail; 2852 } 2853 2854 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 2855 entries * sizeof(struct cq_base), 2856 IB_ACCESS_LOCAL_WRITE); 2857 if (IS_ERR(cq->umem)) { 2858 rc = PTR_ERR(cq->umem); 2859 goto fail; 2860 } 2861 cq->qplib_cq.sg_info.umem = cq->umem; 2862 cq->qplib_cq.dpi = &uctx->dpi; 2863 } else { 2864 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2865 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2866 GFP_KERNEL); 2867 if (!cq->cql) { 2868 rc = -ENOMEM; 2869 goto fail; 2870 } 2871 2872 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2873 } 2874 /* 2875 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2876 * used for getting the NQ index. 2877 */ 2878 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2879 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2880 cq->qplib_cq.max_wqe = entries; 2881 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2882 cq->qplib_cq.nq = nq; 2883 2884 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2885 if (rc) { 2886 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 2887 goto fail; 2888 } 2889 2890 cq->ib_cq.cqe = entries; 2891 cq->cq_period = cq->qplib_cq.period; 2892 nq->budget++; 2893 2894 atomic_inc(&rdev->cq_count); 2895 spin_lock_init(&cq->cq_lock); 2896 2897 if (udata) { 2898 struct bnxt_re_cq_resp resp; 2899 2900 resp.cqid = cq->qplib_cq.id; 2901 resp.tail = cq->qplib_cq.hwq.cons; 2902 resp.phase = cq->qplib_cq.period; 2903 resp.rsvd = 0; 2904 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2905 if (rc) { 2906 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 2907 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2908 goto c2fail; 2909 } 2910 } 2911 2912 return 0; 2913 2914c2fail: 2915 ib_umem_release(cq->umem); 2916fail: 2917 kfree(cq->cql); 2918 return rc; 2919} 2920 2921static u8 __req_to_ib_wc_status(u8 qstatus) 2922{ 2923 switch (qstatus) { 2924 case CQ_REQ_STATUS_OK: 2925 return IB_WC_SUCCESS; 2926 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2927 return IB_WC_BAD_RESP_ERR; 2928 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2929 return IB_WC_LOC_LEN_ERR; 2930 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2931 return IB_WC_LOC_QP_OP_ERR; 2932 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2933 return IB_WC_LOC_PROT_ERR; 2934 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2935 return IB_WC_GENERAL_ERR; 2936 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2937 return IB_WC_REM_INV_REQ_ERR; 2938 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2939 return IB_WC_REM_ACCESS_ERR; 2940 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2941 return IB_WC_REM_OP_ERR; 2942 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2943 return IB_WC_RNR_RETRY_EXC_ERR; 2944 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2945 return IB_WC_RETRY_EXC_ERR; 2946 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2947 return IB_WC_WR_FLUSH_ERR; 2948 default: 2949 return IB_WC_GENERAL_ERR; 2950 } 2951 return 0; 2952} 2953 2954static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2955{ 2956 switch (qstatus) { 2957 case CQ_RES_RAWETH_QP1_STATUS_OK: 2958 return IB_WC_SUCCESS; 2959 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2960 return IB_WC_LOC_ACCESS_ERR; 2961 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2962 return IB_WC_LOC_LEN_ERR; 2963 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2964 return IB_WC_LOC_PROT_ERR; 2965 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2966 return IB_WC_LOC_QP_OP_ERR; 2967 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2968 return IB_WC_GENERAL_ERR; 2969 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2970 return IB_WC_WR_FLUSH_ERR; 2971 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2972 return IB_WC_WR_FLUSH_ERR; 2973 default: 2974 return IB_WC_GENERAL_ERR; 2975 } 2976} 2977 2978static u8 __rc_to_ib_wc_status(u8 qstatus) 2979{ 2980 switch (qstatus) { 2981 case CQ_RES_RC_STATUS_OK: 2982 return IB_WC_SUCCESS; 2983 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2984 return IB_WC_LOC_ACCESS_ERR; 2985 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2986 return IB_WC_LOC_LEN_ERR; 2987 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2988 return IB_WC_LOC_PROT_ERR; 2989 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2990 return IB_WC_LOC_QP_OP_ERR; 2991 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2992 return IB_WC_GENERAL_ERR; 2993 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2994 return IB_WC_REM_INV_REQ_ERR; 2995 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2996 return IB_WC_WR_FLUSH_ERR; 2997 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2998 return IB_WC_WR_FLUSH_ERR; 2999 default: 3000 return IB_WC_GENERAL_ERR; 3001 } 3002} 3003 3004static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3005{ 3006 switch (cqe->type) { 3007 case BNXT_QPLIB_SWQE_TYPE_SEND: 3008 wc->opcode = IB_WC_SEND; 3009 break; 3010 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3011 wc->opcode = IB_WC_SEND; 3012 wc->wc_flags |= IB_WC_WITH_IMM; 3013 break; 3014 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3015 wc->opcode = IB_WC_SEND; 3016 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3017 break; 3018 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3019 wc->opcode = IB_WC_RDMA_WRITE; 3020 break; 3021 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3022 wc->opcode = IB_WC_RDMA_WRITE; 3023 wc->wc_flags |= IB_WC_WITH_IMM; 3024 break; 3025 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3026 wc->opcode = IB_WC_RDMA_READ; 3027 break; 3028 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3029 wc->opcode = IB_WC_COMP_SWAP; 3030 break; 3031 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3032 wc->opcode = IB_WC_FETCH_ADD; 3033 break; 3034 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3035 wc->opcode = IB_WC_LOCAL_INV; 3036 break; 3037 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3038 wc->opcode = IB_WC_REG_MR; 3039 break; 3040 default: 3041 wc->opcode = IB_WC_SEND; 3042 break; 3043 } 3044 3045 wc->status = __req_to_ib_wc_status(cqe->status); 3046} 3047 3048static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3049 u16 raweth_qp1_flags2) 3050{ 3051 bool is_ipv6 = false, is_ipv4 = false; 3052 3053 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3054 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3055 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3056 return -1; 3057 3058 if (raweth_qp1_flags2 & 3059 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3060 raweth_qp1_flags2 & 3061 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3062 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3063 (raweth_qp1_flags2 & 3064 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3065 (is_ipv6 = true) : (is_ipv4 = true); 3066 return ((is_ipv6) ? 3067 BNXT_RE_ROCEV2_IPV6_PACKET : 3068 BNXT_RE_ROCEV2_IPV4_PACKET); 3069 } else { 3070 return BNXT_RE_ROCE_V1_PACKET; 3071 } 3072} 3073 3074static int bnxt_re_to_ib_nw_type(int nw_type) 3075{ 3076 u8 nw_hdr_type = 0xFF; 3077 3078 switch (nw_type) { 3079 case BNXT_RE_ROCE_V1_PACKET: 3080 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3081 break; 3082 case BNXT_RE_ROCEV2_IPV4_PACKET: 3083 nw_hdr_type = RDMA_NETWORK_IPV4; 3084 break; 3085 case BNXT_RE_ROCEV2_IPV6_PACKET: 3086 nw_hdr_type = RDMA_NETWORK_IPV6; 3087 break; 3088 } 3089 return nw_hdr_type; 3090} 3091 3092static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3093 void *rq_hdr_buf) 3094{ 3095 u8 *tmp_buf = NULL; 3096 struct ethhdr *eth_hdr; 3097 u16 eth_type; 3098 bool rc = false; 3099 3100 tmp_buf = (u8 *)rq_hdr_buf; 3101 /* 3102 * If dest mac is not same as I/F mac, this could be a 3103 * loopback address or multicast address, check whether 3104 * it is a loopback packet 3105 */ 3106 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3107 tmp_buf += 4; 3108 /* Check the ether type */ 3109 eth_hdr = (struct ethhdr *)tmp_buf; 3110 eth_type = ntohs(eth_hdr->h_proto); 3111 switch (eth_type) { 3112 case ETH_P_IBOE: 3113 rc = true; 3114 break; 3115 case ETH_P_IP: 3116 case ETH_P_IPV6: { 3117 u32 len; 3118 struct udphdr *udp_hdr; 3119 3120 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3121 sizeof(struct ipv6hdr)); 3122 tmp_buf += sizeof(struct ethhdr) + len; 3123 udp_hdr = (struct udphdr *)tmp_buf; 3124 if (ntohs(udp_hdr->dest) == 3125 ROCE_V2_UDP_DPORT) 3126 rc = true; 3127 break; 3128 } 3129 default: 3130 break; 3131 } 3132 } 3133 3134 return rc; 3135} 3136 3137static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3138 struct bnxt_qplib_cqe *cqe) 3139{ 3140 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3141 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3142 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3143 struct bnxt_re_ah *gsi_sah; 3144 struct ib_send_wr *swr; 3145 struct ib_ud_wr udwr; 3146 struct ib_recv_wr rwr; 3147 int pkt_type = 0; 3148 u32 tbl_idx; 3149 void *rq_hdr_buf; 3150 dma_addr_t rq_hdr_buf_map; 3151 dma_addr_t shrq_hdr_buf_map; 3152 u32 offset = 0; 3153 u32 skip_bytes = 0; 3154 struct ib_sge s_sge[2]; 3155 struct ib_sge r_sge[2]; 3156 int rc; 3157 3158 memset(&udwr, 0, sizeof(udwr)); 3159 memset(&rwr, 0, sizeof(rwr)); 3160 memset(&s_sge, 0, sizeof(s_sge)); 3161 memset(&r_sge, 0, sizeof(r_sge)); 3162 3163 swr = &udwr.wr; 3164 tbl_idx = cqe->wr_id; 3165 3166 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3167 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3168 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3169 tbl_idx); 3170 3171 /* Shadow QP header buffer */ 3172 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3173 tbl_idx); 3174 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3175 3176 /* Store this cqe */ 3177 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3178 sqp_entry->qp1_qp = gsi_qp; 3179 3180 /* Find packet type from the cqe */ 3181 3182 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3183 cqe->raweth_qp1_flags2); 3184 if (pkt_type < 0) { 3185 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3186 return -EINVAL; 3187 } 3188 3189 /* Adjust the offset for the user buffer and post in the rq */ 3190 3191 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3192 offset = 20; 3193 3194 /* 3195 * QP1 loopback packet has 4 bytes of internal header before 3196 * ether header. Skip these four bytes. 3197 */ 3198 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3199 skip_bytes = 4; 3200 3201 /* First send SGE . Skip the ether header*/ 3202 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3203 + skip_bytes; 3204 s_sge[0].lkey = 0xFFFFFFFF; 3205 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3206 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3207 3208 /* Second Send SGE */ 3209 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3210 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3211 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3212 s_sge[1].addr += 8; 3213 s_sge[1].lkey = 0xFFFFFFFF; 3214 s_sge[1].length = 256; 3215 3216 /* First recv SGE */ 3217 3218 r_sge[0].addr = shrq_hdr_buf_map; 3219 r_sge[0].lkey = 0xFFFFFFFF; 3220 r_sge[0].length = 40; 3221 3222 r_sge[1].addr = sqp_entry->sge.addr + offset; 3223 r_sge[1].lkey = sqp_entry->sge.lkey; 3224 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3225 3226 /* Create receive work request */ 3227 rwr.num_sge = 2; 3228 rwr.sg_list = r_sge; 3229 rwr.wr_id = tbl_idx; 3230 rwr.next = NULL; 3231 3232 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3233 if (rc) { 3234 ibdev_err(&rdev->ibdev, 3235 "Failed to post Rx buffers to shadow QP"); 3236 return -ENOMEM; 3237 } 3238 3239 swr->num_sge = 2; 3240 swr->sg_list = s_sge; 3241 swr->wr_id = tbl_idx; 3242 swr->opcode = IB_WR_SEND; 3243 swr->next = NULL; 3244 gsi_sah = rdev->gsi_ctx.gsi_sah; 3245 udwr.ah = &gsi_sah->ib_ah; 3246 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3247 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3248 3249 /* post data received in the send queue */ 3250 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3251} 3252 3253static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3254 struct bnxt_qplib_cqe *cqe) 3255{ 3256 wc->opcode = IB_WC_RECV; 3257 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3258 wc->wc_flags |= IB_WC_GRH; 3259} 3260 3261static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3262 u16 vlan_id) 3263{ 3264 /* 3265 * Check if the vlan is configured in the host. If not configured, it 3266 * can be a transparent VLAN. So dont report the vlan id. 3267 */ 3268 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3269 htons(ETH_P_8021Q), vlan_id)) 3270 return false; 3271 return true; 3272} 3273 3274static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3275 u16 *vid, u8 *sl) 3276{ 3277 bool ret = false; 3278 u32 metadata; 3279 u16 tpid; 3280 3281 metadata = orig_cqe->raweth_qp1_metadata; 3282 if (orig_cqe->raweth_qp1_flags2 & 3283 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3284 tpid = ((metadata & 3285 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3286 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3287 if (tpid == ETH_P_8021Q) { 3288 *vid = metadata & 3289 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3290 *sl = (metadata & 3291 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3292 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3293 ret = true; 3294 } 3295 } 3296 3297 return ret; 3298} 3299 3300static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3301 struct bnxt_qplib_cqe *cqe) 3302{ 3303 wc->opcode = IB_WC_RECV; 3304 wc->status = __rc_to_ib_wc_status(cqe->status); 3305 3306 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3307 wc->wc_flags |= IB_WC_WITH_IMM; 3308 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3309 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3310 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3311 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3312 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3313} 3314 3315static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3316 struct ib_wc *wc, 3317 struct bnxt_qplib_cqe *cqe) 3318{ 3319 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3320 struct bnxt_re_qp *gsi_qp = NULL; 3321 struct bnxt_qplib_cqe *orig_cqe = NULL; 3322 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3323 int nw_type; 3324 u32 tbl_idx; 3325 u16 vlan_id; 3326 u8 sl; 3327 3328 tbl_idx = cqe->wr_id; 3329 3330 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3331 gsi_qp = sqp_entry->qp1_qp; 3332 orig_cqe = &sqp_entry->cqe; 3333 3334 wc->wr_id = sqp_entry->wrid; 3335 wc->byte_len = orig_cqe->length; 3336 wc->qp = &gsi_qp->ib_qp; 3337 3338 wc->ex.imm_data = orig_cqe->immdata; 3339 wc->src_qp = orig_cqe->src_qp; 3340 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3341 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3342 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3343 wc->vlan_id = vlan_id; 3344 wc->sl = sl; 3345 wc->wc_flags |= IB_WC_WITH_VLAN; 3346 } 3347 } 3348 wc->port_num = 1; 3349 wc->vendor_err = orig_cqe->status; 3350 3351 wc->opcode = IB_WC_RECV; 3352 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3353 wc->wc_flags |= IB_WC_GRH; 3354 3355 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3356 orig_cqe->raweth_qp1_flags2); 3357 if (nw_type >= 0) { 3358 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3359 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3360 } 3361} 3362 3363static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3364 struct ib_wc *wc, 3365 struct bnxt_qplib_cqe *cqe) 3366{ 3367 struct bnxt_re_dev *rdev; 3368 u16 vlan_id = 0; 3369 u8 nw_type; 3370 3371 rdev = qp->rdev; 3372 wc->opcode = IB_WC_RECV; 3373 wc->status = __rc_to_ib_wc_status(cqe->status); 3374 3375 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3376 wc->wc_flags |= IB_WC_WITH_IMM; 3377 /* report only on GSI QP for Thor */ 3378 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3379 wc->wc_flags |= IB_WC_GRH; 3380 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3381 wc->wc_flags |= IB_WC_WITH_SMAC; 3382 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3383 vlan_id = (cqe->cfa_meta & 0xFFF); 3384 } 3385 /* Mark only if vlan_id is non zero */ 3386 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3387 wc->vlan_id = vlan_id; 3388 wc->wc_flags |= IB_WC_WITH_VLAN; 3389 } 3390 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3391 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3392 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3393 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3394 } 3395 3396} 3397 3398static int send_phantom_wqe(struct bnxt_re_qp *qp) 3399{ 3400 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3401 unsigned long flags; 3402 int rc = 0; 3403 3404 spin_lock_irqsave(&qp->sq_lock, flags); 3405 3406 rc = bnxt_re_bind_fence_mw(lib_qp); 3407 if (!rc) { 3408 lib_qp->sq.phantom_wqe_cnt++; 3409 ibdev_dbg(&qp->rdev->ibdev, 3410 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3411 lib_qp->id, lib_qp->sq.hwq.prod, 3412 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3413 lib_qp->sq.phantom_wqe_cnt); 3414 } 3415 3416 spin_unlock_irqrestore(&qp->sq_lock, flags); 3417 return rc; 3418} 3419 3420int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3421{ 3422 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3423 struct bnxt_re_qp *qp, *sh_qp; 3424 struct bnxt_qplib_cqe *cqe; 3425 int i, ncqe, budget; 3426 struct bnxt_qplib_q *sq; 3427 struct bnxt_qplib_qp *lib_qp; 3428 u32 tbl_idx; 3429 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3430 unsigned long flags; 3431 3432 spin_lock_irqsave(&cq->cq_lock, flags); 3433 budget = min_t(u32, num_entries, cq->max_cql); 3434 num_entries = budget; 3435 if (!cq->cql) { 3436 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3437 goto exit; 3438 } 3439 cqe = &cq->cql[0]; 3440 while (budget) { 3441 lib_qp = NULL; 3442 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3443 if (lib_qp) { 3444 sq = &lib_qp->sq; 3445 if (sq->send_phantom) { 3446 qp = container_of(lib_qp, 3447 struct bnxt_re_qp, qplib_qp); 3448 if (send_phantom_wqe(qp) == -ENOMEM) 3449 ibdev_err(&cq->rdev->ibdev, 3450 "Phantom failed! Scheduled to send again\n"); 3451 else 3452 sq->send_phantom = false; 3453 } 3454 } 3455 if (ncqe < budget) 3456 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3457 cqe + ncqe, 3458 budget - ncqe); 3459 3460 if (!ncqe) 3461 break; 3462 3463 for (i = 0; i < ncqe; i++, cqe++) { 3464 /* Transcribe each qplib_wqe back to ib_wc */ 3465 memset(wc, 0, sizeof(*wc)); 3466 3467 wc->wr_id = cqe->wr_id; 3468 wc->byte_len = cqe->length; 3469 qp = container_of 3470 ((struct bnxt_qplib_qp *) 3471 (unsigned long)(cqe->qp_handle), 3472 struct bnxt_re_qp, qplib_qp); 3473 if (!qp) { 3474 ibdev_err(&cq->rdev->ibdev, "POLL CQ : bad QP handle"); 3475 continue; 3476 } 3477 wc->qp = &qp->ib_qp; 3478 wc->ex.imm_data = cqe->immdata; 3479 wc->src_qp = cqe->src_qp; 3480 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3481 wc->port_num = 1; 3482 wc->vendor_err = cqe->status; 3483 3484 switch (cqe->opcode) { 3485 case CQ_BASE_CQE_TYPE_REQ: 3486 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3487 if (sh_qp && 3488 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3489 /* Handle this completion with 3490 * the stored completion 3491 */ 3492 memset(wc, 0, sizeof(*wc)); 3493 continue; 3494 } 3495 bnxt_re_process_req_wc(wc, cqe); 3496 break; 3497 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3498 if (!cqe->status) { 3499 int rc = 0; 3500 3501 rc = bnxt_re_process_raw_qp_pkt_rx 3502 (qp, cqe); 3503 if (!rc) { 3504 memset(wc, 0, sizeof(*wc)); 3505 continue; 3506 } 3507 cqe->status = -1; 3508 } 3509 /* Errors need not be looped back. 3510 * But change the wr_id to the one 3511 * stored in the table 3512 */ 3513 tbl_idx = cqe->wr_id; 3514 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3515 wc->wr_id = sqp_entry->wrid; 3516 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3517 break; 3518 case CQ_BASE_CQE_TYPE_RES_RC: 3519 bnxt_re_process_res_rc_wc(wc, cqe); 3520 break; 3521 case CQ_BASE_CQE_TYPE_RES_UD: 3522 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3523 if (sh_qp && 3524 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3525 /* Handle this completion with 3526 * the stored completion 3527 */ 3528 if (cqe->status) { 3529 continue; 3530 } else { 3531 bnxt_re_process_res_shadow_qp_wc 3532 (qp, wc, cqe); 3533 break; 3534 } 3535 } 3536 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3537 break; 3538 default: 3539 ibdev_err(&cq->rdev->ibdev, 3540 "POLL CQ : type 0x%x not handled", 3541 cqe->opcode); 3542 continue; 3543 } 3544 wc++; 3545 budget--; 3546 } 3547 } 3548exit: 3549 spin_unlock_irqrestore(&cq->cq_lock, flags); 3550 return num_entries - budget; 3551} 3552 3553int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3554 enum ib_cq_notify_flags ib_cqn_flags) 3555{ 3556 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3557 int type = 0, rc = 0; 3558 unsigned long flags; 3559 3560 spin_lock_irqsave(&cq->cq_lock, flags); 3561 /* Trigger on the very next completion */ 3562 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3563 type = DBC_DBC_TYPE_CQ_ARMALL; 3564 /* Trigger on the next solicited completion */ 3565 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3566 type = DBC_DBC_TYPE_CQ_ARMSE; 3567 3568 /* Poll to see if there are missed events */ 3569 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3570 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3571 rc = 1; 3572 goto exit; 3573 } 3574 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3575 3576exit: 3577 spin_unlock_irqrestore(&cq->cq_lock, flags); 3578 return rc; 3579} 3580 3581/* Memory Regions */ 3582struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3583{ 3584 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3585 struct bnxt_re_dev *rdev = pd->rdev; 3586 struct bnxt_re_mr *mr; 3587 int rc; 3588 3589 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3590 if (!mr) 3591 return ERR_PTR(-ENOMEM); 3592 3593 mr->rdev = rdev; 3594 mr->qplib_mr.pd = &pd->qplib_pd; 3595 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3596 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3597 3598 /* Allocate and register 0 as the address */ 3599 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3600 if (rc) 3601 goto fail; 3602 3603 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3604 mr->qplib_mr.total_size = -1; /* Infinte length */ 3605 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3606 PAGE_SIZE); 3607 if (rc) 3608 goto fail_mr; 3609 3610 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3611 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3612 IB_ACCESS_REMOTE_ATOMIC)) 3613 mr->ib_mr.rkey = mr->ib_mr.lkey; 3614 atomic_inc(&rdev->mr_count); 3615 3616 return &mr->ib_mr; 3617 3618fail_mr: 3619 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3620fail: 3621 kfree(mr); 3622 return ERR_PTR(rc); 3623} 3624 3625int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3626{ 3627 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3628 struct bnxt_re_dev *rdev = mr->rdev; 3629 int rc; 3630 3631 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3632 if (rc) { 3633 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 3634 return rc; 3635 } 3636 3637 if (mr->pages) { 3638 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3639 &mr->qplib_frpl); 3640 kfree(mr->pages); 3641 mr->npages = 0; 3642 mr->pages = NULL; 3643 } 3644 ib_umem_release(mr->ib_umem); 3645 3646 kfree(mr); 3647 atomic_dec(&rdev->mr_count); 3648 return rc; 3649} 3650 3651static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3652{ 3653 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3654 3655 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3656 return -ENOMEM; 3657 3658 mr->pages[mr->npages++] = addr; 3659 return 0; 3660} 3661 3662int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3663 unsigned int *sg_offset) 3664{ 3665 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3666 3667 mr->npages = 0; 3668 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3669} 3670 3671struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3672 u32 max_num_sg) 3673{ 3674 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3675 struct bnxt_re_dev *rdev = pd->rdev; 3676 struct bnxt_re_mr *mr = NULL; 3677 int rc; 3678 3679 if (type != IB_MR_TYPE_MEM_REG) { 3680 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 3681 return ERR_PTR(-EINVAL); 3682 } 3683 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3684 return ERR_PTR(-EINVAL); 3685 3686 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3687 if (!mr) 3688 return ERR_PTR(-ENOMEM); 3689 3690 mr->rdev = rdev; 3691 mr->qplib_mr.pd = &pd->qplib_pd; 3692 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3693 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3694 3695 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3696 if (rc) 3697 goto bail; 3698 3699 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3700 mr->ib_mr.rkey = mr->ib_mr.lkey; 3701 3702 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3703 if (!mr->pages) { 3704 rc = -ENOMEM; 3705 goto fail; 3706 } 3707 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3708 &mr->qplib_frpl, max_num_sg); 3709 if (rc) { 3710 ibdev_err(&rdev->ibdev, 3711 "Failed to allocate HW FR page list"); 3712 goto fail_mr; 3713 } 3714 3715 atomic_inc(&rdev->mr_count); 3716 return &mr->ib_mr; 3717 3718fail_mr: 3719 kfree(mr->pages); 3720fail: 3721 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3722bail: 3723 kfree(mr); 3724 return ERR_PTR(rc); 3725} 3726 3727struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3728 struct ib_udata *udata) 3729{ 3730 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3731 struct bnxt_re_dev *rdev = pd->rdev; 3732 struct bnxt_re_mw *mw; 3733 int rc; 3734 3735 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3736 if (!mw) 3737 return ERR_PTR(-ENOMEM); 3738 mw->rdev = rdev; 3739 mw->qplib_mw.pd = &pd->qplib_pd; 3740 3741 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3742 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3743 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3744 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3745 if (rc) { 3746 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 3747 goto fail; 3748 } 3749 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3750 3751 atomic_inc(&rdev->mw_count); 3752 return &mw->ib_mw; 3753 3754fail: 3755 kfree(mw); 3756 return ERR_PTR(rc); 3757} 3758 3759int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3760{ 3761 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3762 struct bnxt_re_dev *rdev = mw->rdev; 3763 int rc; 3764 3765 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3766 if (rc) { 3767 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 3768 return rc; 3769 } 3770 3771 kfree(mw); 3772 atomic_dec(&rdev->mw_count); 3773 return rc; 3774} 3775 3776/* uverbs */ 3777struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3778 u64 virt_addr, int mr_access_flags, 3779 struct ib_udata *udata) 3780{ 3781 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3782 struct bnxt_re_dev *rdev = pd->rdev; 3783 struct bnxt_re_mr *mr; 3784 struct ib_umem *umem; 3785 unsigned long page_size; 3786 int umem_pgs, rc; 3787 3788 if (length > BNXT_RE_MAX_MR_SIZE) { 3789 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 3790 length, BNXT_RE_MAX_MR_SIZE); 3791 return ERR_PTR(-ENOMEM); 3792 } 3793 3794 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3795 if (!mr) 3796 return ERR_PTR(-ENOMEM); 3797 3798 mr->rdev = rdev; 3799 mr->qplib_mr.pd = &pd->qplib_pd; 3800 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3801 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3802 3803 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3804 if (rc) { 3805 ibdev_err(&rdev->ibdev, "Failed to allocate MR"); 3806 goto free_mr; 3807 } 3808 /* The fixed portion of the rkey is the same as the lkey */ 3809 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3810 3811 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 3812 if (IS_ERR(umem)) { 3813 ibdev_err(&rdev->ibdev, "Failed to get umem"); 3814 rc = -EFAULT; 3815 goto free_mrw; 3816 } 3817 mr->ib_umem = umem; 3818 3819 mr->qplib_mr.va = virt_addr; 3820 page_size = ib_umem_find_best_pgsz( 3821 umem, BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M, virt_addr); 3822 if (!page_size) { 3823 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 3824 rc = -EFAULT; 3825 goto free_umem; 3826 } 3827 mr->qplib_mr.total_size = length; 3828 3829 if (page_size == BNXT_RE_PAGE_SIZE_4K && 3830 length > BNXT_RE_MAX_MR_SIZE_LOW) { 3831 ibdev_err(&rdev->ibdev, "Requested MR Sz:%llu Max sup:%llu", 3832 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW); 3833 rc = -EINVAL; 3834 goto free_umem; 3835 } 3836 3837 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 3838 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 3839 umem_pgs, page_size); 3840 if (rc) { 3841 ibdev_err(&rdev->ibdev, "Failed to register user MR"); 3842 goto free_umem; 3843 } 3844 3845 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3846 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3847 atomic_inc(&rdev->mr_count); 3848 3849 return &mr->ib_mr; 3850free_umem: 3851 ib_umem_release(umem); 3852free_mrw: 3853 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3854free_mr: 3855 kfree(mr); 3856 return ERR_PTR(rc); 3857} 3858 3859int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 3860{ 3861 struct ib_device *ibdev = ctx->device; 3862 struct bnxt_re_ucontext *uctx = 3863 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 3864 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3865 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3866 struct bnxt_re_uctx_resp resp; 3867 u32 chip_met_rev_num = 0; 3868 int rc; 3869 3870 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 3871 3872 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3873 ibdev_dbg(ibdev, " is different from the device %d ", 3874 BNXT_RE_ABI_VERSION); 3875 return -EPERM; 3876 } 3877 3878 uctx->rdev = rdev; 3879 3880 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3881 if (!uctx->shpg) { 3882 rc = -ENOMEM; 3883 goto fail; 3884 } 3885 spin_lock_init(&uctx->sh_lock); 3886 3887 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 3888 chip_met_rev_num = rdev->chip_ctx->chip_num; 3889 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 3890 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 3891 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 3892 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 3893 resp.chip_id0 = chip_met_rev_num; 3894 /* Future extension of chip info */ 3895 resp.chip_id1 = 0; 3896 /*Temp, Use xa_alloc instead */ 3897 resp.dev_id = rdev->en_dev->pdev->devfn; 3898 resp.max_qp = rdev->qplib_ctx.qpc_count; 3899 resp.pg_size = PAGE_SIZE; 3900 resp.cqe_sz = sizeof(struct cq_base); 3901 resp.max_cqd = dev_attr->max_cq_wqes; 3902 resp.rsvd = 0; 3903 3904 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 3905 if (rc) { 3906 ibdev_err(ibdev, "Failed to copy user context"); 3907 rc = -EFAULT; 3908 goto cfail; 3909 } 3910 3911 return 0; 3912cfail: 3913 free_page((unsigned long)uctx->shpg); 3914 uctx->shpg = NULL; 3915fail: 3916 return rc; 3917} 3918 3919void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3920{ 3921 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3922 struct bnxt_re_ucontext, 3923 ib_uctx); 3924 3925 struct bnxt_re_dev *rdev = uctx->rdev; 3926 3927 if (uctx->shpg) 3928 free_page((unsigned long)uctx->shpg); 3929 3930 if (uctx->dpi.dbr) { 3931 /* Free DPI only if this is the first PD allocated by the 3932 * application and mark the context dpi as NULL 3933 */ 3934 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3935 &rdev->qplib_res.dpi_tbl, &uctx->dpi); 3936 uctx->dpi.dbr = NULL; 3937 } 3938} 3939 3940/* Helper function to mmap the virtual memory from user app */ 3941int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3942{ 3943 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3944 struct bnxt_re_ucontext, 3945 ib_uctx); 3946 struct bnxt_re_dev *rdev = uctx->rdev; 3947 u64 pfn; 3948 3949 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3950 return -EINVAL; 3951 3952 if (vma->vm_pgoff) { 3953 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3954 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3955 PAGE_SIZE, vma->vm_page_prot)) { 3956 ibdev_err(&rdev->ibdev, "Failed to map DPI"); 3957 return -EAGAIN; 3958 } 3959 } else { 3960 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3961 if (remap_pfn_range(vma, vma->vm_start, 3962 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3963 ibdev_err(&rdev->ibdev, "Failed to map shared page"); 3964 return -EAGAIN; 3965 } 3966 } 3967 3968 return 0; 3969} 3970