1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ADIS16480 and similar IMUs driver 4 * 5 * Copyright 2012 Analog Devices Inc. 6 */ 7 8#include <linux/clk.h> 9#include <linux/bitfield.h> 10#include <linux/of_irq.h> 11#include <linux/interrupt.h> 12#include <linux/delay.h> 13#include <linux/mutex.h> 14#include <linux/device.h> 15#include <linux/kernel.h> 16#include <linux/spi/spi.h> 17#include <linux/slab.h> 18#include <linux/sysfs.h> 19#include <linux/module.h> 20 21#include <linux/iio/iio.h> 22#include <linux/iio/sysfs.h> 23#include <linux/iio/buffer.h> 24#include <linux/iio/imu/adis.h> 25 26#include <linux/debugfs.h> 27 28#define ADIS16480_PAGE_SIZE 0x80 29 30#define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) 31 32#define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */ 33#define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06) 34#define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08) 35#define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A) 36#define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C) 37#define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E) 38#define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10) 39#define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14) 40#define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18) 41#define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C) 42#define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20) 43#define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24) 44#define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28) 45#define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A) 46#define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C) 47#define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E) 48#define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40) 49#define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44) 50#define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48) 51#define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C) 52#define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50) 53#define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54) 54#define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E) 55 56#define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04) 57#define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06) 58#define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08) 59#define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A) 60#define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C) 61#define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E) 62#define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10) 63#define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14) 64#define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18) 65#define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C) 66#define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20) 67#define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24) 68#define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28) 69#define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A) 70#define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C) 71#define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40) 72#define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C) 73 74#define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02) 75#define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06) 76#define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08) 77#define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A) 78#define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C) 79#define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10) 80#define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16) 81#define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18) 82#define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20) 83#define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22) 84#define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24) 85#define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28) 86#define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A) 87#define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C) 88#define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E) 89#define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30) 90#define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32) 91#define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34) 92#define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36) 93#define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38) 94#define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A) 95#define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78) 96#define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A) 97#define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C) 98 99/* 100 * External clock scaling in PPS mode. 101 * Available only for ADIS1649x devices 102 */ 103#define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10) 104 105#define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20) 106 107/* Each filter coefficent bank spans two pages */ 108#define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \ 109 ADIS16480_REG((page) + 1, (x) - 60 + 8)) 110#define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x)) 111#define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x)) 112#define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x)) 113#define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x)) 114 115/* ADIS16480_REG_FNCTIO_CTRL */ 116#define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0) 117#define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x) 118#define ADIS16480_DRDY_POL_MSK BIT(2) 119#define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x) 120#define ADIS16480_DRDY_EN_MSK BIT(3) 121#define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x) 122#define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4) 123#define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x) 124#define ADIS16480_SYNC_EN_MSK BIT(7) 125#define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x) 126#define ADIS16480_SYNC_MODE_MSK BIT(8) 127#define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x) 128 129struct adis16480_chip_info { 130 unsigned int num_channels; 131 const struct iio_chan_spec *channels; 132 unsigned int gyro_max_val; 133 unsigned int gyro_max_scale; 134 unsigned int accel_max_val; 135 unsigned int accel_max_scale; 136 unsigned int temp_scale; 137 unsigned int int_clk; 138 unsigned int max_dec_rate; 139 const unsigned int *filter_freqs; 140 bool has_pps_clk_mode; 141 const struct adis_data adis_data; 142}; 143 144enum adis16480_int_pin { 145 ADIS16480_PIN_DIO1, 146 ADIS16480_PIN_DIO2, 147 ADIS16480_PIN_DIO3, 148 ADIS16480_PIN_DIO4 149}; 150 151enum adis16480_clock_mode { 152 ADIS16480_CLK_SYNC, 153 ADIS16480_CLK_PPS, 154 ADIS16480_CLK_INT 155}; 156 157struct adis16480 { 158 const struct adis16480_chip_info *chip_info; 159 160 struct adis adis; 161 struct clk *ext_clk; 162 enum adis16480_clock_mode clk_mode; 163 unsigned int clk_freq; 164}; 165 166static const char * const adis16480_int_pin_names[4] = { 167 [ADIS16480_PIN_DIO1] = "DIO1", 168 [ADIS16480_PIN_DIO2] = "DIO2", 169 [ADIS16480_PIN_DIO3] = "DIO3", 170 [ADIS16480_PIN_DIO4] = "DIO4", 171}; 172 173#ifdef CONFIG_DEBUG_FS 174 175static ssize_t adis16480_show_firmware_revision(struct file *file, 176 char __user *userbuf, size_t count, loff_t *ppos) 177{ 178 struct adis16480 *adis16480 = file->private_data; 179 char buf[7]; 180 size_t len; 181 u16 rev; 182 int ret; 183 184 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); 185 if (ret) 186 return ret; 187 188 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 189 190 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 191} 192 193static const struct file_operations adis16480_firmware_revision_fops = { 194 .open = simple_open, 195 .read = adis16480_show_firmware_revision, 196 .llseek = default_llseek, 197 .owner = THIS_MODULE, 198}; 199 200static ssize_t adis16480_show_firmware_date(struct file *file, 201 char __user *userbuf, size_t count, loff_t *ppos) 202{ 203 struct adis16480 *adis16480 = file->private_data; 204 u16 md, year; 205 char buf[12]; 206 size_t len; 207 int ret; 208 209 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); 210 if (ret) 211 return ret; 212 213 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); 214 if (ret) 215 return ret; 216 217 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", 218 md >> 8, md & 0xff, year); 219 220 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 221} 222 223static const struct file_operations adis16480_firmware_date_fops = { 224 .open = simple_open, 225 .read = adis16480_show_firmware_date, 226 .llseek = default_llseek, 227 .owner = THIS_MODULE, 228}; 229 230static int adis16480_show_serial_number(void *arg, u64 *val) 231{ 232 struct adis16480 *adis16480 = arg; 233 u16 serial; 234 int ret; 235 236 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM, 237 &serial); 238 if (ret) 239 return ret; 240 241 *val = serial; 242 243 return 0; 244} 245DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops, 246 adis16480_show_serial_number, NULL, "0x%.4llx\n"); 247 248static int adis16480_show_product_id(void *arg, u64 *val) 249{ 250 struct adis16480 *adis16480 = arg; 251 u16 prod_id; 252 int ret; 253 254 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID, 255 &prod_id); 256 if (ret) 257 return ret; 258 259 *val = prod_id; 260 261 return 0; 262} 263DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops, 264 adis16480_show_product_id, NULL, "%llu\n"); 265 266static int adis16480_show_flash_count(void *arg, u64 *val) 267{ 268 struct adis16480 *adis16480 = arg; 269 u32 flash_count; 270 int ret; 271 272 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT, 273 &flash_count); 274 if (ret) 275 return ret; 276 277 *val = flash_count; 278 279 return 0; 280} 281DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops, 282 adis16480_show_flash_count, NULL, "%lld\n"); 283 284static int adis16480_debugfs_init(struct iio_dev *indio_dev) 285{ 286 struct adis16480 *adis16480 = iio_priv(indio_dev); 287 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 288 289 debugfs_create_file_unsafe("firmware_revision", 0400, 290 d, adis16480, &adis16480_firmware_revision_fops); 291 debugfs_create_file_unsafe("firmware_date", 0400, 292 d, adis16480, &adis16480_firmware_date_fops); 293 debugfs_create_file_unsafe("serial_number", 0400, 294 d, adis16480, &adis16480_serial_number_fops); 295 debugfs_create_file_unsafe("product_id", 0400, 296 d, adis16480, &adis16480_product_id_fops); 297 debugfs_create_file_unsafe("flash_count", 0400, 298 d, adis16480, &adis16480_flash_count_fops); 299 300 return 0; 301} 302 303#else 304 305static int adis16480_debugfs_init(struct iio_dev *indio_dev) 306{ 307 return 0; 308} 309 310#endif 311 312static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2) 313{ 314 struct adis16480 *st = iio_priv(indio_dev); 315 unsigned int t, reg; 316 317 if (val < 0 || val2 < 0) 318 return -EINVAL; 319 320 t = val * 1000 + val2 / 1000; 321 if (t == 0) 322 return -EINVAL; 323 324 /* 325 * When using PPS mode, the rate of data collection is equal to the 326 * product of the external clock frequency and the scale factor in the 327 * SYNC_SCALE register. 328 * When using sync mode, or internal clock, the output data rate is 329 * equal with the clock frequency divided by DEC_RATE + 1. 330 */ 331 if (st->clk_mode == ADIS16480_CLK_PPS) { 332 t = t / st->clk_freq; 333 reg = ADIS16495_REG_SYNC_SCALE; 334 } else { 335 t = st->clk_freq / t; 336 reg = ADIS16480_REG_DEC_RATE; 337 } 338 339 if (t > st->chip_info->max_dec_rate) 340 t = st->chip_info->max_dec_rate; 341 342 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS)) 343 t--; 344 345 return adis_write_reg_16(&st->adis, reg, t); 346} 347 348static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2) 349{ 350 struct adis16480 *st = iio_priv(indio_dev); 351 uint16_t t; 352 int ret; 353 unsigned int freq; 354 unsigned int reg; 355 356 if (st->clk_mode == ADIS16480_CLK_PPS) 357 reg = ADIS16495_REG_SYNC_SCALE; 358 else 359 reg = ADIS16480_REG_DEC_RATE; 360 361 ret = adis_read_reg_16(&st->adis, reg, &t); 362 if (ret) 363 return ret; 364 365 /* 366 * When using PPS mode, the rate of data collection is equal to the 367 * product of the external clock frequency and the scale factor in the 368 * SYNC_SCALE register. 369 * When using sync mode, or internal clock, the output data rate is 370 * equal with the clock frequency divided by DEC_RATE + 1. 371 */ 372 if (st->clk_mode == ADIS16480_CLK_PPS) 373 freq = st->clk_freq * t; 374 else 375 freq = st->clk_freq / (t + 1); 376 377 *val = freq / 1000; 378 *val2 = (freq % 1000) * 1000; 379 380 return IIO_VAL_INT_PLUS_MICRO; 381} 382 383enum { 384 ADIS16480_SCAN_GYRO_X, 385 ADIS16480_SCAN_GYRO_Y, 386 ADIS16480_SCAN_GYRO_Z, 387 ADIS16480_SCAN_ACCEL_X, 388 ADIS16480_SCAN_ACCEL_Y, 389 ADIS16480_SCAN_ACCEL_Z, 390 ADIS16480_SCAN_MAGN_X, 391 ADIS16480_SCAN_MAGN_Y, 392 ADIS16480_SCAN_MAGN_Z, 393 ADIS16480_SCAN_BARO, 394 ADIS16480_SCAN_TEMP, 395}; 396 397static const unsigned int adis16480_calibbias_regs[] = { 398 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS, 399 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS, 400 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS, 401 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS, 402 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS, 403 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS, 404 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON, 405 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON, 406 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON, 407 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS, 408}; 409 410static const unsigned int adis16480_calibscale_regs[] = { 411 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE, 412 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE, 413 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE, 414 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE, 415 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE, 416 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE, 417}; 418 419static int adis16480_set_calibbias(struct iio_dev *indio_dev, 420 const struct iio_chan_spec *chan, int bias) 421{ 422 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 423 struct adis16480 *st = iio_priv(indio_dev); 424 425 switch (chan->type) { 426 case IIO_MAGN: 427 case IIO_PRESSURE: 428 if (bias < -0x8000 || bias >= 0x8000) 429 return -EINVAL; 430 return adis_write_reg_16(&st->adis, reg, bias); 431 case IIO_ANGL_VEL: 432 case IIO_ACCEL: 433 return adis_write_reg_32(&st->adis, reg, bias); 434 default: 435 break; 436 } 437 438 return -EINVAL; 439} 440 441static int adis16480_get_calibbias(struct iio_dev *indio_dev, 442 const struct iio_chan_spec *chan, int *bias) 443{ 444 unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; 445 struct adis16480 *st = iio_priv(indio_dev); 446 uint16_t val16; 447 uint32_t val32; 448 int ret; 449 450 switch (chan->type) { 451 case IIO_MAGN: 452 case IIO_PRESSURE: 453 ret = adis_read_reg_16(&st->adis, reg, &val16); 454 if (ret == 0) 455 *bias = sign_extend32(val16, 15); 456 break; 457 case IIO_ANGL_VEL: 458 case IIO_ACCEL: 459 ret = adis_read_reg_32(&st->adis, reg, &val32); 460 if (ret == 0) 461 *bias = sign_extend32(val32, 31); 462 break; 463 default: 464 ret = -EINVAL; 465 } 466 467 if (ret) 468 return ret; 469 470 return IIO_VAL_INT; 471} 472 473static int adis16480_set_calibscale(struct iio_dev *indio_dev, 474 const struct iio_chan_spec *chan, int scale) 475{ 476 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 477 struct adis16480 *st = iio_priv(indio_dev); 478 479 if (scale < -0x8000 || scale >= 0x8000) 480 return -EINVAL; 481 482 return adis_write_reg_16(&st->adis, reg, scale); 483} 484 485static int adis16480_get_calibscale(struct iio_dev *indio_dev, 486 const struct iio_chan_spec *chan, int *scale) 487{ 488 unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; 489 struct adis16480 *st = iio_priv(indio_dev); 490 uint16_t val16; 491 int ret; 492 493 ret = adis_read_reg_16(&st->adis, reg, &val16); 494 if (ret) 495 return ret; 496 497 *scale = sign_extend32(val16, 15); 498 return IIO_VAL_INT; 499} 500 501static const unsigned int adis16480_def_filter_freqs[] = { 502 310, 503 55, 504 275, 505 63, 506}; 507 508static const unsigned int adis16495_def_filter_freqs[] = { 509 300, 510 100, 511 300, 512 100, 513}; 514 515static const unsigned int ad16480_filter_data[][2] = { 516 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 }, 517 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 }, 518 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 }, 519 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 }, 520 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 }, 521 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 }, 522 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 }, 523 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 }, 524 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 }, 525}; 526 527static int adis16480_get_filter_freq(struct iio_dev *indio_dev, 528 const struct iio_chan_spec *chan, int *freq) 529{ 530 struct adis16480 *st = iio_priv(indio_dev); 531 unsigned int enable_mask, offset, reg; 532 uint16_t val; 533 int ret; 534 535 reg = ad16480_filter_data[chan->scan_index][0]; 536 offset = ad16480_filter_data[chan->scan_index][1]; 537 enable_mask = BIT(offset + 2); 538 539 ret = adis_read_reg_16(&st->adis, reg, &val); 540 if (ret) 541 return ret; 542 543 if (!(val & enable_mask)) 544 *freq = 0; 545 else 546 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3]; 547 548 return IIO_VAL_INT; 549} 550 551static int adis16480_set_filter_freq(struct iio_dev *indio_dev, 552 const struct iio_chan_spec *chan, unsigned int freq) 553{ 554 struct adis16480 *st = iio_priv(indio_dev); 555 struct mutex *slock = &st->adis.state_lock; 556 unsigned int enable_mask, offset, reg; 557 unsigned int diff, best_diff; 558 unsigned int i, best_freq; 559 uint16_t val; 560 int ret; 561 562 reg = ad16480_filter_data[chan->scan_index][0]; 563 offset = ad16480_filter_data[chan->scan_index][1]; 564 enable_mask = BIT(offset + 2); 565 566 mutex_lock(slock); 567 568 ret = __adis_read_reg_16(&st->adis, reg, &val); 569 if (ret) 570 goto out_unlock; 571 572 if (freq == 0) { 573 val &= ~enable_mask; 574 } else { 575 best_freq = 0; 576 best_diff = st->chip_info->filter_freqs[0]; 577 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) { 578 if (st->chip_info->filter_freqs[i] >= freq) { 579 diff = st->chip_info->filter_freqs[i] - freq; 580 if (diff < best_diff) { 581 best_diff = diff; 582 best_freq = i; 583 } 584 } 585 } 586 587 val &= ~(0x3 << offset); 588 val |= best_freq << offset; 589 val |= enable_mask; 590 } 591 592 ret = __adis_write_reg_16(&st->adis, reg, val); 593out_unlock: 594 mutex_unlock(slock); 595 596 return ret; 597} 598 599static int adis16480_read_raw(struct iio_dev *indio_dev, 600 const struct iio_chan_spec *chan, int *val, int *val2, long info) 601{ 602 struct adis16480 *st = iio_priv(indio_dev); 603 unsigned int temp; 604 605 switch (info) { 606 case IIO_CHAN_INFO_RAW: 607 return adis_single_conversion(indio_dev, chan, 0, val); 608 case IIO_CHAN_INFO_SCALE: 609 switch (chan->type) { 610 case IIO_ANGL_VEL: 611 *val = st->chip_info->gyro_max_scale; 612 *val2 = st->chip_info->gyro_max_val; 613 return IIO_VAL_FRACTIONAL; 614 case IIO_ACCEL: 615 *val = st->chip_info->accel_max_scale; 616 *val2 = st->chip_info->accel_max_val; 617 return IIO_VAL_FRACTIONAL; 618 case IIO_MAGN: 619 *val = 0; 620 *val2 = 100; /* 0.0001 gauss */ 621 return IIO_VAL_INT_PLUS_MICRO; 622 case IIO_TEMP: 623 /* 624 * +85 degrees Celsius = temp_max_scale 625 * +25 degrees Celsius = 0 626 * LSB, 25 degrees Celsius = 60 / temp_max_scale 627 */ 628 *val = st->chip_info->temp_scale / 1000; 629 *val2 = (st->chip_info->temp_scale % 1000) * 1000; 630 return IIO_VAL_INT_PLUS_MICRO; 631 case IIO_PRESSURE: 632 /* 633 * max scale is 1310 mbar 634 * max raw value is 32767 shifted for 32bits 635 */ 636 *val = 131; /* 1310mbar = 131 kPa */ 637 *val2 = 32767 << 16; 638 return IIO_VAL_FRACTIONAL; 639 default: 640 return -EINVAL; 641 } 642 case IIO_CHAN_INFO_OFFSET: 643 /* Only the temperature channel has a offset */ 644 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */ 645 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale); 646 return IIO_VAL_INT; 647 case IIO_CHAN_INFO_CALIBBIAS: 648 return adis16480_get_calibbias(indio_dev, chan, val); 649 case IIO_CHAN_INFO_CALIBSCALE: 650 return adis16480_get_calibscale(indio_dev, chan, val); 651 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 652 return adis16480_get_filter_freq(indio_dev, chan, val); 653 case IIO_CHAN_INFO_SAMP_FREQ: 654 return adis16480_get_freq(indio_dev, val, val2); 655 default: 656 return -EINVAL; 657 } 658} 659 660static int adis16480_write_raw(struct iio_dev *indio_dev, 661 const struct iio_chan_spec *chan, int val, int val2, long info) 662{ 663 switch (info) { 664 case IIO_CHAN_INFO_CALIBBIAS: 665 return adis16480_set_calibbias(indio_dev, chan, val); 666 case IIO_CHAN_INFO_CALIBSCALE: 667 return adis16480_set_calibscale(indio_dev, chan, val); 668 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 669 return adis16480_set_filter_freq(indio_dev, chan, val); 670 case IIO_CHAN_INFO_SAMP_FREQ: 671 return adis16480_set_freq(indio_dev, val, val2); 672 673 default: 674 return -EINVAL; 675 } 676} 677 678#define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \ 679 { \ 680 .type = (_type), \ 681 .modified = 1, \ 682 .channel2 = (_mod), \ 683 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 684 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 685 _info_sep, \ 686 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 687 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 688 .address = (_address), \ 689 .scan_index = (_si), \ 690 .scan_type = { \ 691 .sign = 's', \ 692 .realbits = (_bits), \ 693 .storagebits = (_bits), \ 694 .endianness = IIO_BE, \ 695 }, \ 696 } 697 698#define ADIS16480_GYRO_CHANNEL(_mod) \ 699 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 700 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \ 701 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 702 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 703 32) 704 705#define ADIS16480_ACCEL_CHANNEL(_mod) \ 706 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \ 707 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \ 708 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ 709 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 710 32) 711 712#define ADIS16480_MAGN_CHANNEL(_mod) \ 713 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \ 714 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \ 715 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 716 16) 717 718#define ADIS16480_PRESSURE_CHANNEL() \ 719 { \ 720 .type = IIO_PRESSURE, \ 721 .indexed = 1, \ 722 .channel = 0, \ 723 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 724 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 725 BIT(IIO_CHAN_INFO_SCALE), \ 726 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 727 .address = ADIS16480_REG_BAROM_OUT, \ 728 .scan_index = ADIS16480_SCAN_BARO, \ 729 .scan_type = { \ 730 .sign = 's', \ 731 .realbits = 32, \ 732 .storagebits = 32, \ 733 .endianness = IIO_BE, \ 734 }, \ 735 } 736 737#define ADIS16480_TEMP_CHANNEL() { \ 738 .type = IIO_TEMP, \ 739 .indexed = 1, \ 740 .channel = 0, \ 741 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 742 BIT(IIO_CHAN_INFO_SCALE) | \ 743 BIT(IIO_CHAN_INFO_OFFSET), \ 744 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 745 .address = ADIS16480_REG_TEMP_OUT, \ 746 .scan_index = ADIS16480_SCAN_TEMP, \ 747 .scan_type = { \ 748 .sign = 's', \ 749 .realbits = 16, \ 750 .storagebits = 16, \ 751 .endianness = IIO_BE, \ 752 }, \ 753 } 754 755static const struct iio_chan_spec adis16480_channels[] = { 756 ADIS16480_GYRO_CHANNEL(X), 757 ADIS16480_GYRO_CHANNEL(Y), 758 ADIS16480_GYRO_CHANNEL(Z), 759 ADIS16480_ACCEL_CHANNEL(X), 760 ADIS16480_ACCEL_CHANNEL(Y), 761 ADIS16480_ACCEL_CHANNEL(Z), 762 ADIS16480_MAGN_CHANNEL(X), 763 ADIS16480_MAGN_CHANNEL(Y), 764 ADIS16480_MAGN_CHANNEL(Z), 765 ADIS16480_PRESSURE_CHANNEL(), 766 ADIS16480_TEMP_CHANNEL(), 767 IIO_CHAN_SOFT_TIMESTAMP(11) 768}; 769 770static const struct iio_chan_spec adis16485_channels[] = { 771 ADIS16480_GYRO_CHANNEL(X), 772 ADIS16480_GYRO_CHANNEL(Y), 773 ADIS16480_GYRO_CHANNEL(Z), 774 ADIS16480_ACCEL_CHANNEL(X), 775 ADIS16480_ACCEL_CHANNEL(Y), 776 ADIS16480_ACCEL_CHANNEL(Z), 777 ADIS16480_TEMP_CHANNEL(), 778 IIO_CHAN_SOFT_TIMESTAMP(7) 779}; 780 781enum adis16480_variant { 782 ADIS16375, 783 ADIS16480, 784 ADIS16485, 785 ADIS16488, 786 ADIS16490, 787 ADIS16495_1, 788 ADIS16495_2, 789 ADIS16495_3, 790 ADIS16497_1, 791 ADIS16497_2, 792 ADIS16497_3, 793}; 794 795#define ADIS16480_DIAG_STAT_XGYRO_FAIL 0 796#define ADIS16480_DIAG_STAT_YGYRO_FAIL 1 797#define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2 798#define ADIS16480_DIAG_STAT_XACCL_FAIL 3 799#define ADIS16480_DIAG_STAT_YACCL_FAIL 4 800#define ADIS16480_DIAG_STAT_ZACCL_FAIL 5 801#define ADIS16480_DIAG_STAT_XMAGN_FAIL 8 802#define ADIS16480_DIAG_STAT_YMAGN_FAIL 9 803#define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10 804#define ADIS16480_DIAG_STAT_BARO_FAIL 11 805 806static const char * const adis16480_status_error_msgs[] = { 807 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure", 808 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure", 809 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure", 810 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure", 811 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure", 812 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure", 813 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure", 814 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure", 815 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure", 816 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure", 817}; 818 819static int adis16480_enable_irq(struct adis *adis, bool enable); 820 821#define ADIS16480_DATA(_prod_id, _timeouts) \ 822{ \ 823 .diag_stat_reg = ADIS16480_REG_DIAG_STS, \ 824 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD, \ 825 .prod_id_reg = ADIS16480_REG_PROD_ID, \ 826 .prod_id = (_prod_id), \ 827 .has_paging = true, \ 828 .read_delay = 5, \ 829 .write_delay = 5, \ 830 .self_test_mask = BIT(1), \ 831 .self_test_reg = ADIS16480_REG_GLOB_CMD, \ 832 .status_error_msgs = adis16480_status_error_msgs, \ 833 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) | \ 834 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) | \ 835 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) | \ 836 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) | \ 837 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) | \ 838 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) | \ 839 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) | \ 840 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) | \ 841 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) | \ 842 BIT(ADIS16480_DIAG_STAT_BARO_FAIL), \ 843 .enable_irq = adis16480_enable_irq, \ 844 .timeouts = (_timeouts), \ 845} 846 847static const struct adis_timeout adis16485_timeouts = { 848 .reset_ms = 560, 849 .sw_reset_ms = 120, 850 .self_test_ms = 12, 851}; 852 853static const struct adis_timeout adis16480_timeouts = { 854 .reset_ms = 560, 855 .sw_reset_ms = 560, 856 .self_test_ms = 12, 857}; 858 859static const struct adis_timeout adis16495_timeouts = { 860 .reset_ms = 170, 861 .sw_reset_ms = 130, 862 .self_test_ms = 40, 863}; 864 865static const struct adis_timeout adis16495_1_timeouts = { 866 .reset_ms = 250, 867 .sw_reset_ms = 210, 868 .self_test_ms = 20, 869}; 870 871static const struct adis16480_chip_info adis16480_chip_info[] = { 872 [ADIS16375] = { 873 .channels = adis16485_channels, 874 .num_channels = ARRAY_SIZE(adis16485_channels), 875 /* 876 * Typically we do IIO_RAD_TO_DEGREE in the denominator, which 877 * is exactly the same as IIO_DEGREE_TO_RAD in numerator, since 878 * it gives better approximation. However, in this case we 879 * cannot do it since it would not fit in a 32bit variable. 880 */ 881 .gyro_max_val = 22887 << 16, 882 .gyro_max_scale = IIO_DEGREE_TO_RAD(300), 883 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16), 884 .accel_max_scale = 18, 885 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 886 .int_clk = 2460000, 887 .max_dec_rate = 2048, 888 .filter_freqs = adis16480_def_filter_freqs, 889 .adis_data = ADIS16480_DATA(16375, &adis16485_timeouts), 890 }, 891 [ADIS16480] = { 892 .channels = adis16480_channels, 893 .num_channels = ARRAY_SIZE(adis16480_channels), 894 .gyro_max_val = 22500 << 16, 895 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 896 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16), 897 .accel_max_scale = 10, 898 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 899 .int_clk = 2460000, 900 .max_dec_rate = 2048, 901 .filter_freqs = adis16480_def_filter_freqs, 902 .adis_data = ADIS16480_DATA(16480, &adis16480_timeouts), 903 }, 904 [ADIS16485] = { 905 .channels = adis16485_channels, 906 .num_channels = ARRAY_SIZE(adis16485_channels), 907 .gyro_max_val = 22500 << 16, 908 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 909 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16), 910 .accel_max_scale = 5, 911 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 912 .int_clk = 2460000, 913 .max_dec_rate = 2048, 914 .filter_freqs = adis16480_def_filter_freqs, 915 .adis_data = ADIS16480_DATA(16485, &adis16485_timeouts), 916 }, 917 [ADIS16488] = { 918 .channels = adis16480_channels, 919 .num_channels = ARRAY_SIZE(adis16480_channels), 920 .gyro_max_val = 22500 << 16, 921 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 922 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16), 923 .accel_max_scale = 18, 924 .temp_scale = 5650, /* 5.65 milli degree Celsius */ 925 .int_clk = 2460000, 926 .max_dec_rate = 2048, 927 .filter_freqs = adis16480_def_filter_freqs, 928 .adis_data = ADIS16480_DATA(16488, &adis16485_timeouts), 929 }, 930 [ADIS16490] = { 931 .channels = adis16485_channels, 932 .num_channels = ARRAY_SIZE(adis16485_channels), 933 .gyro_max_val = 20000 << 16, 934 .gyro_max_scale = IIO_DEGREE_TO_RAD(100), 935 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16), 936 .accel_max_scale = 8, 937 .temp_scale = 14285, /* 14.285 milli degree Celsius */ 938 .int_clk = 4250000, 939 .max_dec_rate = 4250, 940 .filter_freqs = adis16495_def_filter_freqs, 941 .has_pps_clk_mode = true, 942 .adis_data = ADIS16480_DATA(16490, &adis16495_timeouts), 943 }, 944 [ADIS16495_1] = { 945 .channels = adis16485_channels, 946 .num_channels = ARRAY_SIZE(adis16485_channels), 947 .gyro_max_val = 20000 << 16, 948 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 949 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 950 .accel_max_scale = 8, 951 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 952 .int_clk = 4250000, 953 .max_dec_rate = 4250, 954 .filter_freqs = adis16495_def_filter_freqs, 955 .has_pps_clk_mode = true, 956 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 957 }, 958 [ADIS16495_2] = { 959 .channels = adis16485_channels, 960 .num_channels = ARRAY_SIZE(adis16485_channels), 961 .gyro_max_val = 18000 << 16, 962 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 963 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 964 .accel_max_scale = 8, 965 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 966 .int_clk = 4250000, 967 .max_dec_rate = 4250, 968 .filter_freqs = adis16495_def_filter_freqs, 969 .has_pps_clk_mode = true, 970 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 971 }, 972 [ADIS16495_3] = { 973 .channels = adis16485_channels, 974 .num_channels = ARRAY_SIZE(adis16485_channels), 975 .gyro_max_val = 20000 << 16, 976 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 977 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 978 .accel_max_scale = 8, 979 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 980 .int_clk = 4250000, 981 .max_dec_rate = 4250, 982 .filter_freqs = adis16495_def_filter_freqs, 983 .has_pps_clk_mode = true, 984 .adis_data = ADIS16480_DATA(16495, &adis16495_1_timeouts), 985 }, 986 [ADIS16497_1] = { 987 .channels = adis16485_channels, 988 .num_channels = ARRAY_SIZE(adis16485_channels), 989 .gyro_max_val = 20000 << 16, 990 .gyro_max_scale = IIO_DEGREE_TO_RAD(125), 991 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 992 .accel_max_scale = 40, 993 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 994 .int_clk = 4250000, 995 .max_dec_rate = 4250, 996 .filter_freqs = adis16495_def_filter_freqs, 997 .has_pps_clk_mode = true, 998 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 999 }, 1000 [ADIS16497_2] = { 1001 .channels = adis16485_channels, 1002 .num_channels = ARRAY_SIZE(adis16485_channels), 1003 .gyro_max_val = 18000 << 16, 1004 .gyro_max_scale = IIO_DEGREE_TO_RAD(450), 1005 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1006 .accel_max_scale = 40, 1007 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1008 .int_clk = 4250000, 1009 .max_dec_rate = 4250, 1010 .filter_freqs = adis16495_def_filter_freqs, 1011 .has_pps_clk_mode = true, 1012 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1013 }, 1014 [ADIS16497_3] = { 1015 .channels = adis16485_channels, 1016 .num_channels = ARRAY_SIZE(adis16485_channels), 1017 .gyro_max_val = 20000 << 16, 1018 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000), 1019 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16), 1020 .accel_max_scale = 40, 1021 .temp_scale = 12500, /* 12.5 milli degree Celsius */ 1022 .int_clk = 4250000, 1023 .max_dec_rate = 4250, 1024 .filter_freqs = adis16495_def_filter_freqs, 1025 .has_pps_clk_mode = true, 1026 .adis_data = ADIS16480_DATA(16497, &adis16495_1_timeouts), 1027 }, 1028}; 1029 1030static const struct iio_info adis16480_info = { 1031 .read_raw = &adis16480_read_raw, 1032 .write_raw = &adis16480_write_raw, 1033 .update_scan_mode = adis_update_scan_mode, 1034 .debugfs_reg_access = adis_debugfs_reg_access, 1035}; 1036 1037static int adis16480_stop_device(struct iio_dev *indio_dev) 1038{ 1039 struct adis16480 *st = iio_priv(indio_dev); 1040 int ret; 1041 1042 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9)); 1043 if (ret) 1044 dev_err(&indio_dev->dev, 1045 "Could not power down device: %d\n", ret); 1046 1047 return ret; 1048} 1049 1050static int adis16480_enable_irq(struct adis *adis, bool enable) 1051{ 1052 uint16_t val; 1053 int ret; 1054 1055 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1056 if (ret) 1057 return ret; 1058 1059 val &= ~ADIS16480_DRDY_EN_MSK; 1060 val |= ADIS16480_DRDY_EN(enable); 1061 1062 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val); 1063} 1064 1065static int adis16480_config_irq_pin(struct device_node *of_node, 1066 struct adis16480 *st) 1067{ 1068 struct irq_data *desc; 1069 enum adis16480_int_pin pin; 1070 unsigned int irq_type; 1071 uint16_t val; 1072 int i, irq = 0; 1073 1074 desc = irq_get_irq_data(st->adis.spi->irq); 1075 if (!desc) { 1076 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq); 1077 return -EINVAL; 1078 } 1079 1080 /* Disable data ready since the default after reset is on */ 1081 val = ADIS16480_DRDY_EN(0); 1082 1083 /* 1084 * Get the interrupt from the devicetre by reading the interrupt-names 1085 * property. If it is not specified, use DIO1 pin as default. 1086 * According to the datasheet, the factory default assigns DIO2 as data 1087 * ready signal. However, in the previous versions of the driver, DIO1 1088 * pin was used. So, we should leave it as is since some devices might 1089 * be expecting the interrupt on the wrong physical pin. 1090 */ 1091 pin = ADIS16480_PIN_DIO1; 1092 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1093 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]); 1094 if (irq > 0) { 1095 pin = i; 1096 break; 1097 } 1098 } 1099 1100 val |= ADIS16480_DRDY_SEL(pin); 1101 1102 /* 1103 * Get the interrupt line behaviour. The data ready polarity can be 1104 * configured as positive or negative, corresponding to 1105 * IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING respectively. 1106 */ 1107 irq_type = irqd_get_trigger_type(desc); 1108 if (irq_type == IRQ_TYPE_EDGE_RISING) { /* Default */ 1109 val |= ADIS16480_DRDY_POL(1); 1110 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1111 val |= ADIS16480_DRDY_POL(0); 1112 } else { 1113 dev_err(&st->adis.spi->dev, 1114 "Invalid interrupt type 0x%x specified\n", irq_type); 1115 return -EINVAL; 1116 } 1117 /* Write the data ready configuration to the FNCTIO_CTRL register */ 1118 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1119} 1120 1121static int adis16480_of_get_ext_clk_pin(struct adis16480 *st, 1122 struct device_node *of_node) 1123{ 1124 const char *ext_clk_pin; 1125 enum adis16480_int_pin pin; 1126 int i; 1127 1128 pin = ADIS16480_PIN_DIO2; 1129 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin)) 1130 goto clk_input_not_found; 1131 1132 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) { 1133 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0) 1134 return i; 1135 } 1136 1137clk_input_not_found: 1138 dev_info(&st->adis.spi->dev, 1139 "clk input line not specified, using DIO2\n"); 1140 return pin; 1141} 1142 1143static int adis16480_ext_clk_config(struct adis16480 *st, 1144 struct device_node *of_node, 1145 bool enable) 1146{ 1147 unsigned int mode, mask; 1148 enum adis16480_int_pin pin; 1149 uint16_t val; 1150 int ret; 1151 1152 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val); 1153 if (ret) 1154 return ret; 1155 1156 pin = adis16480_of_get_ext_clk_pin(st, of_node); 1157 /* 1158 * Each DIOx pin supports only one function at a time. When a single pin 1159 * has two assignments, the enable bit for a lower priority function 1160 * automatically resets to zero (disabling the lower priority function). 1161 */ 1162 if (pin == ADIS16480_DRDY_SEL(val)) 1163 dev_warn(&st->adis.spi->dev, 1164 "DIO%x pin supports only one function at a time\n", 1165 pin + 1); 1166 1167 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin); 1168 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; 1169 /* Only ADIS1649x devices support pps ext clock mode */ 1170 if (st->chip_info->has_pps_clk_mode) { 1171 mode |= ADIS16480_SYNC_MODE(st->clk_mode); 1172 mask |= ADIS16480_SYNC_MODE_MSK; 1173 } 1174 1175 val &= ~mask; 1176 val |= mode; 1177 1178 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val); 1179 if (ret) 1180 return ret; 1181 1182 return clk_prepare_enable(st->ext_clk); 1183} 1184 1185static int adis16480_get_ext_clocks(struct adis16480 *st) 1186{ 1187 st->clk_mode = ADIS16480_CLK_INT; 1188 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync"); 1189 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1190 st->clk_mode = ADIS16480_CLK_SYNC; 1191 return 0; 1192 } 1193 1194 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1195 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1196 return PTR_ERR(st->ext_clk); 1197 } 1198 1199 if (st->chip_info->has_pps_clk_mode) { 1200 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps"); 1201 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1202 st->clk_mode = ADIS16480_CLK_PPS; 1203 return 0; 1204 } 1205 1206 if (PTR_ERR(st->ext_clk) != -ENOENT) { 1207 dev_err(&st->adis.spi->dev, "failed to get ext clk\n"); 1208 return PTR_ERR(st->ext_clk); 1209 } 1210 } 1211 1212 return 0; 1213} 1214 1215static void adis16480_stop(void *data) 1216{ 1217 adis16480_stop_device(data); 1218} 1219 1220static void adis16480_clk_disable(void *data) 1221{ 1222 clk_disable_unprepare(data); 1223} 1224 1225static int adis16480_probe(struct spi_device *spi) 1226{ 1227 const struct spi_device_id *id = spi_get_device_id(spi); 1228 const struct adis_data *adis16480_data; 1229 struct iio_dev *indio_dev; 1230 struct adis16480 *st; 1231 int ret; 1232 1233 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1234 if (indio_dev == NULL) 1235 return -ENOMEM; 1236 1237 spi_set_drvdata(spi, indio_dev); 1238 1239 st = iio_priv(indio_dev); 1240 1241 st->chip_info = &adis16480_chip_info[id->driver_data]; 1242 indio_dev->name = spi_get_device_id(spi)->name; 1243 indio_dev->channels = st->chip_info->channels; 1244 indio_dev->num_channels = st->chip_info->num_channels; 1245 indio_dev->info = &adis16480_info; 1246 indio_dev->modes = INDIO_DIRECT_MODE; 1247 1248 adis16480_data = &st->chip_info->adis_data; 1249 1250 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data); 1251 if (ret) 1252 return ret; 1253 1254 ret = __adis_initial_startup(&st->adis); 1255 if (ret) 1256 return ret; 1257 1258 ret = devm_add_action_or_reset(&spi->dev, adis16480_stop, indio_dev); 1259 if (ret) 1260 return ret; 1261 1262 ret = adis16480_config_irq_pin(spi->dev.of_node, st); 1263 if (ret) 1264 return ret; 1265 1266 ret = adis16480_get_ext_clocks(st); 1267 if (ret) 1268 return ret; 1269 1270 if (!IS_ERR_OR_NULL(st->ext_clk)) { 1271 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true); 1272 if (ret) 1273 return ret; 1274 1275 ret = devm_add_action_or_reset(&spi->dev, adis16480_clk_disable, st->ext_clk); 1276 if (ret) 1277 return ret; 1278 1279 st->clk_freq = clk_get_rate(st->ext_clk); 1280 st->clk_freq *= 1000; /* micro */ 1281 } else { 1282 st->clk_freq = st->chip_info->int_clk; 1283 } 1284 1285 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL); 1286 if (ret) 1287 return ret; 1288 1289 ret = devm_iio_device_register(&spi->dev, indio_dev); 1290 if (ret) 1291 return ret; 1292 1293 adis16480_debugfs_init(indio_dev); 1294 1295 return 0; 1296} 1297 1298static const struct spi_device_id adis16480_ids[] = { 1299 { "adis16375", ADIS16375 }, 1300 { "adis16480", ADIS16480 }, 1301 { "adis16485", ADIS16485 }, 1302 { "adis16488", ADIS16488 }, 1303 { "adis16490", ADIS16490 }, 1304 { "adis16495-1", ADIS16495_1 }, 1305 { "adis16495-2", ADIS16495_2 }, 1306 { "adis16495-3", ADIS16495_3 }, 1307 { "adis16497-1", ADIS16497_1 }, 1308 { "adis16497-2", ADIS16497_2 }, 1309 { "adis16497-3", ADIS16497_3 }, 1310 { } 1311}; 1312MODULE_DEVICE_TABLE(spi, adis16480_ids); 1313 1314static const struct of_device_id adis16480_of_match[] = { 1315 { .compatible = "adi,adis16375" }, 1316 { .compatible = "adi,adis16480" }, 1317 { .compatible = "adi,adis16485" }, 1318 { .compatible = "adi,adis16488" }, 1319 { .compatible = "adi,adis16490" }, 1320 { .compatible = "adi,adis16495-1" }, 1321 { .compatible = "adi,adis16495-2" }, 1322 { .compatible = "adi,adis16495-3" }, 1323 { .compatible = "adi,adis16497-1" }, 1324 { .compatible = "adi,adis16497-2" }, 1325 { .compatible = "adi,adis16497-3" }, 1326 { }, 1327}; 1328MODULE_DEVICE_TABLE(of, adis16480_of_match); 1329 1330static struct spi_driver adis16480_driver = { 1331 .driver = { 1332 .name = "adis16480", 1333 .of_match_table = adis16480_of_match, 1334 }, 1335 .id_table = adis16480_ids, 1336 .probe = adis16480_probe, 1337}; 1338module_spi_driver(adis16480_driver); 1339 1340MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1341MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver"); 1342MODULE_LICENSE("GPL v2"); 1343MODULE_IMPORT_NS(IIO_ADISLIB); 1344