1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * MPU3050 gyroscope driver 4 * 5 * Copyright (C) 2016 Linaro Ltd. 6 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * 8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd 9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by 10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c. 11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011. 12 * 13 * TODO: add support for setting up the low pass 3dB frequency. 14 */ 15 16#include <linux/bitops.h> 17#include <linux/delay.h> 18#include <linux/err.h> 19#include <linux/iio/buffer.h> 20#include <linux/iio/iio.h> 21#include <linux/iio/sysfs.h> 22#include <linux/iio/trigger.h> 23#include <linux/iio/trigger_consumer.h> 24#include <linux/iio/triggered_buffer.h> 25#include <linux/interrupt.h> 26#include <linux/module.h> 27#include <linux/pm_runtime.h> 28#include <linux/random.h> 29#include <linux/slab.h> 30 31#include "mpu3050.h" 32 33#define MPU3050_CHIP_ID 0x68 34#define MPU3050_CHIP_ID_MASK 0x7E 35 36/* 37 * Register map: anything suffixed *_H is a big-endian high byte and always 38 * followed by the corresponding low byte (*_L) even though these are not 39 * explicitly included in the register definitions. 40 */ 41#define MPU3050_CHIP_ID_REG 0x00 42#define MPU3050_PRODUCT_ID_REG 0x01 43#define MPU3050_XG_OFFS_TC 0x05 44#define MPU3050_YG_OFFS_TC 0x08 45#define MPU3050_ZG_OFFS_TC 0x0B 46#define MPU3050_X_OFFS_USR_H 0x0C 47#define MPU3050_Y_OFFS_USR_H 0x0E 48#define MPU3050_Z_OFFS_USR_H 0x10 49#define MPU3050_FIFO_EN 0x12 50#define MPU3050_AUX_VDDIO 0x13 51#define MPU3050_SLV_ADDR 0x14 52#define MPU3050_SMPLRT_DIV 0x15 53#define MPU3050_DLPF_FS_SYNC 0x16 54#define MPU3050_INT_CFG 0x17 55#define MPU3050_AUX_ADDR 0x18 56#define MPU3050_INT_STATUS 0x1A 57#define MPU3050_TEMP_H 0x1B 58#define MPU3050_XOUT_H 0x1D 59#define MPU3050_YOUT_H 0x1F 60#define MPU3050_ZOUT_H 0x21 61#define MPU3050_DMP_CFG1 0x35 62#define MPU3050_DMP_CFG2 0x36 63#define MPU3050_BANK_SEL 0x37 64#define MPU3050_MEM_START_ADDR 0x38 65#define MPU3050_MEM_R_W 0x39 66#define MPU3050_FIFO_COUNT_H 0x3A 67#define MPU3050_FIFO_R 0x3C 68#define MPU3050_USR_CTRL 0x3D 69#define MPU3050_PWR_MGM 0x3E 70 71/* MPU memory bank read options */ 72#define MPU3050_MEM_PRFTCH BIT(5) 73#define MPU3050_MEM_USER_BANK BIT(4) 74/* Bits 8-11 select memory bank */ 75#define MPU3050_MEM_RAM_BANK_0 0 76#define MPU3050_MEM_RAM_BANK_1 1 77#define MPU3050_MEM_RAM_BANK_2 2 78#define MPU3050_MEM_RAM_BANK_3 3 79#define MPU3050_MEM_OTP_BANK_0 4 80 81#define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2)) 82 83/* Register bits */ 84 85/* FIFO Enable */ 86#define MPU3050_FIFO_EN_FOOTER BIT(0) 87#define MPU3050_FIFO_EN_AUX_ZOUT BIT(1) 88#define MPU3050_FIFO_EN_AUX_YOUT BIT(2) 89#define MPU3050_FIFO_EN_AUX_XOUT BIT(3) 90#define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4) 91#define MPU3050_FIFO_EN_GYRO_YOUT BIT(5) 92#define MPU3050_FIFO_EN_GYRO_XOUT BIT(6) 93#define MPU3050_FIFO_EN_TEMP_OUT BIT(7) 94 95/* 96 * Digital Low Pass filter (DLPF) 97 * Full Scale (FS) 98 * and Synchronization 99 */ 100#define MPU3050_EXT_SYNC_NONE 0x00 101#define MPU3050_EXT_SYNC_TEMP 0x20 102#define MPU3050_EXT_SYNC_GYROX 0x40 103#define MPU3050_EXT_SYNC_GYROY 0x60 104#define MPU3050_EXT_SYNC_GYROZ 0x80 105#define MPU3050_EXT_SYNC_ACCELX 0xA0 106#define MPU3050_EXT_SYNC_ACCELY 0xC0 107#define MPU3050_EXT_SYNC_ACCELZ 0xE0 108#define MPU3050_EXT_SYNC_MASK 0xE0 109#define MPU3050_EXT_SYNC_SHIFT 5 110 111#define MPU3050_FS_250DPS 0x00 112#define MPU3050_FS_500DPS 0x08 113#define MPU3050_FS_1000DPS 0x10 114#define MPU3050_FS_2000DPS 0x18 115#define MPU3050_FS_MASK 0x18 116#define MPU3050_FS_SHIFT 3 117 118#define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00 119#define MPU3050_DLPF_CFG_188HZ 0x01 120#define MPU3050_DLPF_CFG_98HZ 0x02 121#define MPU3050_DLPF_CFG_42HZ 0x03 122#define MPU3050_DLPF_CFG_20HZ 0x04 123#define MPU3050_DLPF_CFG_10HZ 0x05 124#define MPU3050_DLPF_CFG_5HZ 0x06 125#define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07 126#define MPU3050_DLPF_CFG_MASK 0x07 127#define MPU3050_DLPF_CFG_SHIFT 0 128 129/* Interrupt config */ 130#define MPU3050_INT_RAW_RDY_EN BIT(0) 131#define MPU3050_INT_DMP_DONE_EN BIT(1) 132#define MPU3050_INT_MPU_RDY_EN BIT(2) 133#define MPU3050_INT_ANYRD_2CLEAR BIT(4) 134#define MPU3050_INT_LATCH_EN BIT(5) 135#define MPU3050_INT_OPEN BIT(6) 136#define MPU3050_INT_ACTL BIT(7) 137/* Interrupt status */ 138#define MPU3050_INT_STATUS_RAW_RDY BIT(0) 139#define MPU3050_INT_STATUS_DMP_DONE BIT(1) 140#define MPU3050_INT_STATUS_MPU_RDY BIT(2) 141#define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7) 142/* USR_CTRL */ 143#define MPU3050_USR_CTRL_FIFO_EN BIT(6) 144#define MPU3050_USR_CTRL_AUX_IF_EN BIT(5) 145#define MPU3050_USR_CTRL_AUX_IF_RST BIT(3) 146#define MPU3050_USR_CTRL_FIFO_RST BIT(1) 147#define MPU3050_USR_CTRL_GYRO_RST BIT(0) 148/* PWR_MGM */ 149#define MPU3050_PWR_MGM_PLL_X 0x01 150#define MPU3050_PWR_MGM_PLL_Y 0x02 151#define MPU3050_PWR_MGM_PLL_Z 0x03 152#define MPU3050_PWR_MGM_CLKSEL_MASK 0x07 153#define MPU3050_PWR_MGM_STBY_ZG BIT(3) 154#define MPU3050_PWR_MGM_STBY_YG BIT(4) 155#define MPU3050_PWR_MGM_STBY_XG BIT(5) 156#define MPU3050_PWR_MGM_SLEEP BIT(6) 157#define MPU3050_PWR_MGM_RESET BIT(7) 158#define MPU3050_PWR_MGM_MASK 0xff 159 160/* 161 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full 162 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale, 163 * in two's complement. 164 */ 165static unsigned int mpu3050_fs_precision[] = { 166 IIO_DEGREE_TO_RAD(250), 167 IIO_DEGREE_TO_RAD(500), 168 IIO_DEGREE_TO_RAD(1000), 169 IIO_DEGREE_TO_RAD(2000) 170}; 171 172/* 173 * Regulator names 174 */ 175static const char mpu3050_reg_vdd[] = "vdd"; 176static const char mpu3050_reg_vlogic[] = "vlogic"; 177 178static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050) 179{ 180 unsigned int freq; 181 182 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) 183 freq = 8000; 184 else 185 freq = 1000; 186 freq /= (mpu3050->divisor + 1); 187 188 return freq; 189} 190 191static int mpu3050_start_sampling(struct mpu3050 *mpu3050) 192{ 193 __be16 raw_val[3]; 194 int ret; 195 int i; 196 197 /* Reset */ 198 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 199 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET); 200 if (ret) 201 return ret; 202 203 /* Turn on the Z-axis PLL */ 204 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 205 MPU3050_PWR_MGM_CLKSEL_MASK, 206 MPU3050_PWR_MGM_PLL_Z); 207 if (ret) 208 return ret; 209 210 /* Write calibration offset registers */ 211 for (i = 0; i < 3; i++) 212 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); 213 214 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val, 215 sizeof(raw_val)); 216 if (ret) 217 return ret; 218 219 /* Set low pass filter (sample rate), sync and full scale */ 220 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC, 221 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT | 222 mpu3050->fullscale << MPU3050_FS_SHIFT | 223 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT); 224 if (ret) 225 return ret; 226 227 /* Set up sampling frequency */ 228 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor); 229 if (ret) 230 return ret; 231 232 /* 233 * Max 50 ms start-up time after setting DLPF_FS_SYNC 234 * according to the data sheet, then wait for the next sample 235 * at this frequency T = 1000/f ms. 236 */ 237 msleep(50 + 1000 / mpu3050_get_freq(mpu3050)); 238 239 return 0; 240} 241 242static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050) 243{ 244 int ret; 245 u8 divisor; 246 enum mpu3050_lpf lpf; 247 248 lpf = mpu3050->lpf; 249 divisor = mpu3050->divisor; 250 251 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */ 252 mpu3050->divisor = 0; /* Divide by 1 */ 253 ret = mpu3050_start_sampling(mpu3050); 254 255 mpu3050->lpf = lpf; 256 mpu3050->divisor = divisor; 257 258 return ret; 259} 260 261static int mpu3050_read_raw(struct iio_dev *indio_dev, 262 struct iio_chan_spec const *chan, 263 int *val, int *val2, 264 long mask) 265{ 266 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 267 int ret; 268 __be16 raw_val; 269 270 switch (mask) { 271 case IIO_CHAN_INFO_OFFSET: 272 switch (chan->type) { 273 case IIO_TEMP: 274 /* 275 * The temperature scaling is (x+23000)/280 Celsius 276 * for the "best fit straight line" temperature range 277 * of -30C..85C. The 23000 includes room temperature 278 * offset of +35C, 280 is the precision scale and x is 279 * the 16-bit signed integer reported by hardware. 280 * 281 * Temperature value itself represents temperature of 282 * the sensor die. 283 */ 284 *val = 23000; 285 return IIO_VAL_INT; 286 default: 287 return -EINVAL; 288 } 289 case IIO_CHAN_INFO_CALIBBIAS: 290 switch (chan->type) { 291 case IIO_ANGL_VEL: 292 *val = mpu3050->calibration[chan->scan_index-1]; 293 return IIO_VAL_INT; 294 default: 295 return -EINVAL; 296 } 297 case IIO_CHAN_INFO_SAMP_FREQ: 298 *val = mpu3050_get_freq(mpu3050); 299 return IIO_VAL_INT; 300 case IIO_CHAN_INFO_SCALE: 301 switch (chan->type) { 302 case IIO_TEMP: 303 /* Millidegrees, see about temperature scaling above */ 304 *val = 1000; 305 *val2 = 280; 306 return IIO_VAL_FRACTIONAL; 307 case IIO_ANGL_VEL: 308 /* 309 * Convert to the corresponding full scale in 310 * radians. All 16 bits are used with sign to 311 * span the available scale: to account for the one 312 * missing value if we multiply by 1/S16_MAX, instead 313 * multiply with 2/U16_MAX. 314 */ 315 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2; 316 *val2 = U16_MAX; 317 return IIO_VAL_FRACTIONAL; 318 default: 319 return -EINVAL; 320 } 321 case IIO_CHAN_INFO_RAW: 322 /* Resume device */ 323 pm_runtime_get_sync(mpu3050->dev); 324 mutex_lock(&mpu3050->lock); 325 326 ret = mpu3050_set_8khz_samplerate(mpu3050); 327 if (ret) 328 goto out_read_raw_unlock; 329 330 switch (chan->type) { 331 case IIO_TEMP: 332 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, 333 &raw_val, sizeof(raw_val)); 334 if (ret) { 335 dev_err(mpu3050->dev, 336 "error reading temperature\n"); 337 goto out_read_raw_unlock; 338 } 339 340 *val = (s16)be16_to_cpu(raw_val); 341 ret = IIO_VAL_INT; 342 343 goto out_read_raw_unlock; 344 case IIO_ANGL_VEL: 345 ret = regmap_bulk_read(mpu3050->map, 346 MPU3050_AXIS_REGS(chan->scan_index-1), 347 &raw_val, 348 sizeof(raw_val)); 349 if (ret) { 350 dev_err(mpu3050->dev, 351 "error reading axis data\n"); 352 goto out_read_raw_unlock; 353 } 354 355 *val = be16_to_cpu(raw_val); 356 ret = IIO_VAL_INT; 357 358 goto out_read_raw_unlock; 359 default: 360 ret = -EINVAL; 361 goto out_read_raw_unlock; 362 } 363 default: 364 break; 365 } 366 367 return -EINVAL; 368 369out_read_raw_unlock: 370 mutex_unlock(&mpu3050->lock); 371 pm_runtime_mark_last_busy(mpu3050->dev); 372 pm_runtime_put_autosuspend(mpu3050->dev); 373 374 return ret; 375} 376 377static int mpu3050_write_raw(struct iio_dev *indio_dev, 378 const struct iio_chan_spec *chan, 379 int val, int val2, long mask) 380{ 381 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 382 /* 383 * Couldn't figure out a way to precalculate these at compile time. 384 */ 385 unsigned int fs250 = 386 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2, 387 U16_MAX); 388 unsigned int fs500 = 389 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2, 390 U16_MAX); 391 unsigned int fs1000 = 392 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2, 393 U16_MAX); 394 unsigned int fs2000 = 395 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2, 396 U16_MAX); 397 398 switch (mask) { 399 case IIO_CHAN_INFO_CALIBBIAS: 400 if (chan->type != IIO_ANGL_VEL) 401 return -EINVAL; 402 mpu3050->calibration[chan->scan_index-1] = val; 403 return 0; 404 case IIO_CHAN_INFO_SAMP_FREQ: 405 /* 406 * The max samplerate is 8000 Hz, the minimum 407 * 1000 / 256 ~= 4 Hz 408 */ 409 if (val < 4 || val > 8000) 410 return -EINVAL; 411 412 /* 413 * Above 1000 Hz we must turn off the digital low pass filter 414 * so we get a base frequency of 8kHz to the divider 415 */ 416 if (val > 1000) { 417 mpu3050->lpf = LPF_256_HZ_NOLPF; 418 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1; 419 return 0; 420 } 421 422 mpu3050->lpf = LPF_188_HZ; 423 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1; 424 return 0; 425 case IIO_CHAN_INFO_SCALE: 426 if (chan->type != IIO_ANGL_VEL) 427 return -EINVAL; 428 /* 429 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s 430 * which means we need to round to the closest radians 431 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35 432 * rad/s. The scale is then for the 16 bits used to cover 433 * it 2/(2^16) of that. 434 */ 435 436 /* Just too large, set the max range */ 437 if (val != 0) { 438 mpu3050->fullscale = FS_2000_DPS; 439 return 0; 440 } 441 442 /* 443 * Now we're dealing with fractions below zero in millirad/s 444 * do some integer interpolation and match with the closest 445 * fullscale in the table. 446 */ 447 if (val2 <= fs250 || 448 val2 < ((fs500 + fs250) / 2)) 449 mpu3050->fullscale = FS_250_DPS; 450 else if (val2 <= fs500 || 451 val2 < ((fs1000 + fs500) / 2)) 452 mpu3050->fullscale = FS_500_DPS; 453 else if (val2 <= fs1000 || 454 val2 < ((fs2000 + fs1000) / 2)) 455 mpu3050->fullscale = FS_1000_DPS; 456 else 457 /* Catch-all */ 458 mpu3050->fullscale = FS_2000_DPS; 459 return 0; 460 default: 461 break; 462 } 463 464 return -EINVAL; 465} 466 467static irqreturn_t mpu3050_trigger_handler(int irq, void *p) 468{ 469 const struct iio_poll_func *pf = p; 470 struct iio_dev *indio_dev = pf->indio_dev; 471 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 472 int ret; 473 /* 474 * Temperature 1*16 bits 475 * Three axes 3*16 bits 476 * Timestamp 64 bits (4*16 bits) 477 * Sum total 8*16 bits 478 */ 479 __be16 hw_values[8]; 480 s64 timestamp; 481 unsigned int datums_from_fifo = 0; 482 483 /* 484 * If we're using the hardware trigger, get the precise timestamp from 485 * the top half of the threaded IRQ handler. Otherwise get the 486 * timestamp here so it will be close in time to the actual values 487 * read from the registers. 488 */ 489 if (iio_trigger_using_own(indio_dev)) 490 timestamp = mpu3050->hw_timestamp; 491 else 492 timestamp = iio_get_time_ns(indio_dev); 493 494 mutex_lock(&mpu3050->lock); 495 496 /* Using the hardware IRQ trigger? Check the buffer then. */ 497 if (mpu3050->hw_irq_trigger) { 498 __be16 raw_fifocnt; 499 u16 fifocnt; 500 /* X, Y, Z + temperature */ 501 unsigned int bytes_per_datum = 8; 502 bool fifo_overflow = false; 503 504 ret = regmap_bulk_read(mpu3050->map, 505 MPU3050_FIFO_COUNT_H, 506 &raw_fifocnt, 507 sizeof(raw_fifocnt)); 508 if (ret) 509 goto out_trigger_unlock; 510 fifocnt = be16_to_cpu(raw_fifocnt); 511 512 if (fifocnt == 512) { 513 dev_info(mpu3050->dev, 514 "FIFO overflow! Emptying and resetting FIFO\n"); 515 fifo_overflow = true; 516 /* Reset and enable the FIFO */ 517 ret = regmap_update_bits(mpu3050->map, 518 MPU3050_USR_CTRL, 519 MPU3050_USR_CTRL_FIFO_EN | 520 MPU3050_USR_CTRL_FIFO_RST, 521 MPU3050_USR_CTRL_FIFO_EN | 522 MPU3050_USR_CTRL_FIFO_RST); 523 if (ret) { 524 dev_info(mpu3050->dev, "error resetting FIFO\n"); 525 goto out_trigger_unlock; 526 } 527 mpu3050->pending_fifo_footer = false; 528 } 529 530 if (fifocnt) 531 dev_dbg(mpu3050->dev, 532 "%d bytes in the FIFO\n", 533 fifocnt); 534 535 while (!fifo_overflow && fifocnt > bytes_per_datum) { 536 unsigned int toread; 537 unsigned int offset; 538 __be16 fifo_values[5]; 539 540 /* 541 * If there is a FIFO footer in the pipe, first clear 542 * that out. This follows the complex algorithm in the 543 * datasheet that states that you may never leave the 544 * FIFO empty after the first reading: you have to 545 * always leave two footer bytes in it. The footer is 546 * in practice just two zero bytes. 547 */ 548 if (mpu3050->pending_fifo_footer) { 549 toread = bytes_per_datum + 2; 550 offset = 0; 551 } else { 552 toread = bytes_per_datum; 553 offset = 1; 554 /* Put in some dummy value */ 555 fifo_values[0] = cpu_to_be16(0xAAAA); 556 } 557 558 ret = regmap_bulk_read(mpu3050->map, 559 MPU3050_FIFO_R, 560 &fifo_values[offset], 561 toread); 562 if (ret) 563 goto out_trigger_unlock; 564 565 dev_dbg(mpu3050->dev, 566 "%04x %04x %04x %04x %04x\n", 567 fifo_values[0], 568 fifo_values[1], 569 fifo_values[2], 570 fifo_values[3], 571 fifo_values[4]); 572 573 /* Index past the footer (fifo_values[0]) and push */ 574 iio_push_to_buffers_with_timestamp(indio_dev, 575 &fifo_values[1], 576 timestamp); 577 578 fifocnt -= toread; 579 datums_from_fifo++; 580 mpu3050->pending_fifo_footer = true; 581 582 /* 583 * If we're emptying the FIFO, just make sure to 584 * check if something new appeared. 585 */ 586 if (fifocnt < bytes_per_datum) { 587 ret = regmap_bulk_read(mpu3050->map, 588 MPU3050_FIFO_COUNT_H, 589 &raw_fifocnt, 590 sizeof(raw_fifocnt)); 591 if (ret) 592 goto out_trigger_unlock; 593 fifocnt = be16_to_cpu(raw_fifocnt); 594 } 595 596 if (fifocnt < bytes_per_datum) 597 dev_dbg(mpu3050->dev, 598 "%d bytes left in the FIFO\n", 599 fifocnt); 600 601 /* 602 * At this point, the timestamp that triggered the 603 * hardware interrupt is no longer valid for what 604 * we are reading (the interrupt likely fired for 605 * the value on the top of the FIFO), so set the 606 * timestamp to zero and let userspace deal with it. 607 */ 608 timestamp = 0; 609 } 610 } 611 612 /* 613 * If we picked some datums from the FIFO that's enough, else 614 * fall through and just read from the current value registers. 615 * This happens in two cases: 616 * 617 * - We are using some other trigger (external, like an HRTimer) 618 * than the sensor's own sample generator. In this case the 619 * sensor is just set to the max sampling frequency and we give 620 * the trigger a copy of the latest value every time we get here. 621 * 622 * - The hardware trigger is active but unused and we actually use 623 * another trigger which calls here with a frequency higher 624 * than what the device provides data. We will then just read 625 * duplicate values directly from the hardware registers. 626 */ 627 if (datums_from_fifo) { 628 dev_dbg(mpu3050->dev, 629 "read %d datums from the FIFO\n", 630 datums_from_fifo); 631 goto out_trigger_unlock; 632 } 633 634 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values, 635 sizeof(hw_values)); 636 if (ret) { 637 dev_err(mpu3050->dev, 638 "error reading axis data\n"); 639 goto out_trigger_unlock; 640 } 641 642 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp); 643 644out_trigger_unlock: 645 mutex_unlock(&mpu3050->lock); 646 iio_trigger_notify_done(indio_dev->trig); 647 648 return IRQ_HANDLED; 649} 650 651static int mpu3050_buffer_preenable(struct iio_dev *indio_dev) 652{ 653 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 654 655 pm_runtime_get_sync(mpu3050->dev); 656 657 /* Unless we have OUR trigger active, run at full speed */ 658 if (!mpu3050->hw_irq_trigger) 659 return mpu3050_set_8khz_samplerate(mpu3050); 660 661 return 0; 662} 663 664static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev) 665{ 666 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 667 668 pm_runtime_mark_last_busy(mpu3050->dev); 669 pm_runtime_put_autosuspend(mpu3050->dev); 670 671 return 0; 672} 673 674static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = { 675 .preenable = mpu3050_buffer_preenable, 676 .postdisable = mpu3050_buffer_postdisable, 677}; 678 679static const struct iio_mount_matrix * 680mpu3050_get_mount_matrix(const struct iio_dev *indio_dev, 681 const struct iio_chan_spec *chan) 682{ 683 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 684 685 return &mpu3050->orientation; 686} 687 688static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = { 689 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix), 690 { }, 691}; 692 693#define MPU3050_AXIS_CHANNEL(axis, index) \ 694 { \ 695 .type = IIO_ANGL_VEL, \ 696 .modified = 1, \ 697 .channel2 = IIO_MOD_##axis, \ 698 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 699 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 700 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 701 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 702 .ext_info = mpu3050_ext_info, \ 703 .scan_index = index, \ 704 .scan_type = { \ 705 .sign = 's', \ 706 .realbits = 16, \ 707 .storagebits = 16, \ 708 .endianness = IIO_BE, \ 709 }, \ 710 } 711 712static const struct iio_chan_spec mpu3050_channels[] = { 713 { 714 .type = IIO_TEMP, 715 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 716 BIT(IIO_CHAN_INFO_SCALE) | 717 BIT(IIO_CHAN_INFO_OFFSET), 718 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 719 .scan_index = 0, 720 .scan_type = { 721 .sign = 's', 722 .realbits = 16, 723 .storagebits = 16, 724 .endianness = IIO_BE, 725 }, 726 }, 727 MPU3050_AXIS_CHANNEL(X, 1), 728 MPU3050_AXIS_CHANNEL(Y, 2), 729 MPU3050_AXIS_CHANNEL(Z, 3), 730 IIO_CHAN_SOFT_TIMESTAMP(4), 731}; 732 733/* Four channels apart from timestamp, scan mask = 0x0f */ 734static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 }; 735 736/* 737 * These are just the hardcoded factors resulting from the more elaborate 738 * calculations done with fractions in the scale raw get/set functions. 739 */ 740static IIO_CONST_ATTR(anglevel_scale_available, 741 "0.000122070 " 742 "0.000274658 " 743 "0.000518798 " 744 "0.001068115"); 745 746static struct attribute *mpu3050_attributes[] = { 747 &iio_const_attr_anglevel_scale_available.dev_attr.attr, 748 NULL, 749}; 750 751static const struct attribute_group mpu3050_attribute_group = { 752 .attrs = mpu3050_attributes, 753}; 754 755static const struct iio_info mpu3050_info = { 756 .read_raw = mpu3050_read_raw, 757 .write_raw = mpu3050_write_raw, 758 .attrs = &mpu3050_attribute_group, 759}; 760 761/** 762 * mpu3050_read_mem() - read MPU-3050 internal memory 763 * @mpu3050: device to read from 764 * @bank: target bank 765 * @addr: target address 766 * @len: number of bytes 767 * @buf: the buffer to store the read bytes in 768 */ 769static int mpu3050_read_mem(struct mpu3050 *mpu3050, 770 u8 bank, 771 u8 addr, 772 u8 len, 773 u8 *buf) 774{ 775 int ret; 776 777 ret = regmap_write(mpu3050->map, 778 MPU3050_BANK_SEL, 779 bank); 780 if (ret) 781 return ret; 782 783 ret = regmap_write(mpu3050->map, 784 MPU3050_MEM_START_ADDR, 785 addr); 786 if (ret) 787 return ret; 788 789 return regmap_bulk_read(mpu3050->map, 790 MPU3050_MEM_R_W, 791 buf, 792 len); 793} 794 795static int mpu3050_hw_init(struct mpu3050 *mpu3050) 796{ 797 int ret; 798 u8 otp[8]; 799 800 /* Reset */ 801 ret = regmap_update_bits(mpu3050->map, 802 MPU3050_PWR_MGM, 803 MPU3050_PWR_MGM_RESET, 804 MPU3050_PWR_MGM_RESET); 805 if (ret) 806 return ret; 807 808 /* Turn on the PLL */ 809 ret = regmap_update_bits(mpu3050->map, 810 MPU3050_PWR_MGM, 811 MPU3050_PWR_MGM_CLKSEL_MASK, 812 MPU3050_PWR_MGM_PLL_Z); 813 if (ret) 814 return ret; 815 816 /* Disable IRQs */ 817 ret = regmap_write(mpu3050->map, 818 MPU3050_INT_CFG, 819 0); 820 if (ret) 821 return ret; 822 823 /* Read out the 8 bytes of OTP (one-time-programmable) memory */ 824 ret = mpu3050_read_mem(mpu3050, 825 (MPU3050_MEM_PRFTCH | 826 MPU3050_MEM_USER_BANK | 827 MPU3050_MEM_OTP_BANK_0), 828 0, 829 sizeof(otp), 830 otp); 831 if (ret) 832 return ret; 833 834 /* This is device-unique data so it goes into the entropy pool */ 835 add_device_randomness(otp, sizeof(otp)); 836 837 dev_info(mpu3050->dev, 838 "die ID: %04X, wafer ID: %02X, A lot ID: %04X, " 839 "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n", 840 /* Die ID, bits 0-12 */ 841 (otp[1] << 8 | otp[0]) & 0x1fff, 842 /* Wafer ID, bits 13-17 */ 843 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5, 844 /* A lot ID, bits 18-33 */ 845 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2, 846 /* W lot ID, bits 34-45 */ 847 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2, 848 /* WP ID, bits 47-49 */ 849 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7, 850 /* rev ID, bits 50-55 */ 851 otp[6] >> 2); 852 853 return 0; 854} 855 856static int mpu3050_power_up(struct mpu3050 *mpu3050) 857{ 858 int ret; 859 860 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 861 if (ret) { 862 dev_err(mpu3050->dev, "cannot enable regulators\n"); 863 return ret; 864 } 865 /* 866 * 20-100 ms start-up time for register read/write according to 867 * the datasheet, be on the safe side and wait 200 ms. 868 */ 869 msleep(200); 870 871 /* Take device out of sleep mode */ 872 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 873 MPU3050_PWR_MGM_SLEEP, 0); 874 if (ret) { 875 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 876 dev_err(mpu3050->dev, "error setting power mode\n"); 877 return ret; 878 } 879 usleep_range(10000, 20000); 880 881 return 0; 882} 883 884static int mpu3050_power_down(struct mpu3050 *mpu3050) 885{ 886 int ret; 887 888 /* 889 * Put MPU-3050 into sleep mode before cutting regulators. 890 * This is important, because we may not be the sole user 891 * of the regulator so the power may stay on after this, and 892 * then we would be wasting power unless we go to sleep mode 893 * first. 894 */ 895 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, 896 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP); 897 if (ret) 898 dev_err(mpu3050->dev, "error putting to sleep\n"); 899 900 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs); 901 if (ret) 902 dev_err(mpu3050->dev, "error disabling regulators\n"); 903 904 return 0; 905} 906 907static irqreturn_t mpu3050_irq_handler(int irq, void *p) 908{ 909 struct iio_trigger *trig = p; 910 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 911 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 912 913 if (!mpu3050->hw_irq_trigger) 914 return IRQ_NONE; 915 916 /* Get the time stamp as close in time as possible */ 917 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev); 918 919 return IRQ_WAKE_THREAD; 920} 921 922static irqreturn_t mpu3050_irq_thread(int irq, void *p) 923{ 924 struct iio_trigger *trig = p; 925 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 926 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 927 unsigned int val; 928 int ret; 929 930 /* ACK IRQ and check if it was from us */ 931 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 932 if (ret) { 933 dev_err(mpu3050->dev, "error reading IRQ status\n"); 934 return IRQ_HANDLED; 935 } 936 if (!(val & MPU3050_INT_STATUS_RAW_RDY)) 937 return IRQ_NONE; 938 939 iio_trigger_poll_chained(p); 940 941 return IRQ_HANDLED; 942} 943 944/** 945 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state 946 * @trig: trigger instance 947 * @enable: true if trigger should be enabled, false to disable 948 */ 949static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig, 950 bool enable) 951{ 952 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 953 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 954 unsigned int val; 955 int ret; 956 957 /* Disabling trigger: disable interrupt and return */ 958 if (!enable) { 959 /* Disable all interrupts */ 960 ret = regmap_write(mpu3050->map, 961 MPU3050_INT_CFG, 962 0); 963 if (ret) 964 dev_err(mpu3050->dev, "error disabling IRQ\n"); 965 966 /* Clear IRQ flag */ 967 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 968 if (ret) 969 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 970 971 /* Disable all things in the FIFO and reset it */ 972 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 973 if (ret) 974 dev_err(mpu3050->dev, "error disabling FIFO\n"); 975 976 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL, 977 MPU3050_USR_CTRL_FIFO_RST); 978 if (ret) 979 dev_err(mpu3050->dev, "error resetting FIFO\n"); 980 981 pm_runtime_mark_last_busy(mpu3050->dev); 982 pm_runtime_put_autosuspend(mpu3050->dev); 983 mpu3050->hw_irq_trigger = false; 984 985 return 0; 986 } else { 987 /* Else we're enabling the trigger from this point */ 988 pm_runtime_get_sync(mpu3050->dev); 989 mpu3050->hw_irq_trigger = true; 990 991 /* Disable all things in the FIFO */ 992 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0); 993 if (ret) 994 return ret; 995 996 /* Reset and enable the FIFO */ 997 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL, 998 MPU3050_USR_CTRL_FIFO_EN | 999 MPU3050_USR_CTRL_FIFO_RST, 1000 MPU3050_USR_CTRL_FIFO_EN | 1001 MPU3050_USR_CTRL_FIFO_RST); 1002 if (ret) 1003 return ret; 1004 1005 mpu3050->pending_fifo_footer = false; 1006 1007 /* Turn on the FIFO for temp+X+Y+Z */ 1008 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 1009 MPU3050_FIFO_EN_TEMP_OUT | 1010 MPU3050_FIFO_EN_GYRO_XOUT | 1011 MPU3050_FIFO_EN_GYRO_YOUT | 1012 MPU3050_FIFO_EN_GYRO_ZOUT | 1013 MPU3050_FIFO_EN_FOOTER); 1014 if (ret) 1015 return ret; 1016 1017 /* Configure the sample engine */ 1018 ret = mpu3050_start_sampling(mpu3050); 1019 if (ret) 1020 return ret; 1021 1022 /* Clear IRQ flag */ 1023 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val); 1024 if (ret) 1025 dev_err(mpu3050->dev, "error clearing IRQ status\n"); 1026 1027 /* Give us interrupts whenever there is new data ready */ 1028 val = MPU3050_INT_RAW_RDY_EN; 1029 1030 if (mpu3050->irq_actl) 1031 val |= MPU3050_INT_ACTL; 1032 if (mpu3050->irq_latch) 1033 val |= MPU3050_INT_LATCH_EN; 1034 if (mpu3050->irq_opendrain) 1035 val |= MPU3050_INT_OPEN; 1036 1037 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val); 1038 if (ret) 1039 return ret; 1040 } 1041 1042 return 0; 1043} 1044 1045static const struct iio_trigger_ops mpu3050_trigger_ops = { 1046 .set_trigger_state = mpu3050_drdy_trigger_set_state, 1047}; 1048 1049static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq) 1050{ 1051 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1052 unsigned long irq_trig; 1053 int ret; 1054 1055 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev, 1056 "%s-dev%d", 1057 indio_dev->name, 1058 indio_dev->id); 1059 if (!mpu3050->trig) 1060 return -ENOMEM; 1061 1062 /* Check if IRQ is open drain */ 1063 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain")) 1064 mpu3050->irq_opendrain = true; 1065 1066 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1067 /* 1068 * Configure the interrupt generator hardware to supply whatever 1069 * the interrupt is configured for, edges low/high level low/high, 1070 * we can provide it all. 1071 */ 1072 switch (irq_trig) { 1073 case IRQF_TRIGGER_RISING: 1074 dev_info(&indio_dev->dev, 1075 "pulse interrupts on the rising edge\n"); 1076 break; 1077 case IRQF_TRIGGER_FALLING: 1078 mpu3050->irq_actl = true; 1079 dev_info(&indio_dev->dev, 1080 "pulse interrupts on the falling edge\n"); 1081 break; 1082 case IRQF_TRIGGER_HIGH: 1083 mpu3050->irq_latch = true; 1084 dev_info(&indio_dev->dev, 1085 "interrupts active high level\n"); 1086 /* 1087 * With level IRQs, we mask the IRQ until it is processed, 1088 * but with edge IRQs (pulses) we can queue several interrupts 1089 * in the top half. 1090 */ 1091 irq_trig |= IRQF_ONESHOT; 1092 break; 1093 case IRQF_TRIGGER_LOW: 1094 mpu3050->irq_latch = true; 1095 mpu3050->irq_actl = true; 1096 irq_trig |= IRQF_ONESHOT; 1097 dev_info(&indio_dev->dev, 1098 "interrupts active low level\n"); 1099 break; 1100 default: 1101 /* This is the most preferred mode, if possible */ 1102 dev_err(&indio_dev->dev, 1103 "unsupported IRQ trigger specified (%lx), enforce " 1104 "rising edge\n", irq_trig); 1105 irq_trig = IRQF_TRIGGER_RISING; 1106 break; 1107 } 1108 1109 /* An open drain line can be shared with several devices */ 1110 if (mpu3050->irq_opendrain) 1111 irq_trig |= IRQF_SHARED; 1112 1113 ret = request_threaded_irq(irq, 1114 mpu3050_irq_handler, 1115 mpu3050_irq_thread, 1116 irq_trig, 1117 mpu3050->trig->name, 1118 mpu3050->trig); 1119 if (ret) { 1120 dev_err(mpu3050->dev, 1121 "can't get IRQ %d, error %d\n", irq, ret); 1122 return ret; 1123 } 1124 1125 mpu3050->irq = irq; 1126 mpu3050->trig->dev.parent = mpu3050->dev; 1127 mpu3050->trig->ops = &mpu3050_trigger_ops; 1128 iio_trigger_set_drvdata(mpu3050->trig, indio_dev); 1129 1130 ret = iio_trigger_register(mpu3050->trig); 1131 if (ret) 1132 return ret; 1133 1134 indio_dev->trig = iio_trigger_get(mpu3050->trig); 1135 1136 return 0; 1137} 1138 1139int mpu3050_common_probe(struct device *dev, 1140 struct regmap *map, 1141 int irq, 1142 const char *name) 1143{ 1144 struct iio_dev *indio_dev; 1145 struct mpu3050 *mpu3050; 1146 unsigned int val; 1147 int ret; 1148 1149 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050)); 1150 if (!indio_dev) 1151 return -ENOMEM; 1152 mpu3050 = iio_priv(indio_dev); 1153 1154 mpu3050->dev = dev; 1155 mpu3050->map = map; 1156 mutex_init(&mpu3050->lock); 1157 /* Default fullscale: 2000 degrees per second */ 1158 mpu3050->fullscale = FS_2000_DPS; 1159 /* 1 kHz, divide by 100, default frequency = 10 Hz */ 1160 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ; 1161 mpu3050->divisor = 99; 1162 1163 /* Read the mounting matrix, if present */ 1164 ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation); 1165 if (ret) 1166 return ret; 1167 1168 /* Fetch and turn on regulators */ 1169 mpu3050->regs[0].supply = mpu3050_reg_vdd; 1170 mpu3050->regs[1].supply = mpu3050_reg_vlogic; 1171 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs), 1172 mpu3050->regs); 1173 if (ret) { 1174 dev_err(dev, "Cannot get regulators\n"); 1175 return ret; 1176 } 1177 1178 ret = mpu3050_power_up(mpu3050); 1179 if (ret) 1180 return ret; 1181 1182 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val); 1183 if (ret) { 1184 dev_err(dev, "could not read device ID\n"); 1185 ret = -ENODEV; 1186 1187 goto err_power_down; 1188 } 1189 1190 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) { 1191 dev_err(dev, "unsupported chip id %02x\n", 1192 (u8)(val & MPU3050_CHIP_ID_MASK)); 1193 ret = -ENODEV; 1194 goto err_power_down; 1195 } 1196 1197 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val); 1198 if (ret) { 1199 dev_err(dev, "could not read device ID\n"); 1200 ret = -ENODEV; 1201 1202 goto err_power_down; 1203 } 1204 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n", 1205 ((val >> 4) & 0xf), (val & 0xf)); 1206 1207 ret = mpu3050_hw_init(mpu3050); 1208 if (ret) 1209 goto err_power_down; 1210 1211 indio_dev->channels = mpu3050_channels; 1212 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels); 1213 indio_dev->info = &mpu3050_info; 1214 indio_dev->available_scan_masks = mpu3050_scan_masks; 1215 indio_dev->modes = INDIO_DIRECT_MODE; 1216 indio_dev->name = name; 1217 1218 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time, 1219 mpu3050_trigger_handler, 1220 &mpu3050_buffer_setup_ops); 1221 if (ret) { 1222 dev_err(dev, "triggered buffer setup failed\n"); 1223 goto err_power_down; 1224 } 1225 1226 ret = iio_device_register(indio_dev); 1227 if (ret) { 1228 dev_err(dev, "device register failed\n"); 1229 goto err_cleanup_buffer; 1230 } 1231 1232 dev_set_drvdata(dev, indio_dev); 1233 1234 /* Check if we have an assigned IRQ to use as trigger */ 1235 if (irq) { 1236 ret = mpu3050_trigger_probe(indio_dev, irq); 1237 if (ret) 1238 dev_err(dev, "failed to register trigger\n"); 1239 } 1240 1241 /* Enable runtime PM */ 1242 pm_runtime_get_noresume(dev); 1243 pm_runtime_set_active(dev); 1244 pm_runtime_enable(dev); 1245 /* 1246 * Set autosuspend to two orders of magnitude larger than the 1247 * start-up time. 100ms start-up time means 10000ms autosuspend, 1248 * i.e. 10 seconds. 1249 */ 1250 pm_runtime_set_autosuspend_delay(dev, 10000); 1251 pm_runtime_use_autosuspend(dev); 1252 pm_runtime_put(dev); 1253 1254 return 0; 1255 1256err_cleanup_buffer: 1257 iio_triggered_buffer_cleanup(indio_dev); 1258err_power_down: 1259 mpu3050_power_down(mpu3050); 1260 1261 return ret; 1262} 1263EXPORT_SYMBOL(mpu3050_common_probe); 1264 1265int mpu3050_common_remove(struct device *dev) 1266{ 1267 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1268 struct mpu3050 *mpu3050 = iio_priv(indio_dev); 1269 1270 pm_runtime_get_sync(dev); 1271 pm_runtime_put_noidle(dev); 1272 pm_runtime_disable(dev); 1273 iio_triggered_buffer_cleanup(indio_dev); 1274 if (mpu3050->irq) 1275 free_irq(mpu3050->irq, mpu3050); 1276 iio_device_unregister(indio_dev); 1277 mpu3050_power_down(mpu3050); 1278 1279 return 0; 1280} 1281EXPORT_SYMBOL(mpu3050_common_remove); 1282 1283#ifdef CONFIG_PM 1284static int mpu3050_runtime_suspend(struct device *dev) 1285{ 1286 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev))); 1287} 1288 1289static int mpu3050_runtime_resume(struct device *dev) 1290{ 1291 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev))); 1292} 1293#endif /* CONFIG_PM */ 1294 1295const struct dev_pm_ops mpu3050_dev_pm_ops = { 1296 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1297 pm_runtime_force_resume) 1298 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend, 1299 mpu3050_runtime_resume, NULL) 1300}; 1301EXPORT_SYMBOL(mpu3050_dev_pm_ops); 1302 1303MODULE_AUTHOR("Linus Walleij"); 1304MODULE_DESCRIPTION("MPU3050 gyroscope driver"); 1305MODULE_LICENSE("GPL"); 1306