1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is part of STM32 DAC driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Authors: Amelie Delaunay <amelie.delaunay@st.com>
7 *	    Fabrice Gasnier <fabrice.gasnier@st.com>
8 */
9
10#include <linux/bitfield.h>
11#include <linux/delay.h>
12#include <linux/iio/iio.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17
18#include "stm32-dac-core.h"
19
20#define STM32_DAC_CHANNEL_1		1
21#define STM32_DAC_CHANNEL_2		2
22#define STM32_DAC_IS_CHAN_1(ch)		((ch) & STM32_DAC_CHANNEL_1)
23
24#define STM32_DAC_AUTO_SUSPEND_DELAY_MS	2000
25
26/**
27 * struct stm32_dac - private data of DAC driver
28 * @common:		reference to DAC common data
29 * @lock:		lock to protect against potential races when reading
30 *			and update CR, to keep it in sync with pm_runtime
31 */
32struct stm32_dac {
33	struct stm32_dac_common *common;
34	struct mutex		lock;
35};
36
37static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
38{
39	struct stm32_dac *dac = iio_priv(indio_dev);
40	u32 en, val;
41	int ret;
42
43	ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
44	if (ret < 0)
45		return ret;
46	if (STM32_DAC_IS_CHAN_1(channel))
47		en = FIELD_GET(STM32_DAC_CR_EN1, val);
48	else
49		en = FIELD_GET(STM32_DAC_CR_EN2, val);
50
51	return !!en;
52}
53
54static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
55				      bool enable)
56{
57	struct stm32_dac *dac = iio_priv(indio_dev);
58	struct device *dev = indio_dev->dev.parent;
59	u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
60	u32 en = enable ? msk : 0;
61	int ret;
62
63	/* already enabled / disabled ? */
64	mutex_lock(&dac->lock);
65	ret = stm32_dac_is_enabled(indio_dev, ch);
66	if (ret < 0 || enable == !!ret) {
67		mutex_unlock(&dac->lock);
68		return ret < 0 ? ret : 0;
69	}
70
71	if (enable) {
72		ret = pm_runtime_get_sync(dev);
73		if (ret < 0) {
74			pm_runtime_put_noidle(dev);
75			mutex_unlock(&dac->lock);
76			return ret;
77		}
78	}
79
80	ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
81	mutex_unlock(&dac->lock);
82	if (ret < 0) {
83		dev_err(&indio_dev->dev, "%s failed\n", en ?
84			"Enable" : "Disable");
85		goto err_put_pm;
86	}
87
88	/*
89	 * When HFSEL is set, it is not allowed to write the DHRx register
90	 * during 8 clock cycles after the ENx bit is set. It is not allowed
91	 * to make software/hardware trigger during this period either.
92	 */
93	if (en && dac->common->hfsel)
94		udelay(1);
95
96	if (!enable) {
97		pm_runtime_mark_last_busy(dev);
98		pm_runtime_put_autosuspend(dev);
99	}
100
101	return 0;
102
103err_put_pm:
104	if (enable) {
105		pm_runtime_mark_last_busy(dev);
106		pm_runtime_put_autosuspend(dev);
107	}
108
109	return ret;
110}
111
112static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
113{
114	int ret;
115
116	if (STM32_DAC_IS_CHAN_1(channel))
117		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
118	else
119		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
120
121	return ret ? ret : IIO_VAL_INT;
122}
123
124static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
125{
126	int ret;
127
128	if (STM32_DAC_IS_CHAN_1(channel))
129		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
130	else
131		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
132
133	return ret;
134}
135
136static int stm32_dac_read_raw(struct iio_dev *indio_dev,
137			      struct iio_chan_spec const *chan,
138			      int *val, int *val2, long mask)
139{
140	struct stm32_dac *dac = iio_priv(indio_dev);
141
142	switch (mask) {
143	case IIO_CHAN_INFO_RAW:
144		return stm32_dac_get_value(dac, chan->channel, val);
145	case IIO_CHAN_INFO_SCALE:
146		*val = dac->common->vref_mv;
147		*val2 = chan->scan_type.realbits;
148		return IIO_VAL_FRACTIONAL_LOG2;
149	default:
150		return -EINVAL;
151	}
152}
153
154static int stm32_dac_write_raw(struct iio_dev *indio_dev,
155			       struct iio_chan_spec const *chan,
156			       int val, int val2, long mask)
157{
158	struct stm32_dac *dac = iio_priv(indio_dev);
159
160	switch (mask) {
161	case IIO_CHAN_INFO_RAW:
162		return stm32_dac_set_value(dac, chan->channel, val);
163	default:
164		return -EINVAL;
165	}
166}
167
168static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
169					unsigned reg, unsigned writeval,
170					unsigned *readval)
171{
172	struct stm32_dac *dac = iio_priv(indio_dev);
173
174	if (!readval)
175		return regmap_write(dac->common->regmap, reg, writeval);
176	else
177		return regmap_read(dac->common->regmap, reg, readval);
178}
179
180static const struct iio_info stm32_dac_iio_info = {
181	.read_raw = stm32_dac_read_raw,
182	.write_raw = stm32_dac_write_raw,
183	.debugfs_reg_access = stm32_dac_debugfs_reg_access,
184};
185
186static const char * const stm32_dac_powerdown_modes[] = {
187	"three_state",
188};
189
190static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
191					const struct iio_chan_spec *chan)
192{
193	return 0;
194}
195
196static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
197					const struct iio_chan_spec *chan,
198					unsigned int type)
199{
200	return 0;
201}
202
203static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
204					uintptr_t private,
205					const struct iio_chan_spec *chan,
206					char *buf)
207{
208	int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
209
210	if (ret < 0)
211		return ret;
212
213	return sprintf(buf, "%d\n", ret ? 0 : 1);
214}
215
216static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
217					 uintptr_t private,
218					 const struct iio_chan_spec *chan,
219					 const char *buf, size_t len)
220{
221	bool powerdown;
222	int ret;
223
224	ret = strtobool(buf, &powerdown);
225	if (ret)
226		return ret;
227
228	ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
229	if (ret)
230		return ret;
231
232	return len;
233}
234
235static const struct iio_enum stm32_dac_powerdown_mode_en = {
236	.items = stm32_dac_powerdown_modes,
237	.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
238	.get = stm32_dac_get_powerdown_mode,
239	.set = stm32_dac_set_powerdown_mode,
240};
241
242static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
243	{
244		.name = "powerdown",
245		.read = stm32_dac_read_powerdown,
246		.write = stm32_dac_write_powerdown,
247		.shared = IIO_SEPARATE,
248	},
249	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
250	IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
251	{},
252};
253
254#define STM32_DAC_CHANNEL(chan, name) {			\
255	.type = IIO_VOLTAGE,				\
256	.indexed = 1,					\
257	.output = 1,					\
258	.channel = chan,				\
259	.info_mask_separate =				\
260		BIT(IIO_CHAN_INFO_RAW) |		\
261		BIT(IIO_CHAN_INFO_SCALE),		\
262	/* scan_index is always 0 as num_channels is 1 */ \
263	.scan_type = {					\
264		.sign = 'u',				\
265		.realbits = 12,				\
266		.storagebits = 16,			\
267	},						\
268	.datasheet_name = name,				\
269	.ext_info = stm32_dac_ext_info			\
270}
271
272static const struct iio_chan_spec stm32_dac_channels[] = {
273	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
274	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
275};
276
277static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
278{
279	struct device_node *np = indio_dev->dev.of_node;
280	unsigned int i;
281	u32 channel;
282	int ret;
283
284	ret = of_property_read_u32(np, "reg", &channel);
285	if (ret) {
286		dev_err(&indio_dev->dev, "Failed to read reg property\n");
287		return ret;
288	}
289
290	for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
291		if (stm32_dac_channels[i].channel == channel)
292			break;
293	}
294	if (i >= ARRAY_SIZE(stm32_dac_channels)) {
295		dev_err(&indio_dev->dev, "Invalid reg property\n");
296		return -EINVAL;
297	}
298
299	indio_dev->channels = &stm32_dac_channels[i];
300	/*
301	 * Expose only one channel here, as they can be used independently,
302	 * with separate trigger. Then separate IIO devices are instantiated
303	 * to manage this.
304	 */
305	indio_dev->num_channels = 1;
306
307	return 0;
308};
309
310static int stm32_dac_probe(struct platform_device *pdev)
311{
312	struct device_node *np = pdev->dev.of_node;
313	struct device *dev = &pdev->dev;
314	struct iio_dev *indio_dev;
315	struct stm32_dac *dac;
316	int ret;
317
318	if (!np)
319		return -ENODEV;
320
321	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
322	if (!indio_dev)
323		return -ENOMEM;
324	platform_set_drvdata(pdev, indio_dev);
325
326	dac = iio_priv(indio_dev);
327	dac->common = dev_get_drvdata(pdev->dev.parent);
328	indio_dev->name = dev_name(&pdev->dev);
329	indio_dev->dev.of_node = pdev->dev.of_node;
330	indio_dev->info = &stm32_dac_iio_info;
331	indio_dev->modes = INDIO_DIRECT_MODE;
332
333	mutex_init(&dac->lock);
334
335	ret = stm32_dac_chan_of_init(indio_dev);
336	if (ret < 0)
337		return ret;
338
339	/* Get stm32-dac-core PM online */
340	pm_runtime_get_noresume(dev);
341	pm_runtime_set_active(dev);
342	pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
343	pm_runtime_use_autosuspend(dev);
344	pm_runtime_enable(dev);
345
346	ret = iio_device_register(indio_dev);
347	if (ret)
348		goto err_pm_put;
349
350	pm_runtime_mark_last_busy(dev);
351	pm_runtime_put_autosuspend(dev);
352
353	return 0;
354
355err_pm_put:
356	pm_runtime_disable(dev);
357	pm_runtime_set_suspended(dev);
358	pm_runtime_put_noidle(dev);
359
360	return ret;
361}
362
363static int stm32_dac_remove(struct platform_device *pdev)
364{
365	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
366
367	pm_runtime_get_sync(&pdev->dev);
368	iio_device_unregister(indio_dev);
369	pm_runtime_disable(&pdev->dev);
370	pm_runtime_set_suspended(&pdev->dev);
371	pm_runtime_put_noidle(&pdev->dev);
372
373	return 0;
374}
375
376static int __maybe_unused stm32_dac_suspend(struct device *dev)
377{
378	struct iio_dev *indio_dev = dev_get_drvdata(dev);
379	int channel = indio_dev->channels[0].channel;
380	int ret;
381
382	/* Ensure DAC is disabled before suspend */
383	ret = stm32_dac_is_enabled(indio_dev, channel);
384	if (ret)
385		return ret < 0 ? ret : -EBUSY;
386
387	return pm_runtime_force_suspend(dev);
388}
389
390static const struct dev_pm_ops stm32_dac_pm_ops = {
391	SET_SYSTEM_SLEEP_PM_OPS(stm32_dac_suspend, pm_runtime_force_resume)
392};
393
394static const struct of_device_id stm32_dac_of_match[] = {
395	{ .compatible = "st,stm32-dac", },
396	{},
397};
398MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
399
400static struct platform_driver stm32_dac_driver = {
401	.probe = stm32_dac_probe,
402	.remove = stm32_dac_remove,
403	.driver = {
404		.name = "stm32-dac",
405		.of_match_table = stm32_dac_of_match,
406		.pm = &stm32_dac_pm_ops,
407	},
408};
409module_platform_driver(stm32_dac_driver);
410
411MODULE_ALIAS("platform:stm32-dac");
412MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
413MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
414MODULE_LICENSE("GPL v2");
415