1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Xilinx XADC driver 4 * 5 * Copyright 2013-2014 Analog Devices Inc. 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 * 8 * Documentation for the parts can be found at: 9 * - XADC hardmacro: Xilinx UG480 10 * - ZYNQ XADC interface: Xilinx UG585 11 * - AXI XADC interface: Xilinx PG019 12 */ 13 14#include <linux/clk.h> 15#include <linux/device.h> 16#include <linux/err.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/of.h> 22#include <linux/overflow.h> 23#include <linux/platform_device.h> 24#include <linux/slab.h> 25#include <linux/sysfs.h> 26 27#include <linux/iio/buffer.h> 28#include <linux/iio/events.h> 29#include <linux/iio/iio.h> 30#include <linux/iio/sysfs.h> 31#include <linux/iio/trigger.h> 32#include <linux/iio/trigger_consumer.h> 33#include <linux/iio/triggered_buffer.h> 34 35#include "xilinx-xadc.h" 36 37static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500; 38 39/* ZYNQ register definitions */ 40#define XADC_ZYNQ_REG_CFG 0x00 41#define XADC_ZYNQ_REG_INTSTS 0x04 42#define XADC_ZYNQ_REG_INTMSK 0x08 43#define XADC_ZYNQ_REG_STATUS 0x0c 44#define XADC_ZYNQ_REG_CFIFO 0x10 45#define XADC_ZYNQ_REG_DFIFO 0x14 46#define XADC_ZYNQ_REG_CTL 0x18 47 48#define XADC_ZYNQ_CFG_ENABLE BIT(31) 49#define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20) 50#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20 51#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16) 52#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16 53#define XADC_ZYNQ_CFG_WEDGE BIT(13) 54#define XADC_ZYNQ_CFG_REDGE BIT(12) 55#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8) 56#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8) 57#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8) 58#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8) 59#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8) 60#define XADC_ZYNQ_CFG_IGAP_MASK 0x1f 61#define XADC_ZYNQ_CFG_IGAP(x) (x) 62 63#define XADC_ZYNQ_INT_CFIFO_LTH BIT(9) 64#define XADC_ZYNQ_INT_DFIFO_GTH BIT(8) 65#define XADC_ZYNQ_INT_ALARM_MASK 0xff 66#define XADC_ZYNQ_INT_ALARM_OFFSET 0 67 68#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16) 69#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16 70#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12) 71#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12 72#define XADC_ZYNQ_STATUS_CFIFOF BIT(11) 73#define XADC_ZYNQ_STATUS_CFIFOE BIT(10) 74#define XADC_ZYNQ_STATUS_DFIFOF BIT(9) 75#define XADC_ZYNQ_STATUS_DFIFOE BIT(8) 76#define XADC_ZYNQ_STATUS_OT BIT(7) 77#define XADC_ZYNQ_STATUS_ALM(x) BIT(x) 78 79#define XADC_ZYNQ_CTL_RESET BIT(4) 80 81#define XADC_ZYNQ_CMD_NOP 0x00 82#define XADC_ZYNQ_CMD_READ 0x01 83#define XADC_ZYNQ_CMD_WRITE 0x02 84 85#define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data)) 86 87/* AXI register definitions */ 88#define XADC_AXI_REG_RESET 0x00 89#define XADC_AXI_REG_STATUS 0x04 90#define XADC_AXI_REG_ALARM_STATUS 0x08 91#define XADC_AXI_REG_CONVST 0x0c 92#define XADC_AXI_REG_XADC_RESET 0x10 93#define XADC_AXI_REG_GIER 0x5c 94#define XADC_AXI_REG_IPISR 0x60 95#define XADC_AXI_REG_IPIER 0x68 96#define XADC_AXI_ADC_REG_OFFSET 0x200 97 98#define XADC_AXI_RESET_MAGIC 0xa 99#define XADC_AXI_GIER_ENABLE BIT(31) 100 101#define XADC_AXI_INT_EOS BIT(4) 102#define XADC_AXI_INT_ALARM_MASK 0x3c0f 103 104#define XADC_FLAGS_BUFFERED BIT(0) 105 106/* 107 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does 108 * not have a hardware FIFO. Which means an interrupt is generated for each 109 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely 110 * overloaded by the interrupts that it soft-lockups. For this reason the driver 111 * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy, 112 * but still responsive. 113 */ 114#define XADC_MAX_SAMPLERATE 150000 115 116static void xadc_write_reg(struct xadc *xadc, unsigned int reg, 117 uint32_t val) 118{ 119 writel(val, xadc->base + reg); 120} 121 122static void xadc_read_reg(struct xadc *xadc, unsigned int reg, 123 uint32_t *val) 124{ 125 *val = readl(xadc->base + reg); 126} 127 128/* 129 * The ZYNQ interface uses two asynchronous FIFOs for communication with the 130 * XADC. Reads and writes to the XADC register are performed by submitting a 131 * request to the command FIFO (CFIFO), once the request has been completed the 132 * result can be read from the data FIFO (DFIFO). The method currently used in 133 * this driver is to submit the request for a read/write operation, then go to 134 * sleep and wait for an interrupt that signals that a response is available in 135 * the data FIFO. 136 */ 137 138static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd, 139 unsigned int n) 140{ 141 unsigned int i; 142 143 for (i = 0; i < n; i++) 144 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]); 145} 146 147static void xadc_zynq_drain_fifo(struct xadc *xadc) 148{ 149 uint32_t status, tmp; 150 151 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status); 152 153 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) { 154 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp); 155 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status); 156 } 157} 158 159static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask, 160 unsigned int val) 161{ 162 xadc->zynq_intmask &= ~mask; 163 xadc->zynq_intmask |= val; 164 165 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, 166 xadc->zynq_intmask | xadc->zynq_masked_alarm); 167} 168 169static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, 170 uint16_t val) 171{ 172 uint32_t cmd[1]; 173 uint32_t tmp; 174 int ret; 175 176 spin_lock_irq(&xadc->lock); 177 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 178 XADC_ZYNQ_INT_DFIFO_GTH); 179 180 reinit_completion(&xadc->completion); 181 182 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val); 183 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd)); 184 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp); 185 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK; 186 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; 187 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp); 188 189 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0); 190 spin_unlock_irq(&xadc->lock); 191 192 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ); 193 if (ret == 0) 194 ret = -EIO; 195 else 196 ret = 0; 197 198 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp); 199 200 return ret; 201} 202 203static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, 204 uint16_t *val) 205{ 206 uint32_t cmd[2]; 207 uint32_t resp, tmp; 208 int ret; 209 210 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0); 211 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0); 212 213 spin_lock_irq(&xadc->lock); 214 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 215 XADC_ZYNQ_INT_DFIFO_GTH); 216 xadc_zynq_drain_fifo(xadc); 217 reinit_completion(&xadc->completion); 218 219 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd)); 220 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp); 221 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK; 222 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; 223 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp); 224 225 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0); 226 spin_unlock_irq(&xadc->lock); 227 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ); 228 if (ret == 0) 229 ret = -EIO; 230 if (ret < 0) 231 return ret; 232 233 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp); 234 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp); 235 236 *val = resp & 0xffff; 237 238 return 0; 239} 240 241static unsigned int xadc_zynq_transform_alarm(unsigned int alarm) 242{ 243 return ((alarm & 0x80) >> 4) | 244 ((alarm & 0x78) << 1) | 245 (alarm & 0x07); 246} 247 248/* 249 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the 250 * threshold condition go way from within the interrupt handler, this means as 251 * soon as a threshold condition is present we would enter the interrupt handler 252 * again and again. To work around this we mask all active thresholds interrupts 253 * in the interrupt handler and start a timer. In this timer we poll the 254 * interrupt status and only if the interrupt is inactive we unmask it again. 255 */ 256static void xadc_zynq_unmask_worker(struct work_struct *work) 257{ 258 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work); 259 unsigned int misc_sts, unmask; 260 261 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts); 262 263 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK; 264 265 spin_lock_irq(&xadc->lock); 266 267 /* Clear those bits which are not active anymore */ 268 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm; 269 xadc->zynq_masked_alarm &= misc_sts; 270 271 /* Also clear those which are masked out anyway */ 272 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask; 273 274 /* Clear the interrupts before we unmask them */ 275 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask); 276 277 xadc_zynq_update_intmsk(xadc, 0, 0); 278 279 spin_unlock_irq(&xadc->lock); 280 281 /* if still pending some alarm re-trigger the timer */ 282 if (xadc->zynq_masked_alarm) { 283 schedule_delayed_work(&xadc->zynq_unmask_work, 284 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT)); 285 } 286 287} 288 289static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid) 290{ 291 struct iio_dev *indio_dev = devid; 292 struct xadc *xadc = iio_priv(indio_dev); 293 uint32_t status; 294 295 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status); 296 297 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm); 298 299 if (!status) 300 return IRQ_NONE; 301 302 spin_lock(&xadc->lock); 303 304 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status); 305 306 if (status & XADC_ZYNQ_INT_DFIFO_GTH) { 307 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 308 XADC_ZYNQ_INT_DFIFO_GTH); 309 complete(&xadc->completion); 310 } 311 312 status &= XADC_ZYNQ_INT_ALARM_MASK; 313 if (status) { 314 xadc->zynq_masked_alarm |= status; 315 /* 316 * mask the current event interrupt, 317 * unmask it when the interrupt is no more active. 318 */ 319 xadc_zynq_update_intmsk(xadc, 0, 0); 320 321 xadc_handle_events(indio_dev, 322 xadc_zynq_transform_alarm(status)); 323 324 /* unmask the required interrupts in timer. */ 325 schedule_delayed_work(&xadc->zynq_unmask_work, 326 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT)); 327 } 328 spin_unlock(&xadc->lock); 329 330 return IRQ_HANDLED; 331} 332 333#define XADC_ZYNQ_TCK_RATE_MAX 50000000 334#define XADC_ZYNQ_IGAP_DEFAULT 20 335#define XADC_ZYNQ_PCAP_RATE_MAX 200000000 336 337static int xadc_zynq_setup(struct platform_device *pdev, 338 struct iio_dev *indio_dev, int irq) 339{ 340 struct xadc *xadc = iio_priv(indio_dev); 341 unsigned long pcap_rate; 342 unsigned int tck_div; 343 unsigned int div; 344 unsigned int igap; 345 unsigned int tck_rate; 346 int ret; 347 348 /* TODO: Figure out how to make igap and tck_rate configurable */ 349 igap = XADC_ZYNQ_IGAP_DEFAULT; 350 tck_rate = XADC_ZYNQ_TCK_RATE_MAX; 351 352 xadc->zynq_intmask = ~0; 353 354 pcap_rate = clk_get_rate(xadc->clk); 355 if (!pcap_rate) 356 return -EINVAL; 357 358 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) { 359 ret = clk_set_rate(xadc->clk, 360 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX); 361 if (ret) 362 return ret; 363 } 364 365 if (tck_rate > pcap_rate / 2) { 366 div = 2; 367 } else { 368 div = pcap_rate / tck_rate; 369 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX) 370 div++; 371 } 372 373 if (div <= 3) 374 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2; 375 else if (div <= 7) 376 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4; 377 else if (div <= 15) 378 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8; 379 else 380 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16; 381 382 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET); 383 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0); 384 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0); 385 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask); 386 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | 387 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE | 388 tck_div | XADC_ZYNQ_CFG_IGAP(igap)); 389 390 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) { 391 ret = clk_set_rate(xadc->clk, pcap_rate); 392 if (ret) 393 return ret; 394 } 395 396 return 0; 397} 398 399static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc) 400{ 401 unsigned int div; 402 uint32_t val; 403 404 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val); 405 406 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) { 407 case XADC_ZYNQ_CFG_TCKRATE_DIV4: 408 div = 4; 409 break; 410 case XADC_ZYNQ_CFG_TCKRATE_DIV8: 411 div = 8; 412 break; 413 case XADC_ZYNQ_CFG_TCKRATE_DIV16: 414 div = 16; 415 break; 416 default: 417 div = 2; 418 break; 419 } 420 421 return clk_get_rate(xadc->clk) / div; 422} 423 424static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm) 425{ 426 unsigned long flags; 427 uint32_t status; 428 429 /* Move OT to bit 7 */ 430 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07); 431 432 spin_lock_irqsave(&xadc->lock, flags); 433 434 /* Clear previous interrupts if any. */ 435 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status); 436 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm); 437 438 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK, 439 ~alarm & XADC_ZYNQ_INT_ALARM_MASK); 440 441 spin_unlock_irqrestore(&xadc->lock, flags); 442} 443 444static const struct xadc_ops xadc_zynq_ops = { 445 .read = xadc_zynq_read_adc_reg, 446 .write = xadc_zynq_write_adc_reg, 447 .setup = xadc_zynq_setup, 448 .get_dclk_rate = xadc_zynq_get_dclk_rate, 449 .interrupt_handler = xadc_zynq_interrupt_handler, 450 .update_alarm = xadc_zynq_update_alarm, 451}; 452 453static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, 454 uint16_t *val) 455{ 456 uint32_t val32; 457 458 xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32); 459 *val = val32 & 0xffff; 460 461 return 0; 462} 463 464static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, 465 uint16_t val) 466{ 467 xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val); 468 469 return 0; 470} 471 472static int xadc_axi_setup(struct platform_device *pdev, 473 struct iio_dev *indio_dev, int irq) 474{ 475 struct xadc *xadc = iio_priv(indio_dev); 476 477 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC); 478 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE); 479 480 return 0; 481} 482 483static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid) 484{ 485 struct iio_dev *indio_dev = devid; 486 struct xadc *xadc = iio_priv(indio_dev); 487 uint32_t status, mask; 488 unsigned int events; 489 490 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status); 491 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask); 492 status &= mask; 493 494 if (!status) 495 return IRQ_NONE; 496 497 if ((status & XADC_AXI_INT_EOS) && xadc->trigger) 498 iio_trigger_poll(xadc->trigger); 499 500 if (status & XADC_AXI_INT_ALARM_MASK) { 501 /* 502 * The order of the bits in the AXI-XADC status register does 503 * not match the order of the bits in the XADC alarm enable 504 * register. xadc_handle_events() expects the events to be in 505 * the same order as the XADC alarm enable register. 506 */ 507 events = (status & 0x000e) >> 1; 508 events |= (status & 0x0001) << 3; 509 events |= (status & 0x3c00) >> 6; 510 xadc_handle_events(indio_dev, events); 511 } 512 513 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status); 514 515 return IRQ_HANDLED; 516} 517 518static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm) 519{ 520 uint32_t val; 521 unsigned long flags; 522 523 /* 524 * The order of the bits in the AXI-XADC status register does not match 525 * the order of the bits in the XADC alarm enable register. We get 526 * passed the alarm mask in the same order as in the XADC alarm enable 527 * register. 528 */ 529 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | 530 ((alarm & 0xf0) << 6); 531 532 spin_lock_irqsave(&xadc->lock, flags); 533 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); 534 val &= ~XADC_AXI_INT_ALARM_MASK; 535 val |= alarm; 536 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val); 537 spin_unlock_irqrestore(&xadc->lock, flags); 538} 539 540static unsigned long xadc_axi_get_dclk(struct xadc *xadc) 541{ 542 return clk_get_rate(xadc->clk); 543} 544 545static const struct xadc_ops xadc_axi_ops = { 546 .read = xadc_axi_read_adc_reg, 547 .write = xadc_axi_write_adc_reg, 548 .setup = xadc_axi_setup, 549 .get_dclk_rate = xadc_axi_get_dclk, 550 .update_alarm = xadc_axi_update_alarm, 551 .interrupt_handler = xadc_axi_interrupt_handler, 552 .flags = XADC_FLAGS_BUFFERED, 553}; 554 555static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, 556 uint16_t mask, uint16_t val) 557{ 558 uint16_t tmp; 559 int ret; 560 561 ret = _xadc_read_adc_reg(xadc, reg, &tmp); 562 if (ret) 563 return ret; 564 565 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val); 566} 567 568static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, 569 uint16_t mask, uint16_t val) 570{ 571 int ret; 572 573 mutex_lock(&xadc->mutex); 574 ret = _xadc_update_adc_reg(xadc, reg, mask, val); 575 mutex_unlock(&xadc->mutex); 576 577 return ret; 578} 579 580static unsigned long xadc_get_dclk_rate(struct xadc *xadc) 581{ 582 return xadc->ops->get_dclk_rate(xadc); 583} 584 585static int xadc_update_scan_mode(struct iio_dev *indio_dev, 586 const unsigned long *mask) 587{ 588 struct xadc *xadc = iio_priv(indio_dev); 589 size_t new_size, n; 590 void *data; 591 592 n = bitmap_weight(mask, indio_dev->masklength); 593 594 if (check_mul_overflow(n, sizeof(*xadc->data), &new_size)) 595 return -ENOMEM; 596 597 data = devm_krealloc(indio_dev->dev.parent, xadc->data, 598 new_size, GFP_KERNEL); 599 if (!data) 600 return -ENOMEM; 601 602 memset(data, 0, new_size); 603 xadc->data = data; 604 605 return 0; 606} 607 608static unsigned int xadc_scan_index_to_channel(unsigned int scan_index) 609{ 610 switch (scan_index) { 611 case 5: 612 return XADC_REG_VCCPINT; 613 case 6: 614 return XADC_REG_VCCPAUX; 615 case 7: 616 return XADC_REG_VCCO_DDR; 617 case 8: 618 return XADC_REG_TEMP; 619 case 9: 620 return XADC_REG_VCCINT; 621 case 10: 622 return XADC_REG_VCCAUX; 623 case 11: 624 return XADC_REG_VPVN; 625 case 12: 626 return XADC_REG_VREFP; 627 case 13: 628 return XADC_REG_VREFN; 629 case 14: 630 return XADC_REG_VCCBRAM; 631 default: 632 return XADC_REG_VAUX(scan_index - 16); 633 } 634} 635 636static irqreturn_t xadc_trigger_handler(int irq, void *p) 637{ 638 struct iio_poll_func *pf = p; 639 struct iio_dev *indio_dev = pf->indio_dev; 640 struct xadc *xadc = iio_priv(indio_dev); 641 unsigned int chan; 642 int i, j; 643 644 if (!xadc->data) 645 goto out; 646 647 j = 0; 648 for_each_set_bit(i, indio_dev->active_scan_mask, 649 indio_dev->masklength) { 650 chan = xadc_scan_index_to_channel(i); 651 xadc_read_adc_reg(xadc, chan, &xadc->data[j]); 652 j++; 653 } 654 655 iio_push_to_buffers(indio_dev, xadc->data); 656 657out: 658 iio_trigger_notify_done(indio_dev->trig); 659 660 return IRQ_HANDLED; 661} 662 663static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state) 664{ 665 struct xadc *xadc = iio_trigger_get_drvdata(trigger); 666 unsigned long flags; 667 unsigned int convst; 668 unsigned int val; 669 int ret = 0; 670 671 mutex_lock(&xadc->mutex); 672 673 if (state) { 674 /* Only one of the two triggers can be active at a time. */ 675 if (xadc->trigger != NULL) { 676 ret = -EBUSY; 677 goto err_out; 678 } else { 679 xadc->trigger = trigger; 680 if (trigger == xadc->convst_trigger) 681 convst = XADC_CONF0_EC; 682 else 683 convst = 0; 684 } 685 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC, 686 convst); 687 if (ret) 688 goto err_out; 689 } else { 690 xadc->trigger = NULL; 691 } 692 693 spin_lock_irqsave(&xadc->lock, flags); 694 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); 695 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS); 696 if (state) 697 val |= XADC_AXI_INT_EOS; 698 else 699 val &= ~XADC_AXI_INT_EOS; 700 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val); 701 spin_unlock_irqrestore(&xadc->lock, flags); 702 703err_out: 704 mutex_unlock(&xadc->mutex); 705 706 return ret; 707} 708 709static const struct iio_trigger_ops xadc_trigger_ops = { 710 .set_trigger_state = &xadc_trigger_set_state, 711}; 712 713static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev, 714 const char *name) 715{ 716 struct device *dev = indio_dev->dev.parent; 717 struct iio_trigger *trig; 718 int ret; 719 720 trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name, 721 indio_dev->id, name); 722 if (trig == NULL) 723 return ERR_PTR(-ENOMEM); 724 725 trig->dev.parent = indio_dev->dev.parent; 726 trig->ops = &xadc_trigger_ops; 727 iio_trigger_set_drvdata(trig, iio_priv(indio_dev)); 728 729 ret = devm_iio_trigger_register(dev, trig); 730 if (ret) 731 return ERR_PTR(ret); 732 733 return trig; 734} 735 736static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode) 737{ 738 uint16_t val; 739 740 /* Powerdown the ADC-B when it is not needed. */ 741 switch (seq_mode) { 742 case XADC_CONF1_SEQ_SIMULTANEOUS: 743 case XADC_CONF1_SEQ_INDEPENDENT: 744 val = 0; 745 break; 746 default: 747 val = XADC_CONF2_PD_ADC_B; 748 break; 749 } 750 751 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK, 752 val); 753} 754 755static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode) 756{ 757 unsigned int aux_scan_mode = scan_mode >> 16; 758 759 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL) 760 return XADC_CONF1_SEQ_SIMULTANEOUS; 761 762 if ((aux_scan_mode & 0xff00) == 0 || 763 (aux_scan_mode & 0x00ff) == 0) 764 return XADC_CONF1_SEQ_CONTINUOUS; 765 766 return XADC_CONF1_SEQ_SIMULTANEOUS; 767} 768 769static int xadc_postdisable(struct iio_dev *indio_dev) 770{ 771 struct xadc *xadc = iio_priv(indio_dev); 772 unsigned long scan_mask; 773 int ret; 774 int i; 775 776 scan_mask = 1; /* Run calibration as part of the sequence */ 777 for (i = 0; i < indio_dev->num_channels; i++) 778 scan_mask |= BIT(indio_dev->channels[i].scan_index); 779 780 /* Enable all channels and calibration */ 781 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff); 782 if (ret) 783 return ret; 784 785 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); 786 if (ret) 787 return ret; 788 789 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, 790 XADC_CONF1_SEQ_CONTINUOUS); 791 if (ret) 792 return ret; 793 794 return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS); 795} 796 797static int xadc_preenable(struct iio_dev *indio_dev) 798{ 799 struct xadc *xadc = iio_priv(indio_dev); 800 unsigned long scan_mask; 801 int seq_mode; 802 int ret; 803 804 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, 805 XADC_CONF1_SEQ_DEFAULT); 806 if (ret) 807 goto err; 808 809 scan_mask = *indio_dev->active_scan_mask; 810 seq_mode = xadc_get_seq_mode(xadc, scan_mask); 811 812 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff); 813 if (ret) 814 goto err; 815 816 /* 817 * In simultaneous mode the upper and lower aux channels are samples at 818 * the same time. In this mode the upper 8 bits in the sequencer 819 * register are don't care and the lower 8 bits control two channels 820 * each. As such we must set the bit if either the channel in the lower 821 * group or the upper group is enabled. 822 */ 823 if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS) 824 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000; 825 826 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); 827 if (ret) 828 goto err; 829 830 ret = xadc_power_adc_b(xadc, seq_mode); 831 if (ret) 832 goto err; 833 834 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, 835 seq_mode); 836 if (ret) 837 goto err; 838 839 return 0; 840err: 841 xadc_postdisable(indio_dev); 842 return ret; 843} 844 845static const struct iio_buffer_setup_ops xadc_buffer_ops = { 846 .preenable = &xadc_preenable, 847 .postdisable = &xadc_postdisable, 848}; 849 850static int xadc_read_samplerate(struct xadc *xadc) 851{ 852 unsigned int div; 853 uint16_t val16; 854 int ret; 855 856 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16); 857 if (ret) 858 return ret; 859 860 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; 861 if (div < 2) 862 div = 2; 863 864 return xadc_get_dclk_rate(xadc) / div / 26; 865} 866 867static int xadc_read_raw(struct iio_dev *indio_dev, 868 struct iio_chan_spec const *chan, int *val, int *val2, long info) 869{ 870 struct xadc *xadc = iio_priv(indio_dev); 871 uint16_t val16; 872 int ret; 873 874 switch (info) { 875 case IIO_CHAN_INFO_RAW: 876 if (iio_buffer_enabled(indio_dev)) 877 return -EBUSY; 878 ret = xadc_read_adc_reg(xadc, chan->address, &val16); 879 if (ret < 0) 880 return ret; 881 882 val16 >>= 4; 883 if (chan->scan_type.sign == 'u') 884 *val = val16; 885 else 886 *val = sign_extend32(val16, 11); 887 888 return IIO_VAL_INT; 889 case IIO_CHAN_INFO_SCALE: 890 switch (chan->type) { 891 case IIO_VOLTAGE: 892 /* V = (val * 3.0) / 4096 */ 893 switch (chan->address) { 894 case XADC_REG_VCCINT: 895 case XADC_REG_VCCAUX: 896 case XADC_REG_VREFP: 897 case XADC_REG_VREFN: 898 case XADC_REG_VCCBRAM: 899 case XADC_REG_VCCPINT: 900 case XADC_REG_VCCPAUX: 901 case XADC_REG_VCCO_DDR: 902 *val = 3000; 903 break; 904 default: 905 *val = 1000; 906 break; 907 } 908 *val2 = 12; 909 return IIO_VAL_FRACTIONAL_LOG2; 910 case IIO_TEMP: 911 /* Temp in C = (val * 503.975) / 4096 - 273.15 */ 912 *val = 503975; 913 *val2 = 12; 914 return IIO_VAL_FRACTIONAL_LOG2; 915 default: 916 return -EINVAL; 917 } 918 case IIO_CHAN_INFO_OFFSET: 919 /* Only the temperature channel has an offset */ 920 *val = -((273150 << 12) / 503975); 921 return IIO_VAL_INT; 922 case IIO_CHAN_INFO_SAMP_FREQ: 923 ret = xadc_read_samplerate(xadc); 924 if (ret < 0) 925 return ret; 926 927 *val = ret; 928 return IIO_VAL_INT; 929 default: 930 return -EINVAL; 931 } 932} 933 934static int xadc_write_samplerate(struct xadc *xadc, int val) 935{ 936 unsigned long clk_rate = xadc_get_dclk_rate(xadc); 937 unsigned int div; 938 939 if (!clk_rate) 940 return -EINVAL; 941 942 if (val <= 0) 943 return -EINVAL; 944 945 /* Max. 150 kSPS */ 946 if (val > XADC_MAX_SAMPLERATE) 947 val = XADC_MAX_SAMPLERATE; 948 949 val *= 26; 950 951 /* Min 1MHz */ 952 if (val < 1000000) 953 val = 1000000; 954 955 /* 956 * We want to round down, but only if we do not exceed the 150 kSPS 957 * limit. 958 */ 959 div = clk_rate / val; 960 if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE) 961 div++; 962 if (div < 2) 963 div = 2; 964 else if (div > 0xff) 965 div = 0xff; 966 967 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK, 968 div << XADC_CONF2_DIV_OFFSET); 969} 970 971static int xadc_write_raw(struct iio_dev *indio_dev, 972 struct iio_chan_spec const *chan, int val, int val2, long info) 973{ 974 struct xadc *xadc = iio_priv(indio_dev); 975 976 if (info != IIO_CHAN_INFO_SAMP_FREQ) 977 return -EINVAL; 978 979 return xadc_write_samplerate(xadc, val); 980} 981 982static const struct iio_event_spec xadc_temp_events[] = { 983 { 984 .type = IIO_EV_TYPE_THRESH, 985 .dir = IIO_EV_DIR_RISING, 986 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 987 BIT(IIO_EV_INFO_VALUE) | 988 BIT(IIO_EV_INFO_HYSTERESIS), 989 }, 990}; 991 992/* Separate values for upper and lower thresholds, but only a shared enabled */ 993static const struct iio_event_spec xadc_voltage_events[] = { 994 { 995 .type = IIO_EV_TYPE_THRESH, 996 .dir = IIO_EV_DIR_RISING, 997 .mask_separate = BIT(IIO_EV_INFO_VALUE), 998 }, { 999 .type = IIO_EV_TYPE_THRESH, 1000 .dir = IIO_EV_DIR_FALLING, 1001 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1002 }, { 1003 .type = IIO_EV_TYPE_THRESH, 1004 .dir = IIO_EV_DIR_EITHER, 1005 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1006 }, 1007}; 1008 1009#define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \ 1010 .type = IIO_TEMP, \ 1011 .indexed = 1, \ 1012 .channel = (_chan), \ 1013 .address = (_addr), \ 1014 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1015 BIT(IIO_CHAN_INFO_SCALE) | \ 1016 BIT(IIO_CHAN_INFO_OFFSET), \ 1017 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1018 .event_spec = xadc_temp_events, \ 1019 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \ 1020 .scan_index = (_scan_index), \ 1021 .scan_type = { \ 1022 .sign = 'u', \ 1023 .realbits = 12, \ 1024 .storagebits = 16, \ 1025 .shift = 4, \ 1026 .endianness = IIO_CPU, \ 1027 }, \ 1028} 1029 1030#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \ 1031 .type = IIO_VOLTAGE, \ 1032 .indexed = 1, \ 1033 .channel = (_chan), \ 1034 .address = (_addr), \ 1035 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1036 BIT(IIO_CHAN_INFO_SCALE), \ 1037 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1038 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \ 1039 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \ 1040 .scan_index = (_scan_index), \ 1041 .scan_type = { \ 1042 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \ 1043 .realbits = 12, \ 1044 .storagebits = 16, \ 1045 .shift = 4, \ 1046 .endianness = IIO_CPU, \ 1047 }, \ 1048 .extend_name = _ext, \ 1049} 1050 1051static const struct iio_chan_spec xadc_channels[] = { 1052 XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP), 1053 XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true), 1054 XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true), 1055 XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true), 1056 XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true), 1057 XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true), 1058 XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true), 1059 XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false), 1060 XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false), 1061 XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false), 1062 XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false), 1063 XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false), 1064 XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false), 1065 XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false), 1066 XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false), 1067 XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false), 1068 XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false), 1069 XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false), 1070 XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false), 1071 XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false), 1072 XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false), 1073 XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false), 1074 XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false), 1075 XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false), 1076 XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false), 1077 XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false), 1078}; 1079 1080static const struct iio_info xadc_info = { 1081 .read_raw = &xadc_read_raw, 1082 .write_raw = &xadc_write_raw, 1083 .read_event_config = &xadc_read_event_config, 1084 .write_event_config = &xadc_write_event_config, 1085 .read_event_value = &xadc_read_event_value, 1086 .write_event_value = &xadc_write_event_value, 1087 .update_scan_mode = &xadc_update_scan_mode, 1088}; 1089 1090static const struct of_device_id xadc_of_match_table[] = { 1091 { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops }, 1092 { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops }, 1093 { }, 1094}; 1095MODULE_DEVICE_TABLE(of, xadc_of_match_table); 1096 1097static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, 1098 unsigned int *conf) 1099{ 1100 struct device *dev = indio_dev->dev.parent; 1101 struct xadc *xadc = iio_priv(indio_dev); 1102 struct iio_chan_spec *channels, *chan; 1103 struct device_node *chan_node, *child; 1104 unsigned int num_channels; 1105 const char *external_mux; 1106 u32 ext_mux_chan; 1107 u32 reg; 1108 int ret; 1109 1110 *conf = 0; 1111 1112 ret = of_property_read_string(np, "xlnx,external-mux", &external_mux); 1113 if (ret < 0 || strcasecmp(external_mux, "none") == 0) 1114 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE; 1115 else if (strcasecmp(external_mux, "single") == 0) 1116 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE; 1117 else if (strcasecmp(external_mux, "dual") == 0) 1118 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL; 1119 else 1120 return -EINVAL; 1121 1122 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) { 1123 ret = of_property_read_u32(np, "xlnx,external-mux-channel", 1124 &ext_mux_chan); 1125 if (ret < 0) 1126 return ret; 1127 1128 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) { 1129 if (ext_mux_chan == 0) 1130 ext_mux_chan = XADC_REG_VPVN; 1131 else if (ext_mux_chan <= 16) 1132 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1); 1133 else 1134 return -EINVAL; 1135 } else { 1136 if (ext_mux_chan > 0 && ext_mux_chan <= 8) 1137 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1); 1138 else 1139 return -EINVAL; 1140 } 1141 1142 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan); 1143 } 1144 1145 channels = devm_kmemdup(dev, xadc_channels, 1146 sizeof(xadc_channels), GFP_KERNEL); 1147 if (!channels) 1148 return -ENOMEM; 1149 1150 num_channels = 9; 1151 chan = &channels[9]; 1152 1153 chan_node = of_get_child_by_name(np, "xlnx,channels"); 1154 if (chan_node) { 1155 for_each_child_of_node(chan_node, child) { 1156 if (num_channels >= ARRAY_SIZE(xadc_channels)) { 1157 of_node_put(child); 1158 break; 1159 } 1160 1161 ret = of_property_read_u32(child, "reg", ®); 1162 if (ret || reg > 16) 1163 continue; 1164 1165 if (of_property_read_bool(child, "xlnx,bipolar")) 1166 chan->scan_type.sign = 's'; 1167 1168 if (reg == 0) { 1169 chan->scan_index = 11; 1170 chan->address = XADC_REG_VPVN; 1171 } else { 1172 chan->scan_index = 15 + reg; 1173 chan->address = XADC_REG_VAUX(reg - 1); 1174 } 1175 num_channels++; 1176 chan++; 1177 } 1178 } 1179 of_node_put(chan_node); 1180 1181 indio_dev->num_channels = num_channels; 1182 indio_dev->channels = devm_krealloc(dev, channels, 1183 sizeof(*channels) * num_channels, 1184 GFP_KERNEL); 1185 /* If we can't resize the channels array, just use the original */ 1186 if (!indio_dev->channels) 1187 indio_dev->channels = channels; 1188 1189 return 0; 1190} 1191 1192static void xadc_clk_disable_unprepare(void *data) 1193{ 1194 struct clk *clk = data; 1195 1196 clk_disable_unprepare(clk); 1197} 1198 1199static void xadc_cancel_delayed_work(void *data) 1200{ 1201 struct delayed_work *work = data; 1202 1203 cancel_delayed_work_sync(work); 1204} 1205 1206static int xadc_probe(struct platform_device *pdev) 1207{ 1208 struct device *dev = &pdev->dev; 1209 const struct of_device_id *id; 1210 struct iio_dev *indio_dev; 1211 unsigned int bipolar_mask; 1212 unsigned int conf0; 1213 struct xadc *xadc; 1214 int ret; 1215 int irq; 1216 int i; 1217 1218 if (!dev->of_node) 1219 return -ENODEV; 1220 1221 id = of_match_node(xadc_of_match_table, dev->of_node); 1222 if (!id) 1223 return -EINVAL; 1224 1225 irq = platform_get_irq(pdev, 0); 1226 if (irq <= 0) 1227 return -ENXIO; 1228 1229 indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc)); 1230 if (!indio_dev) 1231 return -ENOMEM; 1232 1233 xadc = iio_priv(indio_dev); 1234 xadc->ops = id->data; 1235 xadc->irq = irq; 1236 init_completion(&xadc->completion); 1237 mutex_init(&xadc->mutex); 1238 spin_lock_init(&xadc->lock); 1239 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker); 1240 1241 xadc->base = devm_platform_ioremap_resource(pdev, 0); 1242 if (IS_ERR(xadc->base)) 1243 return PTR_ERR(xadc->base); 1244 1245 indio_dev->name = "xadc"; 1246 indio_dev->modes = INDIO_DIRECT_MODE; 1247 indio_dev->info = &xadc_info; 1248 1249 ret = xadc_parse_dt(indio_dev, dev->of_node, &conf0); 1250 if (ret) 1251 return ret; 1252 1253 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { 1254 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1255 &iio_pollfunc_store_time, 1256 &xadc_trigger_handler, 1257 &xadc_buffer_ops); 1258 if (ret) 1259 return ret; 1260 1261 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst"); 1262 if (IS_ERR(xadc->convst_trigger)) 1263 return PTR_ERR(xadc->convst_trigger); 1264 1265 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, 1266 "samplerate"); 1267 if (IS_ERR(xadc->samplerate_trigger)) 1268 return PTR_ERR(xadc->samplerate_trigger); 1269 } 1270 1271 xadc->clk = devm_clk_get(dev, NULL); 1272 if (IS_ERR(xadc->clk)) 1273 return PTR_ERR(xadc->clk); 1274 1275 ret = clk_prepare_enable(xadc->clk); 1276 if (ret) 1277 return ret; 1278 1279 ret = devm_add_action_or_reset(dev, 1280 xadc_clk_disable_unprepare, xadc->clk); 1281 if (ret) 1282 return ret; 1283 1284 /* 1285 * Make sure not to exceed the maximum samplerate since otherwise the 1286 * resulting interrupt storm will soft-lock the system. 1287 */ 1288 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { 1289 ret = xadc_read_samplerate(xadc); 1290 if (ret < 0) 1291 return ret; 1292 1293 if (ret > XADC_MAX_SAMPLERATE) { 1294 ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE); 1295 if (ret < 0) 1296 return ret; 1297 } 1298 } 1299 1300 ret = devm_request_irq(dev, xadc->irq, xadc->ops->interrupt_handler, 0, 1301 dev_name(dev), indio_dev); 1302 if (ret) 1303 return ret; 1304 1305 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work, 1306 &xadc->zynq_unmask_work); 1307 if (ret) 1308 return ret; 1309 1310 ret = xadc->ops->setup(pdev, indio_dev, xadc->irq); 1311 if (ret) 1312 return ret; 1313 1314 for (i = 0; i < 16; i++) 1315 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i), 1316 &xadc->threshold[i]); 1317 1318 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0); 1319 if (ret) 1320 return ret; 1321 1322 bipolar_mask = 0; 1323 for (i = 0; i < indio_dev->num_channels; i++) { 1324 if (indio_dev->channels[i].scan_type.sign == 's') 1325 bipolar_mask |= BIT(indio_dev->channels[i].scan_index); 1326 } 1327 1328 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask); 1329 if (ret) 1330 return ret; 1331 1332 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1), 1333 bipolar_mask >> 16); 1334 if (ret) 1335 return ret; 1336 1337 /* Go to non-buffered mode */ 1338 xadc_postdisable(indio_dev); 1339 1340 return devm_iio_device_register(dev, indio_dev); 1341} 1342 1343static struct platform_driver xadc_driver = { 1344 .probe = xadc_probe, 1345 .driver = { 1346 .name = "xadc", 1347 .of_match_table = xadc_of_match_table, 1348 }, 1349}; 1350module_platform_driver(xadc_driver); 1351 1352MODULE_LICENSE("GPL v2"); 1353MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1354MODULE_DESCRIPTION("Xilinx XADC IIO driver"); 1355