1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale Vybrid vf610 ADC driver
4 *
5 * Copyright 2013 Freescale Semiconductor, Inc.
6 */
7
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/delay.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/completion.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of_platform.h>
21#include <linux/err.h>
22
23#include <linux/iio/iio.h>
24#include <linux/iio/buffer.h>
25#include <linux/iio/sysfs.h>
26#include <linux/iio/trigger.h>
27#include <linux/iio/trigger_consumer.h>
28#include <linux/iio/triggered_buffer.h>
29
30/* This will be the driver name the kernel reports */
31#define DRIVER_NAME "vf610-adc"
32
33/* Vybrid/IMX ADC registers */
34#define VF610_REG_ADC_HC0		0x00
35#define VF610_REG_ADC_HC1		0x04
36#define VF610_REG_ADC_HS		0x08
37#define VF610_REG_ADC_R0		0x0c
38#define VF610_REG_ADC_R1		0x10
39#define VF610_REG_ADC_CFG		0x14
40#define VF610_REG_ADC_GC		0x18
41#define VF610_REG_ADC_GS		0x1c
42#define VF610_REG_ADC_CV		0x20
43#define VF610_REG_ADC_OFS		0x24
44#define VF610_REG_ADC_CAL		0x28
45#define VF610_REG_ADC_PCTL		0x30
46
47/* Configuration register field define */
48#define VF610_ADC_MODE_BIT8		0x00
49#define VF610_ADC_MODE_BIT10		0x04
50#define VF610_ADC_MODE_BIT12		0x08
51#define VF610_ADC_MODE_MASK		0x0c
52#define VF610_ADC_BUSCLK2_SEL		0x01
53#define VF610_ADC_ALTCLK_SEL		0x02
54#define VF610_ADC_ADACK_SEL		0x03
55#define VF610_ADC_ADCCLK_MASK		0x03
56#define VF610_ADC_CLK_DIV2		0x20
57#define VF610_ADC_CLK_DIV4		0x40
58#define VF610_ADC_CLK_DIV8		0x60
59#define VF610_ADC_CLK_MASK		0x60
60#define VF610_ADC_ADLSMP_LONG		0x10
61#define VF610_ADC_ADSTS_SHORT   0x100
62#define VF610_ADC_ADSTS_NORMAL  0x200
63#define VF610_ADC_ADSTS_LONG    0x300
64#define VF610_ADC_ADSTS_MASK		0x300
65#define VF610_ADC_ADLPC_EN		0x80
66#define VF610_ADC_ADHSC_EN		0x400
67#define VF610_ADC_REFSEL_VALT		0x800
68#define VF610_ADC_REFSEL_VBG		0x1000
69#define VF610_ADC_ADTRG_HARD		0x2000
70#define VF610_ADC_AVGS_8		0x4000
71#define VF610_ADC_AVGS_16		0x8000
72#define VF610_ADC_AVGS_32		0xC000
73#define VF610_ADC_AVGS_MASK		0xC000
74#define VF610_ADC_OVWREN		0x10000
75
76/* General control register field define */
77#define VF610_ADC_ADACKEN		0x1
78#define VF610_ADC_DMAEN			0x2
79#define VF610_ADC_ACREN			0x4
80#define VF610_ADC_ACFGT			0x8
81#define VF610_ADC_ACFE			0x10
82#define VF610_ADC_AVGEN			0x20
83#define VF610_ADC_ADCON			0x40
84#define VF610_ADC_CAL			0x80
85
86/* Other field define */
87#define VF610_ADC_ADCHC(x)		((x) & 0x1F)
88#define VF610_ADC_AIEN			(0x1 << 7)
89#define VF610_ADC_CONV_DISABLE		0x1F
90#define VF610_ADC_HS_COCO0		0x1
91#define VF610_ADC_CALF			0x2
92#define VF610_ADC_TIMEOUT		msecs_to_jiffies(100)
93
94#define DEFAULT_SAMPLE_TIME		1000
95
96/* V at 25°C of 696 mV */
97#define VF610_VTEMP25_3V0		950
98/* V at 25°C of 699 mV */
99#define VF610_VTEMP25_3V3		867
100/* Typical sensor slope coefficient at all temperatures */
101#define VF610_TEMP_SLOPE_COEFF		1840
102
103enum clk_sel {
104	VF610_ADCIOC_BUSCLK_SET,
105	VF610_ADCIOC_ALTCLK_SET,
106	VF610_ADCIOC_ADACK_SET,
107};
108
109enum vol_ref {
110	VF610_ADCIOC_VR_VREF_SET,
111	VF610_ADCIOC_VR_VALT_SET,
112	VF610_ADCIOC_VR_VBG_SET,
113};
114
115enum average_sel {
116	VF610_ADC_SAMPLE_1,
117	VF610_ADC_SAMPLE_4,
118	VF610_ADC_SAMPLE_8,
119	VF610_ADC_SAMPLE_16,
120	VF610_ADC_SAMPLE_32,
121};
122
123enum conversion_mode_sel {
124	VF610_ADC_CONV_NORMAL,
125	VF610_ADC_CONV_HIGH_SPEED,
126	VF610_ADC_CONV_LOW_POWER,
127};
128
129enum lst_adder_sel {
130	VF610_ADCK_CYCLES_3,
131	VF610_ADCK_CYCLES_5,
132	VF610_ADCK_CYCLES_7,
133	VF610_ADCK_CYCLES_9,
134	VF610_ADCK_CYCLES_13,
135	VF610_ADCK_CYCLES_17,
136	VF610_ADCK_CYCLES_21,
137	VF610_ADCK_CYCLES_25,
138};
139
140struct vf610_adc_feature {
141	enum clk_sel	clk_sel;
142	enum vol_ref	vol_ref;
143	enum conversion_mode_sel conv_mode;
144
145	int	clk_div;
146	int     sample_rate;
147	int	res_mode;
148	u32 lst_adder_index;
149	u32 default_sample_time;
150
151	bool	calibration;
152	bool	ovwren;
153};
154
155struct vf610_adc {
156	struct device *dev;
157	void __iomem *regs;
158	struct clk *clk;
159
160	u32 vref_uv;
161	u32 value;
162	struct regulator *vref;
163
164	u32 max_adck_rate[3];
165	struct vf610_adc_feature adc_feature;
166
167	u32 sample_freq_avail[5];
168
169	struct completion completion;
170	/* Ensure the timestamp is naturally aligned */
171	struct {
172		u16 chan;
173		s64 timestamp __aligned(8);
174	} scan;
175};
176
177static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
178static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
179
180static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
181{
182	struct vf610_adc_feature *adc_feature = &info->adc_feature;
183	unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
184	u32 adck_period, lst_addr_min;
185	int divisor, i;
186
187	adck_rate = info->max_adck_rate[adc_feature->conv_mode];
188
189	if (adck_rate) {
190		/* calculate clk divider which is within specification */
191		divisor = ipg_rate / adck_rate;
192		adc_feature->clk_div = 1 << fls(divisor + 1);
193	} else {
194		/* fall-back value using a safe divisor */
195		adc_feature->clk_div = 8;
196	}
197
198	adck_rate = ipg_rate / adc_feature->clk_div;
199
200	/*
201	 * Determine the long sample time adder value to be used based
202	 * on the default minimum sample time provided.
203	 */
204	adck_period = NSEC_PER_SEC / adck_rate;
205	lst_addr_min = adc_feature->default_sample_time / adck_period;
206	for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
207		if (vf610_lst_adder[i] > lst_addr_min) {
208			adc_feature->lst_adder_index = i;
209			break;
210		}
211	}
212
213	/*
214	 * Calculate ADC sample frequencies
215	 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
216	 * which is the same as bus clock.
217	 *
218	 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
219	 * SFCAdder: fixed to 6 ADCK cycles
220	 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
221	 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
222	 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
223	 */
224	for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
225		info->sample_freq_avail[i] =
226			adck_rate / (6 + vf610_hw_avgs[i] *
227			 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
228}
229
230static inline void vf610_adc_cfg_init(struct vf610_adc *info)
231{
232	struct vf610_adc_feature *adc_feature = &info->adc_feature;
233
234	/* set default Configuration for ADC controller */
235	adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
236	adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
237
238	adc_feature->calibration = true;
239	adc_feature->ovwren = true;
240
241	adc_feature->res_mode = 12;
242	adc_feature->sample_rate = 1;
243
244	adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
245
246	vf610_adc_calculate_rates(info);
247}
248
249static void vf610_adc_cfg_post_set(struct vf610_adc *info)
250{
251	struct vf610_adc_feature *adc_feature = &info->adc_feature;
252	int cfg_data = 0;
253	int gc_data = 0;
254
255	switch (adc_feature->clk_sel) {
256	case VF610_ADCIOC_ALTCLK_SET:
257		cfg_data |= VF610_ADC_ALTCLK_SEL;
258		break;
259	case VF610_ADCIOC_ADACK_SET:
260		cfg_data |= VF610_ADC_ADACK_SEL;
261		break;
262	default:
263		break;
264	}
265
266	/* low power set for calibration */
267	cfg_data |= VF610_ADC_ADLPC_EN;
268
269	/* enable high speed for calibration */
270	cfg_data |= VF610_ADC_ADHSC_EN;
271
272	/* voltage reference */
273	switch (adc_feature->vol_ref) {
274	case VF610_ADCIOC_VR_VREF_SET:
275		break;
276	case VF610_ADCIOC_VR_VALT_SET:
277		cfg_data |= VF610_ADC_REFSEL_VALT;
278		break;
279	case VF610_ADCIOC_VR_VBG_SET:
280		cfg_data |= VF610_ADC_REFSEL_VBG;
281		break;
282	default:
283		dev_err(info->dev, "error voltage reference\n");
284	}
285
286	/* data overwrite enable */
287	if (adc_feature->ovwren)
288		cfg_data |= VF610_ADC_OVWREN;
289
290	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
291	writel(gc_data, info->regs + VF610_REG_ADC_GC);
292}
293
294static void vf610_adc_calibration(struct vf610_adc *info)
295{
296	int adc_gc, hc_cfg;
297
298	if (!info->adc_feature.calibration)
299		return;
300
301	/* enable calibration interrupt */
302	hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
303	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
304
305	adc_gc = readl(info->regs + VF610_REG_ADC_GC);
306	writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
307
308	if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
309		dev_err(info->dev, "Timeout for adc calibration\n");
310
311	adc_gc = readl(info->regs + VF610_REG_ADC_GS);
312	if (adc_gc & VF610_ADC_CALF)
313		dev_err(info->dev, "ADC calibration failed\n");
314
315	info->adc_feature.calibration = false;
316}
317
318static void vf610_adc_cfg_set(struct vf610_adc *info)
319{
320	struct vf610_adc_feature *adc_feature = &(info->adc_feature);
321	int cfg_data;
322
323	cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
324
325	cfg_data &= ~VF610_ADC_ADLPC_EN;
326	if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
327		cfg_data |= VF610_ADC_ADLPC_EN;
328
329	cfg_data &= ~VF610_ADC_ADHSC_EN;
330	if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
331		cfg_data |= VF610_ADC_ADHSC_EN;
332
333	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
334}
335
336static void vf610_adc_sample_set(struct vf610_adc *info)
337{
338	struct vf610_adc_feature *adc_feature = &(info->adc_feature);
339	int cfg_data, gc_data;
340
341	cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
342	gc_data = readl(info->regs + VF610_REG_ADC_GC);
343
344	/* resolution mode */
345	cfg_data &= ~VF610_ADC_MODE_MASK;
346	switch (adc_feature->res_mode) {
347	case 8:
348		cfg_data |= VF610_ADC_MODE_BIT8;
349		break;
350	case 10:
351		cfg_data |= VF610_ADC_MODE_BIT10;
352		break;
353	case 12:
354		cfg_data |= VF610_ADC_MODE_BIT12;
355		break;
356	default:
357		dev_err(info->dev, "error resolution mode\n");
358		break;
359	}
360
361	/* clock select and clock divider */
362	cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
363	switch (adc_feature->clk_div) {
364	case 1:
365		break;
366	case 2:
367		cfg_data |= VF610_ADC_CLK_DIV2;
368		break;
369	case 4:
370		cfg_data |= VF610_ADC_CLK_DIV4;
371		break;
372	case 8:
373		cfg_data |= VF610_ADC_CLK_DIV8;
374		break;
375	case 16:
376		switch (adc_feature->clk_sel) {
377		case VF610_ADCIOC_BUSCLK_SET:
378			cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
379			break;
380		default:
381			dev_err(info->dev, "error clk divider\n");
382			break;
383		}
384		break;
385	}
386
387	/*
388	 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
389	 * determined.
390	 */
391	switch (adc_feature->lst_adder_index) {
392	case VF610_ADCK_CYCLES_3:
393		break;
394	case VF610_ADCK_CYCLES_5:
395		cfg_data |= VF610_ADC_ADSTS_SHORT;
396		break;
397	case VF610_ADCK_CYCLES_7:
398		cfg_data |= VF610_ADC_ADSTS_NORMAL;
399		break;
400	case VF610_ADCK_CYCLES_9:
401		cfg_data |= VF610_ADC_ADSTS_LONG;
402		break;
403	case VF610_ADCK_CYCLES_13:
404		cfg_data |= VF610_ADC_ADLSMP_LONG;
405		break;
406	case VF610_ADCK_CYCLES_17:
407		cfg_data |= VF610_ADC_ADLSMP_LONG;
408		cfg_data |= VF610_ADC_ADSTS_SHORT;
409		break;
410	case VF610_ADCK_CYCLES_21:
411		cfg_data |= VF610_ADC_ADLSMP_LONG;
412		cfg_data |= VF610_ADC_ADSTS_NORMAL;
413		break;
414	case VF610_ADCK_CYCLES_25:
415		cfg_data |= VF610_ADC_ADLSMP_LONG;
416		cfg_data |= VF610_ADC_ADSTS_NORMAL;
417		break;
418	default:
419		dev_err(info->dev, "error in sample time select\n");
420	}
421
422	/* update hardware average selection */
423	cfg_data &= ~VF610_ADC_AVGS_MASK;
424	gc_data &= ~VF610_ADC_AVGEN;
425	switch (adc_feature->sample_rate) {
426	case VF610_ADC_SAMPLE_1:
427		break;
428	case VF610_ADC_SAMPLE_4:
429		gc_data |= VF610_ADC_AVGEN;
430		break;
431	case VF610_ADC_SAMPLE_8:
432		gc_data |= VF610_ADC_AVGEN;
433		cfg_data |= VF610_ADC_AVGS_8;
434		break;
435	case VF610_ADC_SAMPLE_16:
436		gc_data |= VF610_ADC_AVGEN;
437		cfg_data |= VF610_ADC_AVGS_16;
438		break;
439	case VF610_ADC_SAMPLE_32:
440		gc_data |= VF610_ADC_AVGEN;
441		cfg_data |= VF610_ADC_AVGS_32;
442		break;
443	default:
444		dev_err(info->dev,
445			"error hardware sample average select\n");
446	}
447
448	writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
449	writel(gc_data, info->regs + VF610_REG_ADC_GC);
450}
451
452static void vf610_adc_hw_init(struct vf610_adc *info)
453{
454	/* CFG: Feature set */
455	vf610_adc_cfg_post_set(info);
456	vf610_adc_sample_set(info);
457
458	/* adc calibration */
459	vf610_adc_calibration(info);
460
461	/* CFG: power and speed set */
462	vf610_adc_cfg_set(info);
463}
464
465static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
466				     const struct iio_chan_spec *chan,
467				     unsigned int mode)
468{
469	struct vf610_adc *info = iio_priv(indio_dev);
470
471	mutex_lock(&indio_dev->mlock);
472	info->adc_feature.conv_mode = mode;
473	vf610_adc_calculate_rates(info);
474	vf610_adc_hw_init(info);
475	mutex_unlock(&indio_dev->mlock);
476
477	return 0;
478}
479
480static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
481				     const struct iio_chan_spec *chan)
482{
483	struct vf610_adc *info = iio_priv(indio_dev);
484
485	return info->adc_feature.conv_mode;
486}
487
488static const char * const vf610_conv_modes[] = { "normal", "high-speed",
489						 "low-power" };
490
491static const struct iio_enum vf610_conversion_mode = {
492	.items = vf610_conv_modes,
493	.num_items = ARRAY_SIZE(vf610_conv_modes),
494	.get = vf610_get_conversion_mode,
495	.set = vf610_set_conversion_mode,
496};
497
498static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
499	IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
500	{},
501};
502
503#define VF610_ADC_CHAN(_idx, _chan_type) {			\
504	.type = (_chan_type),					\
505	.indexed = 1,						\
506	.channel = (_idx),					\
507	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
508	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
509				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
510	.ext_info = vf610_ext_info,				\
511	.scan_index = (_idx),			\
512	.scan_type = {					\
513		.sign = 'u',				\
514		.realbits = 12,				\
515		.storagebits = 16,			\
516	},						\
517}
518
519#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {	\
520	.type = (_chan_type),	\
521	.channel = (_idx),		\
522	.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),	\
523	.scan_index = (_idx),					\
524	.scan_type = {						\
525		.sign = 'u',					\
526		.realbits = 12,					\
527		.storagebits = 16,				\
528	},							\
529}
530
531static const struct iio_chan_spec vf610_adc_iio_channels[] = {
532	VF610_ADC_CHAN(0, IIO_VOLTAGE),
533	VF610_ADC_CHAN(1, IIO_VOLTAGE),
534	VF610_ADC_CHAN(2, IIO_VOLTAGE),
535	VF610_ADC_CHAN(3, IIO_VOLTAGE),
536	VF610_ADC_CHAN(4, IIO_VOLTAGE),
537	VF610_ADC_CHAN(5, IIO_VOLTAGE),
538	VF610_ADC_CHAN(6, IIO_VOLTAGE),
539	VF610_ADC_CHAN(7, IIO_VOLTAGE),
540	VF610_ADC_CHAN(8, IIO_VOLTAGE),
541	VF610_ADC_CHAN(9, IIO_VOLTAGE),
542	VF610_ADC_CHAN(10, IIO_VOLTAGE),
543	VF610_ADC_CHAN(11, IIO_VOLTAGE),
544	VF610_ADC_CHAN(12, IIO_VOLTAGE),
545	VF610_ADC_CHAN(13, IIO_VOLTAGE),
546	VF610_ADC_CHAN(14, IIO_VOLTAGE),
547	VF610_ADC_CHAN(15, IIO_VOLTAGE),
548	VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
549	IIO_CHAN_SOFT_TIMESTAMP(32),
550	/* sentinel */
551};
552
553static int vf610_adc_read_data(struct vf610_adc *info)
554{
555	int result;
556
557	result = readl(info->regs + VF610_REG_ADC_R0);
558
559	switch (info->adc_feature.res_mode) {
560	case 8:
561		result &= 0xFF;
562		break;
563	case 10:
564		result &= 0x3FF;
565		break;
566	case 12:
567		result &= 0xFFF;
568		break;
569	default:
570		break;
571	}
572
573	return result;
574}
575
576static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
577{
578	struct iio_dev *indio_dev = dev_id;
579	struct vf610_adc *info = iio_priv(indio_dev);
580	int coco;
581
582	coco = readl(info->regs + VF610_REG_ADC_HS);
583	if (coco & VF610_ADC_HS_COCO0) {
584		info->value = vf610_adc_read_data(info);
585		if (iio_buffer_enabled(indio_dev)) {
586			info->scan.chan = info->value;
587			iio_push_to_buffers_with_timestamp(indio_dev,
588					&info->scan,
589					iio_get_time_ns(indio_dev));
590			iio_trigger_notify_done(indio_dev->trig);
591		} else
592			complete(&info->completion);
593	}
594
595	return IRQ_HANDLED;
596}
597
598static ssize_t vf610_show_samp_freq_avail(struct device *dev,
599				struct device_attribute *attr, char *buf)
600{
601	struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
602	size_t len = 0;
603	int i;
604
605	for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
606		len += scnprintf(buf + len, PAGE_SIZE - len,
607			"%u ", info->sample_freq_avail[i]);
608
609	/* replace trailing space by newline */
610	buf[len - 1] = '\n';
611
612	return len;
613}
614
615static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
616
617static struct attribute *vf610_attributes[] = {
618	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
619	NULL
620};
621
622static const struct attribute_group vf610_attribute_group = {
623	.attrs = vf610_attributes,
624};
625
626static int vf610_read_raw(struct iio_dev *indio_dev,
627			struct iio_chan_spec const *chan,
628			int *val,
629			int *val2,
630			long mask)
631{
632	struct vf610_adc *info = iio_priv(indio_dev);
633	unsigned int hc_cfg;
634	long ret;
635
636	switch (mask) {
637	case IIO_CHAN_INFO_RAW:
638	case IIO_CHAN_INFO_PROCESSED:
639		mutex_lock(&indio_dev->mlock);
640		if (iio_buffer_enabled(indio_dev)) {
641			mutex_unlock(&indio_dev->mlock);
642			return -EBUSY;
643		}
644
645		reinit_completion(&info->completion);
646		hc_cfg = VF610_ADC_ADCHC(chan->channel);
647		hc_cfg |= VF610_ADC_AIEN;
648		writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
649		ret = wait_for_completion_interruptible_timeout
650				(&info->completion, VF610_ADC_TIMEOUT);
651		if (ret == 0) {
652			mutex_unlock(&indio_dev->mlock);
653			return -ETIMEDOUT;
654		}
655		if (ret < 0) {
656			mutex_unlock(&indio_dev->mlock);
657			return ret;
658		}
659
660		switch (chan->type) {
661		case IIO_VOLTAGE:
662			*val = info->value;
663			break;
664		case IIO_TEMP:
665			/*
666			 * Calculate in degree Celsius times 1000
667			 * Using the typical sensor slope of 1.84 mV/°C
668			 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
669			 */
670			*val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
671					1000000 / VF610_TEMP_SLOPE_COEFF;
672
673			break;
674		default:
675			mutex_unlock(&indio_dev->mlock);
676			return -EINVAL;
677		}
678
679		mutex_unlock(&indio_dev->mlock);
680		return IIO_VAL_INT;
681
682	case IIO_CHAN_INFO_SCALE:
683		*val = info->vref_uv / 1000;
684		*val2 = info->adc_feature.res_mode;
685		return IIO_VAL_FRACTIONAL_LOG2;
686
687	case IIO_CHAN_INFO_SAMP_FREQ:
688		*val = info->sample_freq_avail[info->adc_feature.sample_rate];
689		*val2 = 0;
690		return IIO_VAL_INT;
691
692	default:
693		break;
694	}
695
696	return -EINVAL;
697}
698
699static int vf610_write_raw(struct iio_dev *indio_dev,
700			struct iio_chan_spec const *chan,
701			int val,
702			int val2,
703			long mask)
704{
705	struct vf610_adc *info = iio_priv(indio_dev);
706	int i;
707
708	switch (mask) {
709	case IIO_CHAN_INFO_SAMP_FREQ:
710		for (i = 0;
711			i < ARRAY_SIZE(info->sample_freq_avail);
712			i++)
713			if (val == info->sample_freq_avail[i]) {
714				info->adc_feature.sample_rate = i;
715				vf610_adc_sample_set(info);
716				return 0;
717			}
718		break;
719
720	default:
721		break;
722	}
723
724	return -EINVAL;
725}
726
727static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
728{
729	struct vf610_adc *info = iio_priv(indio_dev);
730	unsigned int channel;
731	int val;
732
733	val = readl(info->regs + VF610_REG_ADC_GC);
734	val |= VF610_ADC_ADCON;
735	writel(val, info->regs + VF610_REG_ADC_GC);
736
737	channel = find_first_bit(indio_dev->active_scan_mask,
738						indio_dev->masklength);
739
740	val = VF610_ADC_ADCHC(channel);
741	val |= VF610_ADC_AIEN;
742
743	writel(val, info->regs + VF610_REG_ADC_HC0);
744
745	return 0;
746}
747
748static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
749{
750	struct vf610_adc *info = iio_priv(indio_dev);
751	unsigned int hc_cfg = 0;
752	int val;
753
754	val = readl(info->regs + VF610_REG_ADC_GC);
755	val &= ~VF610_ADC_ADCON;
756	writel(val, info->regs + VF610_REG_ADC_GC);
757
758	hc_cfg |= VF610_ADC_CONV_DISABLE;
759	hc_cfg &= ~VF610_ADC_AIEN;
760
761	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
762
763	return 0;
764}
765
766static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
767	.postenable = &vf610_adc_buffer_postenable,
768	.predisable = &vf610_adc_buffer_predisable,
769	.validate_scan_mask = &iio_validate_scan_mask_onehot,
770};
771
772static int vf610_adc_reg_access(struct iio_dev *indio_dev,
773			unsigned reg, unsigned writeval,
774			unsigned *readval)
775{
776	struct vf610_adc *info = iio_priv(indio_dev);
777
778	if ((readval == NULL) ||
779		((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
780		return -EINVAL;
781
782	*readval = readl(info->regs + reg);
783
784	return 0;
785}
786
787static const struct iio_info vf610_adc_iio_info = {
788	.read_raw = &vf610_read_raw,
789	.write_raw = &vf610_write_raw,
790	.debugfs_reg_access = &vf610_adc_reg_access,
791	.attrs = &vf610_attribute_group,
792};
793
794static const struct of_device_id vf610_adc_match[] = {
795	{ .compatible = "fsl,vf610-adc", },
796	{ /* sentinel */ }
797};
798MODULE_DEVICE_TABLE(of, vf610_adc_match);
799
800static int vf610_adc_probe(struct platform_device *pdev)
801{
802	struct vf610_adc *info;
803	struct iio_dev *indio_dev;
804	int irq;
805	int ret;
806
807	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
808	if (!indio_dev) {
809		dev_err(&pdev->dev, "Failed allocating iio device\n");
810		return -ENOMEM;
811	}
812
813	info = iio_priv(indio_dev);
814	info->dev = &pdev->dev;
815
816	info->regs = devm_platform_ioremap_resource(pdev, 0);
817	if (IS_ERR(info->regs))
818		return PTR_ERR(info->regs);
819
820	irq = platform_get_irq(pdev, 0);
821	if (irq < 0)
822		return irq;
823
824	ret = devm_request_irq(info->dev, irq,
825				vf610_adc_isr, 0,
826				dev_name(&pdev->dev), indio_dev);
827	if (ret < 0) {
828		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
829		return ret;
830	}
831
832	info->clk = devm_clk_get(&pdev->dev, "adc");
833	if (IS_ERR(info->clk)) {
834		dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
835						PTR_ERR(info->clk));
836		return PTR_ERR(info->clk);
837	}
838
839	info->vref = devm_regulator_get(&pdev->dev, "vref");
840	if (IS_ERR(info->vref))
841		return PTR_ERR(info->vref);
842
843	ret = regulator_enable(info->vref);
844	if (ret)
845		return ret;
846
847	info->vref_uv = regulator_get_voltage(info->vref);
848
849	of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
850			info->max_adck_rate, 3);
851
852	ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
853			&info->adc_feature.default_sample_time);
854	if (ret)
855		info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
856
857	platform_set_drvdata(pdev, indio_dev);
858
859	init_completion(&info->completion);
860
861	indio_dev->name = dev_name(&pdev->dev);
862	indio_dev->info = &vf610_adc_iio_info;
863	indio_dev->modes = INDIO_DIRECT_MODE;
864	indio_dev->channels = vf610_adc_iio_channels;
865	indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
866
867	ret = clk_prepare_enable(info->clk);
868	if (ret) {
869		dev_err(&pdev->dev,
870			"Could not prepare or enable the clock.\n");
871		goto error_adc_clk_enable;
872	}
873
874	vf610_adc_cfg_init(info);
875	vf610_adc_hw_init(info);
876
877	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
878					NULL, &iio_triggered_buffer_setup_ops);
879	if (ret < 0) {
880		dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
881		goto error_iio_device_register;
882	}
883
884	ret = iio_device_register(indio_dev);
885	if (ret) {
886		dev_err(&pdev->dev, "Couldn't register the device.\n");
887		goto error_adc_buffer_init;
888	}
889
890	return 0;
891
892error_adc_buffer_init:
893	iio_triggered_buffer_cleanup(indio_dev);
894error_iio_device_register:
895	clk_disable_unprepare(info->clk);
896error_adc_clk_enable:
897	regulator_disable(info->vref);
898
899	return ret;
900}
901
902static int vf610_adc_remove(struct platform_device *pdev)
903{
904	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
905	struct vf610_adc *info = iio_priv(indio_dev);
906
907	iio_device_unregister(indio_dev);
908	iio_triggered_buffer_cleanup(indio_dev);
909	regulator_disable(info->vref);
910	clk_disable_unprepare(info->clk);
911
912	return 0;
913}
914
915#ifdef CONFIG_PM_SLEEP
916static int vf610_adc_suspend(struct device *dev)
917{
918	struct iio_dev *indio_dev = dev_get_drvdata(dev);
919	struct vf610_adc *info = iio_priv(indio_dev);
920	int hc_cfg;
921
922	/* ADC controller enters to stop mode */
923	hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
924	hc_cfg |= VF610_ADC_CONV_DISABLE;
925	writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
926
927	clk_disable_unprepare(info->clk);
928	regulator_disable(info->vref);
929
930	return 0;
931}
932
933static int vf610_adc_resume(struct device *dev)
934{
935	struct iio_dev *indio_dev = dev_get_drvdata(dev);
936	struct vf610_adc *info = iio_priv(indio_dev);
937	int ret;
938
939	ret = regulator_enable(info->vref);
940	if (ret)
941		return ret;
942
943	ret = clk_prepare_enable(info->clk);
944	if (ret)
945		goto disable_reg;
946
947	vf610_adc_hw_init(info);
948
949	return 0;
950
951disable_reg:
952	regulator_disable(info->vref);
953	return ret;
954}
955#endif
956
957static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
958
959static struct platform_driver vf610_adc_driver = {
960	.probe          = vf610_adc_probe,
961	.remove         = vf610_adc_remove,
962	.driver         = {
963		.name   = DRIVER_NAME,
964		.of_match_table = vf610_adc_match,
965		.pm     = &vf610_adc_pm_ops,
966	},
967};
968
969module_platform_driver(vf610_adc_driver);
970
971MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
972MODULE_DESCRIPTION("Freescale VF610 ADC driver");
973MODULE_LICENSE("GPL v2");
974