1/* 2 * TI ADC MFD driver 3 * 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/err.h> 18#include <linux/module.h> 19#include <linux/slab.h> 20#include <linux/interrupt.h> 21#include <linux/platform_device.h> 22#include <linux/io.h> 23#include <linux/iio/iio.h> 24#include <linux/of.h> 25#include <linux/of_device.h> 26#include <linux/iio/machine.h> 27#include <linux/iio/driver.h> 28 29#include <linux/mfd/ti_am335x_tscadc.h> 30#include <linux/iio/buffer.h> 31#include <linux/iio/kfifo_buf.h> 32 33#include <linux/dmaengine.h> 34#include <linux/dma-mapping.h> 35 36#define DMA_BUFFER_SIZE SZ_2K 37 38struct tiadc_dma { 39 struct dma_slave_config conf; 40 struct dma_chan *chan; 41 dma_addr_t addr; 42 dma_cookie_t cookie; 43 u8 *buf; 44 int current_period; 45 int period_size; 46 u8 fifo_thresh; 47}; 48 49struct tiadc_device { 50 struct ti_tscadc_dev *mfd_tscadc; 51 struct tiadc_dma dma; 52 struct mutex fifo1_lock; /* to protect fifo access */ 53 int channels; 54 int total_ch_enabled; 55 u8 channel_line[8]; 56 u8 channel_step[8]; 57 int buffer_en_ch_steps; 58 u16 data[8]; 59 u32 open_delay[8], sample_delay[8], step_avg[8]; 60}; 61 62static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) 63{ 64 return readl(adc->mfd_tscadc->tscadc_base + reg); 65} 66 67static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, 68 unsigned int val) 69{ 70 writel(val, adc->mfd_tscadc->tscadc_base + reg); 71} 72 73static u32 get_adc_step_mask(struct tiadc_device *adc_dev) 74{ 75 u32 step_en; 76 77 step_en = ((1 << adc_dev->channels) - 1); 78 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; 79 return step_en; 80} 81 82static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, 83 struct iio_chan_spec const *chan) 84{ 85 int i; 86 87 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { 88 if (chan->channel == adc_dev->channel_line[i]) { 89 u32 step; 90 91 step = adc_dev->channel_step[i]; 92 /* +1 for the charger */ 93 return 1 << (step + 1); 94 } 95 } 96 WARN_ON(1); 97 return 0; 98} 99 100static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) 101{ 102 return 1 << adc_dev->channel_step[chan]; 103} 104 105static void tiadc_step_config(struct iio_dev *indio_dev) 106{ 107 struct tiadc_device *adc_dev = iio_priv(indio_dev); 108 struct device *dev = adc_dev->mfd_tscadc->dev; 109 unsigned int stepconfig; 110 int i, steps = 0; 111 112 /* 113 * There are 16 configurable steps and 8 analog input 114 * lines available which are shared between Touchscreen and ADC. 115 * 116 * Steps forwards i.e. from 0 towards 16 are used by ADC 117 * depending on number of input lines needed. 118 * Channel would represent which analog input 119 * needs to be given to ADC to digitalize data. 120 */ 121 122 123 for (i = 0; i < adc_dev->channels; i++) { 124 int chan; 125 126 chan = adc_dev->channel_line[i]; 127 128 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { 129 dev_warn(dev, "chan %d step_avg truncating to %d\n", 130 chan, STEPCONFIG_AVG_16); 131 adc_dev->step_avg[i] = STEPCONFIG_AVG_16; 132 } 133 134 if (adc_dev->step_avg[i]) 135 stepconfig = 136 STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | 137 STEPCONFIG_FIFO1; 138 else 139 stepconfig = STEPCONFIG_FIFO1; 140 141 if (iio_buffer_enabled(indio_dev)) 142 stepconfig |= STEPCONFIG_MODE_SWCNT; 143 144 tiadc_writel(adc_dev, REG_STEPCONFIG(steps), 145 stepconfig | STEPCONFIG_INP(chan) | 146 STEPCONFIG_INM_ADCREFM | 147 STEPCONFIG_RFP_VREFP | 148 STEPCONFIG_RFM_VREFN); 149 150 if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) { 151 dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n", 152 chan); 153 adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK; 154 } 155 156 if (adc_dev->sample_delay[i] > 0xFF) { 157 dev_warn(dev, "chan %d sample delay truncating to 0xFF\n", 158 chan); 159 adc_dev->sample_delay[i] = 0xFF; 160 } 161 162 tiadc_writel(adc_dev, REG_STEPDELAY(steps), 163 STEPDELAY_OPEN(adc_dev->open_delay[i]) | 164 STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); 165 166 adc_dev->channel_step[i] = steps; 167 steps++; 168 } 169} 170 171static irqreturn_t tiadc_irq_h(int irq, void *private) 172{ 173 struct iio_dev *indio_dev = private; 174 struct tiadc_device *adc_dev = iio_priv(indio_dev); 175 unsigned int status, config, adc_fsm; 176 unsigned short count = 0; 177 178 status = tiadc_readl(adc_dev, REG_IRQSTATUS); 179 180 /* 181 * ADC and touchscreen share the IRQ line. 182 * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only 183 */ 184 if (status & IRQENB_FIFO1OVRRUN) { 185 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ 186 config = tiadc_readl(adc_dev, REG_CTRL); 187 config &= ~(CNTRLREG_TSCSSENB); 188 tiadc_writel(adc_dev, REG_CTRL, config); 189 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN 190 | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES); 191 192 /* wait for idle state. 193 * ADC needs to finish the current conversion 194 * before disabling the module 195 */ 196 do { 197 adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM); 198 } while (adc_fsm != 0x10 && count++ < 100); 199 200 tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB)); 201 return IRQ_HANDLED; 202 } else if (status & IRQENB_FIFO1THRES) { 203 /* Disable irq and wake worker thread */ 204 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); 205 return IRQ_WAKE_THREAD; 206 } 207 208 return IRQ_NONE; 209} 210 211static irqreturn_t tiadc_worker_h(int irq, void *private) 212{ 213 struct iio_dev *indio_dev = private; 214 struct tiadc_device *adc_dev = iio_priv(indio_dev); 215 int i, k, fifo1count, read; 216 u16 *data = adc_dev->data; 217 218 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 219 for (k = 0; k < fifo1count; k = k + i) { 220 for (i = 0; i < (indio_dev->scan_bytes)/2; i++) { 221 read = tiadc_readl(adc_dev, REG_FIFO1); 222 data[i] = read & FIFOREAD_DATA_MASK; 223 } 224 iio_push_to_buffers(indio_dev, (u8 *) data); 225 } 226 227 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); 228 tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); 229 230 return IRQ_HANDLED; 231} 232 233static void tiadc_dma_rx_complete(void *param) 234{ 235 struct iio_dev *indio_dev = param; 236 struct tiadc_device *adc_dev = iio_priv(indio_dev); 237 struct tiadc_dma *dma = &adc_dev->dma; 238 u8 *data; 239 int i; 240 241 data = dma->buf + dma->current_period * dma->period_size; 242 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */ 243 244 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) { 245 iio_push_to_buffers(indio_dev, data); 246 data += indio_dev->scan_bytes; 247 } 248} 249 250static int tiadc_start_dma(struct iio_dev *indio_dev) 251{ 252 struct tiadc_device *adc_dev = iio_priv(indio_dev); 253 struct tiadc_dma *dma = &adc_dev->dma; 254 struct dma_async_tx_descriptor *desc; 255 256 dma->current_period = 0; /* We start to fill period 0 */ 257 /* 258 * Make the fifo thresh as the multiple of total number of 259 * channels enabled, so make sure that cyclic DMA period 260 * length is also a multiple of total number of channels 261 * enabled. This ensures that no invalid data is reported 262 * to the stack via iio_push_to_buffers(). 263 */ 264 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, 265 adc_dev->total_ch_enabled) - 1; 266 /* Make sure that period length is multiple of fifo thresh level */ 267 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, 268 (dma->fifo_thresh + 1) * sizeof(u16)); 269 270 dma->conf.src_maxburst = dma->fifo_thresh + 1; 271 dmaengine_slave_config(dma->chan, &dma->conf); 272 273 desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr, 274 dma->period_size * 2, 275 dma->period_size, DMA_DEV_TO_MEM, 276 DMA_PREP_INTERRUPT); 277 if (!desc) 278 return -EBUSY; 279 280 desc->callback = tiadc_dma_rx_complete; 281 desc->callback_param = indio_dev; 282 283 dma->cookie = dmaengine_submit(desc); 284 285 dma_async_issue_pending(dma->chan); 286 287 tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh); 288 tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh); 289 tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1); 290 291 return 0; 292} 293 294static int tiadc_buffer_preenable(struct iio_dev *indio_dev) 295{ 296 struct tiadc_device *adc_dev = iio_priv(indio_dev); 297 int i, fifo1count; 298 299 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 300 IRQENB_FIFO1OVRRUN | 301 IRQENB_FIFO1UNDRFLW)); 302 303 /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ 304 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 305 for (i = 0; i < fifo1count; i++) 306 tiadc_readl(adc_dev, REG_FIFO1); 307 308 return 0; 309} 310 311static int tiadc_buffer_postenable(struct iio_dev *indio_dev) 312{ 313 struct tiadc_device *adc_dev = iio_priv(indio_dev); 314 struct tiadc_dma *dma = &adc_dev->dma; 315 unsigned int irq_enable; 316 unsigned int enb = 0; 317 u8 bit; 318 319 tiadc_step_config(indio_dev); 320 for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) { 321 enb |= (get_adc_step_bit(adc_dev, bit) << 1); 322 adc_dev->total_ch_enabled++; 323 } 324 adc_dev->buffer_en_ch_steps = enb; 325 326 if (dma->chan) 327 tiadc_start_dma(indio_dev); 328 329 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); 330 331 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES 332 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW); 333 334 irq_enable = IRQENB_FIFO1OVRRUN; 335 if (!dma->chan) 336 irq_enable |= IRQENB_FIFO1THRES; 337 tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable); 338 339 return 0; 340} 341 342static int tiadc_buffer_predisable(struct iio_dev *indio_dev) 343{ 344 struct tiadc_device *adc_dev = iio_priv(indio_dev); 345 struct tiadc_dma *dma = &adc_dev->dma; 346 int fifo1count, i; 347 348 tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES | 349 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW)); 350 am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); 351 adc_dev->buffer_en_ch_steps = 0; 352 adc_dev->total_ch_enabled = 0; 353 if (dma->chan) { 354 tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2); 355 dmaengine_terminate_async(dma->chan); 356 } 357 358 /* Flush FIFO of leftover data in the time it takes to disable adc */ 359 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 360 for (i = 0; i < fifo1count; i++) 361 tiadc_readl(adc_dev, REG_FIFO1); 362 363 return 0; 364} 365 366static int tiadc_buffer_postdisable(struct iio_dev *indio_dev) 367{ 368 tiadc_step_config(indio_dev); 369 370 return 0; 371} 372 373static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { 374 .preenable = &tiadc_buffer_preenable, 375 .postenable = &tiadc_buffer_postenable, 376 .predisable = &tiadc_buffer_predisable, 377 .postdisable = &tiadc_buffer_postdisable, 378}; 379 380static int tiadc_iio_buffered_hardware_setup(struct device *dev, 381 struct iio_dev *indio_dev, 382 irqreturn_t (*pollfunc_bh)(int irq, void *p), 383 irqreturn_t (*pollfunc_th)(int irq, void *p), 384 int irq, 385 unsigned long flags, 386 const struct iio_buffer_setup_ops *setup_ops) 387{ 388 struct iio_buffer *buffer; 389 int ret; 390 391 buffer = devm_iio_kfifo_allocate(dev); 392 if (!buffer) 393 return -ENOMEM; 394 395 iio_device_attach_buffer(indio_dev, buffer); 396 397 ret = devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh, 398 flags, indio_dev->name, indio_dev); 399 if (ret) 400 return ret; 401 402 indio_dev->setup_ops = setup_ops; 403 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 404 405 return 0; 406} 407 408static const char * const chan_name_ain[] = { 409 "AIN0", 410 "AIN1", 411 "AIN2", 412 "AIN3", 413 "AIN4", 414 "AIN5", 415 "AIN6", 416 "AIN7", 417}; 418 419static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev, 420 int channels) 421{ 422 struct tiadc_device *adc_dev = iio_priv(indio_dev); 423 struct iio_chan_spec *chan_array; 424 struct iio_chan_spec *chan; 425 int i; 426 427 indio_dev->num_channels = channels; 428 chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array), 429 GFP_KERNEL); 430 if (chan_array == NULL) 431 return -ENOMEM; 432 433 chan = chan_array; 434 for (i = 0; i < channels; i++, chan++) { 435 436 chan->type = IIO_VOLTAGE; 437 chan->indexed = 1; 438 chan->channel = adc_dev->channel_line[i]; 439 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 440 chan->datasheet_name = chan_name_ain[chan->channel]; 441 chan->scan_index = i; 442 chan->scan_type.sign = 'u'; 443 chan->scan_type.realbits = 12; 444 chan->scan_type.storagebits = 16; 445 } 446 447 indio_dev->channels = chan_array; 448 449 return 0; 450} 451 452static int tiadc_read_raw(struct iio_dev *indio_dev, 453 struct iio_chan_spec const *chan, 454 int *val, int *val2, long mask) 455{ 456 struct tiadc_device *adc_dev = iio_priv(indio_dev); 457 int ret = IIO_VAL_INT; 458 int i, map_val; 459 unsigned int fifo1count, read, stepid; 460 bool found = false; 461 u32 step_en; 462 unsigned long timeout; 463 464 if (iio_buffer_enabled(indio_dev)) 465 return -EBUSY; 466 467 step_en = get_adc_chan_step_mask(adc_dev, chan); 468 if (!step_en) 469 return -EINVAL; 470 471 mutex_lock(&adc_dev->fifo1_lock); 472 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 473 while (fifo1count--) 474 tiadc_readl(adc_dev, REG_FIFO1); 475 476 am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); 477 478 timeout = jiffies + msecs_to_jiffies 479 (IDLE_TIMEOUT * adc_dev->channels); 480 /* Wait for Fifo threshold interrupt */ 481 while (1) { 482 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 483 if (fifo1count) 484 break; 485 486 if (time_after(jiffies, timeout)) { 487 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 488 ret = -EAGAIN; 489 goto err_unlock; 490 } 491 } 492 map_val = adc_dev->channel_step[chan->scan_index]; 493 494 /* 495 * We check the complete FIFO. We programmed just one entry but in case 496 * something went wrong we left empty handed (-EAGAIN previously) and 497 * then the value apeared somehow in the FIFO we would have two entries. 498 * Therefore we read every item and keep only the latest version of the 499 * requested channel. 500 */ 501 for (i = 0; i < fifo1count; i++) { 502 read = tiadc_readl(adc_dev, REG_FIFO1); 503 stepid = read & FIFOREAD_CHNLID_MASK; 504 stepid = stepid >> 0x10; 505 506 if (stepid == map_val) { 507 read = read & FIFOREAD_DATA_MASK; 508 found = true; 509 *val = (u16) read; 510 } 511 } 512 am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); 513 514 if (!found) 515 ret = -EBUSY; 516 517err_unlock: 518 mutex_unlock(&adc_dev->fifo1_lock); 519 return ret; 520} 521 522static const struct iio_info tiadc_info = { 523 .read_raw = &tiadc_read_raw, 524}; 525 526static int tiadc_request_dma(struct platform_device *pdev, 527 struct tiadc_device *adc_dev) 528{ 529 struct tiadc_dma *dma = &adc_dev->dma; 530 dma_cap_mask_t mask; 531 532 /* Default slave configuration parameters */ 533 dma->conf.direction = DMA_DEV_TO_MEM; 534 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 535 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1; 536 537 dma_cap_zero(mask); 538 dma_cap_set(DMA_CYCLIC, mask); 539 540 /* Get a channel for RX */ 541 dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1"); 542 if (IS_ERR(dma->chan)) { 543 int ret = PTR_ERR(dma->chan); 544 545 dma->chan = NULL; 546 return ret; 547 } 548 549 /* RX buffer */ 550 dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 551 &dma->addr, GFP_KERNEL); 552 if (!dma->buf) 553 goto err; 554 555 return 0; 556err: 557 dma_release_channel(dma->chan); 558 return -ENOMEM; 559} 560 561static int tiadc_parse_dt(struct platform_device *pdev, 562 struct tiadc_device *adc_dev) 563{ 564 struct device_node *node = pdev->dev.of_node; 565 struct property *prop; 566 const __be32 *cur; 567 int channels = 0; 568 u32 val; 569 570 of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { 571 adc_dev->channel_line[channels] = val; 572 573 /* Set Default values for optional DT parameters */ 574 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; 575 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; 576 adc_dev->step_avg[channels] = 16; 577 578 channels++; 579 } 580 581 of_property_read_u32_array(node, "ti,chan-step-avg", 582 adc_dev->step_avg, channels); 583 of_property_read_u32_array(node, "ti,chan-step-opendelay", 584 adc_dev->open_delay, channels); 585 of_property_read_u32_array(node, "ti,chan-step-sampledelay", 586 adc_dev->sample_delay, channels); 587 588 adc_dev->channels = channels; 589 return 0; 590} 591 592static int tiadc_probe(struct platform_device *pdev) 593{ 594 struct iio_dev *indio_dev; 595 struct tiadc_device *adc_dev; 596 struct device_node *node = pdev->dev.of_node; 597 int err; 598 599 if (!node) { 600 dev_err(&pdev->dev, "Could not find valid DT data.\n"); 601 return -EINVAL; 602 } 603 604 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); 605 if (indio_dev == NULL) { 606 dev_err(&pdev->dev, "failed to allocate iio device\n"); 607 return -ENOMEM; 608 } 609 adc_dev = iio_priv(indio_dev); 610 611 adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev); 612 tiadc_parse_dt(pdev, adc_dev); 613 614 indio_dev->name = dev_name(&pdev->dev); 615 indio_dev->modes = INDIO_DIRECT_MODE; 616 indio_dev->info = &tiadc_info; 617 618 tiadc_step_config(indio_dev); 619 tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD); 620 mutex_init(&adc_dev->fifo1_lock); 621 622 err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels); 623 if (err < 0) 624 return err; 625 626 err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev, 627 &tiadc_worker_h, 628 &tiadc_irq_h, 629 adc_dev->mfd_tscadc->irq, 630 IRQF_SHARED, 631 &tiadc_buffer_setup_ops); 632 633 if (err) 634 goto err_free_channels; 635 636 err = iio_device_register(indio_dev); 637 if (err) 638 goto err_buffer_unregister; 639 640 platform_set_drvdata(pdev, indio_dev); 641 642 err = tiadc_request_dma(pdev, adc_dev); 643 if (err && err != -ENODEV) { 644 dev_err_probe(&pdev->dev, err, "DMA request failed\n"); 645 goto err_dma; 646 } 647 648 return 0; 649 650err_dma: 651 iio_device_unregister(indio_dev); 652err_buffer_unregister: 653err_free_channels: 654 return err; 655} 656 657static int tiadc_remove(struct platform_device *pdev) 658{ 659 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 660 struct tiadc_device *adc_dev = iio_priv(indio_dev); 661 struct tiadc_dma *dma = &adc_dev->dma; 662 u32 step_en; 663 664 if (dma->chan) { 665 dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, 666 dma->buf, dma->addr); 667 dma_release_channel(dma->chan); 668 } 669 iio_device_unregister(indio_dev); 670 671 step_en = get_adc_step_mask(adc_dev); 672 am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); 673 674 return 0; 675} 676 677static int __maybe_unused tiadc_suspend(struct device *dev) 678{ 679 struct iio_dev *indio_dev = dev_get_drvdata(dev); 680 struct tiadc_device *adc_dev = iio_priv(indio_dev); 681 unsigned int idle; 682 683 idle = tiadc_readl(adc_dev, REG_CTRL); 684 idle &= ~(CNTRLREG_TSCSSENB); 685 tiadc_writel(adc_dev, REG_CTRL, (idle | 686 CNTRLREG_POWERDOWN)); 687 688 return 0; 689} 690 691static int __maybe_unused tiadc_resume(struct device *dev) 692{ 693 struct iio_dev *indio_dev = dev_get_drvdata(dev); 694 struct tiadc_device *adc_dev = iio_priv(indio_dev); 695 unsigned int restore; 696 697 /* Make sure ADC is powered up */ 698 restore = tiadc_readl(adc_dev, REG_CTRL); 699 restore &= ~(CNTRLREG_POWERDOWN); 700 tiadc_writel(adc_dev, REG_CTRL, restore); 701 702 tiadc_step_config(indio_dev); 703 am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, 704 adc_dev->buffer_en_ch_steps); 705 return 0; 706} 707 708static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); 709 710static const struct of_device_id ti_adc_dt_ids[] = { 711 { .compatible = "ti,am3359-adc", }, 712 { } 713}; 714MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); 715 716static struct platform_driver tiadc_driver = { 717 .driver = { 718 .name = "TI-am335x-adc", 719 .pm = &tiadc_pm_ops, 720 .of_match_table = ti_adc_dt_ids, 721 }, 722 .probe = tiadc_probe, 723 .remove = tiadc_remove, 724}; 725module_platform_driver(tiadc_driver); 726 727MODULE_DESCRIPTION("TI ADC controller driver"); 728MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); 729MODULE_LICENSE("GPL"); 730