1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9#include <linux/clk.h> 10#include <linux/delay.h> 11#include <linux/dma-mapping.h> 12#include <linux/dmaengine.h> 13#include <linux/iio/iio.h> 14#include <linux/iio/buffer.h> 15#include <linux/iio/timer/stm32-lptim-trigger.h> 16#include <linux/iio/timer/stm32-timer-trigger.h> 17#include <linux/iio/trigger.h> 18#include <linux/iio/trigger_consumer.h> 19#include <linux/iio/triggered_buffer.h> 20#include <linux/interrupt.h> 21#include <linux/io.h> 22#include <linux/iopoll.h> 23#include <linux/module.h> 24#include <linux/platform_device.h> 25#include <linux/pm_runtime.h> 26#include <linux/of.h> 27#include <linux/of_device.h> 28 29#include "stm32-adc-core.h" 30 31/* Number of linear calibration shadow registers / LINCALRDYW control bits */ 32#define STM32H7_LINCALFACT_NUM 6 33 34/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 35#define STM32H7_BOOST_CLKRATE 20000000UL 36 37#define STM32_ADC_CH_MAX 20 /* max number of channels */ 38#define STM32_ADC_CH_SZ 10 /* max channel name size */ 39#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 40#define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 41#define STM32_ADC_TIMEOUT_US 100000 42#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 43#define STM32_ADC_HW_STOP_DELAY_MS 100 44 45#define STM32_DMA_BUFFER_SIZE PAGE_SIZE 46 47/* External trigger enable */ 48enum stm32_adc_exten { 49 STM32_EXTEN_SWTRIG, 50 STM32_EXTEN_HWTRIG_RISING_EDGE, 51 STM32_EXTEN_HWTRIG_FALLING_EDGE, 52 STM32_EXTEN_HWTRIG_BOTH_EDGES, 53}; 54 55/* extsel - trigger mux selection value */ 56enum stm32_adc_extsel { 57 STM32_EXT0, 58 STM32_EXT1, 59 STM32_EXT2, 60 STM32_EXT3, 61 STM32_EXT4, 62 STM32_EXT5, 63 STM32_EXT6, 64 STM32_EXT7, 65 STM32_EXT8, 66 STM32_EXT9, 67 STM32_EXT10, 68 STM32_EXT11, 69 STM32_EXT12, 70 STM32_EXT13, 71 STM32_EXT14, 72 STM32_EXT15, 73 STM32_EXT16, 74 STM32_EXT17, 75 STM32_EXT18, 76 STM32_EXT19, 77 STM32_EXT20, 78}; 79 80/** 81 * struct stm32_adc_trig_info - ADC trigger info 82 * @name: name of the trigger, corresponding to its source 83 * @extsel: trigger selection 84 */ 85struct stm32_adc_trig_info { 86 const char *name; 87 enum stm32_adc_extsel extsel; 88}; 89 90/** 91 * struct stm32_adc_calib - optional adc calibration data 92 * @calfact_s: Calibration offset for single ended channels 93 * @calfact_d: Calibration offset in differential 94 * @lincalfact: Linearity calibration factor 95 * @calibrated: Indicates calibration status 96 */ 97struct stm32_adc_calib { 98 u32 calfact_s; 99 u32 calfact_d; 100 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 101 bool calibrated; 102}; 103 104/** 105 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc 106 * @reg: register offset 107 * @mask: bitfield mask 108 * @shift: left shift 109 */ 110struct stm32_adc_regs { 111 int reg; 112 int mask; 113 int shift; 114}; 115 116/** 117 * struct stm32_adc_regspec - stm32 registers definition 118 * @dr: data register offset 119 * @ier_eoc: interrupt enable register & eocie bitfield 120 * @ier_ovr: interrupt enable register & overrun bitfield 121 * @isr_eoc: interrupt status register & eoc bitfield 122 * @isr_ovr: interrupt status register & overrun bitfield 123 * @sqr: reference to sequence registers array 124 * @exten: trigger control register & bitfield 125 * @extsel: trigger selection register & bitfield 126 * @res: resolution selection register & bitfield 127 * @smpr: smpr1 & smpr2 registers offset array 128 * @smp_bits: smpr1 & smpr2 index and bitfields 129 */ 130struct stm32_adc_regspec { 131 const u32 dr; 132 const struct stm32_adc_regs ier_eoc; 133 const struct stm32_adc_regs ier_ovr; 134 const struct stm32_adc_regs isr_eoc; 135 const struct stm32_adc_regs isr_ovr; 136 const struct stm32_adc_regs *sqr; 137 const struct stm32_adc_regs exten; 138 const struct stm32_adc_regs extsel; 139 const struct stm32_adc_regs res; 140 const u32 smpr[2]; 141 const struct stm32_adc_regs *smp_bits; 142}; 143 144struct stm32_adc; 145 146/** 147 * struct stm32_adc_cfg - stm32 compatible configuration data 148 * @regs: registers descriptions 149 * @adc_info: per instance input channels definitions 150 * @trigs: external trigger sources 151 * @clk_required: clock is required 152 * @has_vregready: vregready status flag presence 153 * @prepare: optional prepare routine (power-up, enable) 154 * @start_conv: routine to start conversions 155 * @stop_conv: routine to stop conversions 156 * @unprepare: optional unprepare routine (disable, power-down) 157 * @irq_clear: routine to clear irqs 158 * @smp_cycles: programmable sampling time (ADC clock cycles) 159 */ 160struct stm32_adc_cfg { 161 const struct stm32_adc_regspec *regs; 162 const struct stm32_adc_info *adc_info; 163 struct stm32_adc_trig_info *trigs; 164 bool clk_required; 165 bool has_vregready; 166 int (*prepare)(struct iio_dev *); 167 void (*start_conv)(struct iio_dev *, bool dma); 168 void (*stop_conv)(struct iio_dev *); 169 void (*unprepare)(struct iio_dev *); 170 void (*irq_clear)(struct iio_dev *indio_dev, u32 msk); 171 const unsigned int *smp_cycles; 172}; 173 174/** 175 * struct stm32_adc - private data of each ADC IIO instance 176 * @common: reference to ADC block common data 177 * @offset: ADC instance register offset in ADC block 178 * @cfg: compatible configuration data 179 * @completion: end of single conversion completion 180 * @buffer: data buffer 181 * @clk: clock for this adc instance 182 * @irq: interrupt for this adc instance 183 * @lock: spinlock 184 * @bufi: data buffer index 185 * @num_conv: expected number of scan conversions 186 * @res: data resolution (e.g. RES bitfield value) 187 * @trigger_polarity: external trigger polarity (e.g. exten) 188 * @dma_chan: dma channel 189 * @rx_buf: dma rx buffer cpu address 190 * @rx_dma_buf: dma rx buffer bus address 191 * @rx_buf_sz: dma rx buffer size 192 * @difsel: bitmask to set single-ended/differential channel 193 * @pcsel: bitmask to preselect channels on some devices 194 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 195 * @cal: optional calibration data on some devices 196 * @chan_name: channel name array 197 */ 198struct stm32_adc { 199 struct stm32_adc_common *common; 200 u32 offset; 201 const struct stm32_adc_cfg *cfg; 202 struct completion completion; 203 u16 buffer[STM32_ADC_MAX_SQ]; 204 struct clk *clk; 205 int irq; 206 spinlock_t lock; /* interrupt lock */ 207 unsigned int bufi; 208 unsigned int num_conv; 209 u32 res; 210 u32 trigger_polarity; 211 struct dma_chan *dma_chan; 212 u8 *rx_buf; 213 dma_addr_t rx_dma_buf; 214 unsigned int rx_buf_sz; 215 u32 difsel; 216 u32 pcsel; 217 u32 smpr_val[2]; 218 struct stm32_adc_calib cal; 219 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 220}; 221 222struct stm32_adc_diff_channel { 223 u32 vinp; 224 u32 vinn; 225}; 226 227/** 228 * struct stm32_adc_info - stm32 ADC, per instance config data 229 * @max_channels: Number of channels 230 * @resolutions: available resolutions 231 * @num_res: number of available resolutions 232 */ 233struct stm32_adc_info { 234 int max_channels; 235 const unsigned int *resolutions; 236 const unsigned int num_res; 237}; 238 239static const unsigned int stm32f4_adc_resolutions[] = { 240 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 241 12, 10, 8, 6, 242}; 243 244/* stm32f4 can have up to 16 channels */ 245static const struct stm32_adc_info stm32f4_adc_info = { 246 .max_channels = 16, 247 .resolutions = stm32f4_adc_resolutions, 248 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 249}; 250 251static const unsigned int stm32h7_adc_resolutions[] = { 252 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 253 16, 14, 12, 10, 8, 254}; 255 256/* stm32h7 can have up to 20 channels */ 257static const struct stm32_adc_info stm32h7_adc_info = { 258 .max_channels = STM32_ADC_CH_MAX, 259 .resolutions = stm32h7_adc_resolutions, 260 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 261}; 262 263/* 264 * stm32f4_sq - describe regular sequence registers 265 * - L: sequence len (register & bit field) 266 * - SQ1..SQ16: sequence entries (register & bit field) 267 */ 268static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 269 /* L: len bit field description to be kept as first element */ 270 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 271 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 272 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 273 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 274 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 275 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 276 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 277 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 278 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 279 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 280 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 281 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 282 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 283 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 284 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 285 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 286 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 287 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 288}; 289 290/* STM32F4 external trigger sources for all instances */ 291static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 292 { TIM1_CH1, STM32_EXT0 }, 293 { TIM1_CH2, STM32_EXT1 }, 294 { TIM1_CH3, STM32_EXT2 }, 295 { TIM2_CH2, STM32_EXT3 }, 296 { TIM2_CH3, STM32_EXT4 }, 297 { TIM2_CH4, STM32_EXT5 }, 298 { TIM2_TRGO, STM32_EXT6 }, 299 { TIM3_CH1, STM32_EXT7 }, 300 { TIM3_TRGO, STM32_EXT8 }, 301 { TIM4_CH4, STM32_EXT9 }, 302 { TIM5_CH1, STM32_EXT10 }, 303 { TIM5_CH2, STM32_EXT11 }, 304 { TIM5_CH3, STM32_EXT12 }, 305 { TIM8_CH1, STM32_EXT13 }, 306 { TIM8_TRGO, STM32_EXT14 }, 307 {}, /* sentinel */ 308}; 309 310/* 311 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 312 * Sorted so it can be indexed by channel number. 313 */ 314static const struct stm32_adc_regs stm32f4_smp_bits[] = { 315 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 316 { 1, GENMASK(2, 0), 0 }, 317 { 1, GENMASK(5, 3), 3 }, 318 { 1, GENMASK(8, 6), 6 }, 319 { 1, GENMASK(11, 9), 9 }, 320 { 1, GENMASK(14, 12), 12 }, 321 { 1, GENMASK(17, 15), 15 }, 322 { 1, GENMASK(20, 18), 18 }, 323 { 1, GENMASK(23, 21), 21 }, 324 { 1, GENMASK(26, 24), 24 }, 325 { 1, GENMASK(29, 27), 27 }, 326 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 327 { 0, GENMASK(2, 0), 0 }, 328 { 0, GENMASK(5, 3), 3 }, 329 { 0, GENMASK(8, 6), 6 }, 330 { 0, GENMASK(11, 9), 9 }, 331 { 0, GENMASK(14, 12), 12 }, 332 { 0, GENMASK(17, 15), 15 }, 333 { 0, GENMASK(20, 18), 18 }, 334 { 0, GENMASK(23, 21), 21 }, 335 { 0, GENMASK(26, 24), 24 }, 336}; 337 338/* STM32F4 programmable sampling time (ADC clock cycles) */ 339static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 340 3, 15, 28, 56, 84, 112, 144, 480, 341}; 342 343static const struct stm32_adc_regspec stm32f4_adc_regspec = { 344 .dr = STM32F4_ADC_DR, 345 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 346 .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE }, 347 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 348 .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR }, 349 .sqr = stm32f4_sq, 350 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 351 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 352 STM32F4_EXTSEL_SHIFT }, 353 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 354 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 355 .smp_bits = stm32f4_smp_bits, 356}; 357 358static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 359 /* L: len bit field description to be kept as first element */ 360 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 361 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 362 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 363 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 364 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 365 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 366 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 367 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 368 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 369 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 370 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 371 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 372 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 373 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 374 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 375 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 376 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 377 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 378}; 379 380/* STM32H7 external trigger sources for all instances */ 381static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 382 { TIM1_CH1, STM32_EXT0 }, 383 { TIM1_CH2, STM32_EXT1 }, 384 { TIM1_CH3, STM32_EXT2 }, 385 { TIM2_CH2, STM32_EXT3 }, 386 { TIM3_TRGO, STM32_EXT4 }, 387 { TIM4_CH4, STM32_EXT5 }, 388 { TIM8_TRGO, STM32_EXT7 }, 389 { TIM8_TRGO2, STM32_EXT8 }, 390 { TIM1_TRGO, STM32_EXT9 }, 391 { TIM1_TRGO2, STM32_EXT10 }, 392 { TIM2_TRGO, STM32_EXT11 }, 393 { TIM4_TRGO, STM32_EXT12 }, 394 { TIM6_TRGO, STM32_EXT13 }, 395 { TIM15_TRGO, STM32_EXT14 }, 396 { TIM3_CH4, STM32_EXT15 }, 397 { LPTIM1_OUT, STM32_EXT18 }, 398 { LPTIM2_OUT, STM32_EXT19 }, 399 { LPTIM3_OUT, STM32_EXT20 }, 400 {}, 401}; 402 403/* 404 * stm32h7_smp_bits - describe sampling time register index & bit fields 405 * Sorted so it can be indexed by channel number. 406 */ 407static const struct stm32_adc_regs stm32h7_smp_bits[] = { 408 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 409 { 0, GENMASK(2, 0), 0 }, 410 { 0, GENMASK(5, 3), 3 }, 411 { 0, GENMASK(8, 6), 6 }, 412 { 0, GENMASK(11, 9), 9 }, 413 { 0, GENMASK(14, 12), 12 }, 414 { 0, GENMASK(17, 15), 15 }, 415 { 0, GENMASK(20, 18), 18 }, 416 { 0, GENMASK(23, 21), 21 }, 417 { 0, GENMASK(26, 24), 24 }, 418 { 0, GENMASK(29, 27), 27 }, 419 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 420 { 1, GENMASK(2, 0), 0 }, 421 { 1, GENMASK(5, 3), 3 }, 422 { 1, GENMASK(8, 6), 6 }, 423 { 1, GENMASK(11, 9), 9 }, 424 { 1, GENMASK(14, 12), 12 }, 425 { 1, GENMASK(17, 15), 15 }, 426 { 1, GENMASK(20, 18), 18 }, 427 { 1, GENMASK(23, 21), 21 }, 428 { 1, GENMASK(26, 24), 24 }, 429 { 1, GENMASK(29, 27), 27 }, 430}; 431 432/* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 433static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 434 1, 2, 8, 16, 32, 64, 387, 810, 435}; 436 437static const struct stm32_adc_regspec stm32h7_adc_regspec = { 438 .dr = STM32H7_ADC_DR, 439 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 440 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 441 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 442 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 443 .sqr = stm32h7_sq, 444 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 445 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 446 STM32H7_EXTSEL_SHIFT }, 447 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 448 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 449 .smp_bits = stm32h7_smp_bits, 450}; 451 452/** 453 * STM32 ADC registers access routines 454 * @adc: stm32 adc instance 455 * @reg: reg offset in adc instance 456 * 457 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 458 * for adc1, adc2 and adc3. 459 */ 460static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 461{ 462 return readl_relaxed(adc->common->base + adc->offset + reg); 463} 464 465#define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 466 467#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 468 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 469 cond, sleep_us, timeout_us) 470 471static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 472{ 473 return readw_relaxed(adc->common->base + adc->offset + reg); 474} 475 476static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 477{ 478 writel_relaxed(val, adc->common->base + adc->offset + reg); 479} 480 481static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 482{ 483 unsigned long flags; 484 485 spin_lock_irqsave(&adc->lock, flags); 486 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 487 spin_unlock_irqrestore(&adc->lock, flags); 488} 489 490static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 491{ 492 unsigned long flags; 493 494 spin_lock_irqsave(&adc->lock, flags); 495 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 496 spin_unlock_irqrestore(&adc->lock, flags); 497} 498 499/** 500 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 501 * @adc: stm32 adc instance 502 */ 503static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 504{ 505 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 506 adc->cfg->regs->ier_eoc.mask); 507}; 508 509/** 510 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 511 * @adc: stm32 adc instance 512 */ 513static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 514{ 515 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 516 adc->cfg->regs->ier_eoc.mask); 517} 518 519static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) 520{ 521 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, 522 adc->cfg->regs->ier_ovr.mask); 523} 524 525static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) 526{ 527 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, 528 adc->cfg->regs->ier_ovr.mask); 529} 530 531static void stm32_adc_set_res(struct stm32_adc *adc) 532{ 533 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 534 u32 val; 535 536 val = stm32_adc_readl(adc, res->reg); 537 val = (val & ~res->mask) | (adc->res << res->shift); 538 stm32_adc_writel(adc, res->reg, val); 539} 540 541static int stm32_adc_hw_stop(struct device *dev) 542{ 543 struct iio_dev *indio_dev = dev_get_drvdata(dev); 544 struct stm32_adc *adc = iio_priv(indio_dev); 545 546 if (adc->cfg->unprepare) 547 adc->cfg->unprepare(indio_dev); 548 549 if (adc->clk) 550 clk_disable_unprepare(adc->clk); 551 552 return 0; 553} 554 555static int stm32_adc_hw_start(struct device *dev) 556{ 557 struct iio_dev *indio_dev = dev_get_drvdata(dev); 558 struct stm32_adc *adc = iio_priv(indio_dev); 559 int ret; 560 561 if (adc->clk) { 562 ret = clk_prepare_enable(adc->clk); 563 if (ret) 564 return ret; 565 } 566 567 stm32_adc_set_res(adc); 568 569 if (adc->cfg->prepare) { 570 ret = adc->cfg->prepare(indio_dev); 571 if (ret) 572 goto err_clk_dis; 573 } 574 575 return 0; 576 577err_clk_dis: 578 if (adc->clk) 579 clk_disable_unprepare(adc->clk); 580 581 return ret; 582} 583 584/** 585 * stm32f4_adc_start_conv() - Start conversions for regular channels. 586 * @indio_dev: IIO device instance 587 * @dma: use dma to transfer conversion result 588 * 589 * Start conversions for regular channels. 590 * Also take care of normal or DMA mode. Circular DMA may be used for regular 591 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 592 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 593 */ 594static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) 595{ 596 struct stm32_adc *adc = iio_priv(indio_dev); 597 598 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 599 600 if (dma) 601 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 602 STM32F4_DMA | STM32F4_DDS); 603 604 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 605 606 /* Wait for Power-up time (tSTAB from datasheet) */ 607 usleep_range(2, 3); 608 609 /* Software start ? (e.g. trigger detection disabled ?) */ 610 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 611 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 612} 613 614static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev) 615{ 616 struct stm32_adc *adc = iio_priv(indio_dev); 617 618 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 619 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 620 621 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 622 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 623 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 624} 625 626static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 627{ 628 struct stm32_adc *adc = iio_priv(indio_dev); 629 630 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 631} 632 633static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) 634{ 635 struct stm32_adc *adc = iio_priv(indio_dev); 636 enum stm32h7_adc_dmngt dmngt; 637 unsigned long flags; 638 u32 val; 639 640 if (dma) 641 dmngt = STM32H7_DMNGT_DMA_CIRC; 642 else 643 dmngt = STM32H7_DMNGT_DR_ONLY; 644 645 spin_lock_irqsave(&adc->lock, flags); 646 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 647 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 648 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 649 spin_unlock_irqrestore(&adc->lock, flags); 650 651 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 652} 653 654static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev) 655{ 656 struct stm32_adc *adc = iio_priv(indio_dev); 657 int ret; 658 u32 val; 659 660 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 661 662 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 663 !(val & (STM32H7_ADSTART)), 664 100, STM32_ADC_TIMEOUT_US); 665 if (ret) 666 dev_warn(&indio_dev->dev, "stop failed\n"); 667 668 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 669} 670 671static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 672{ 673 struct stm32_adc *adc = iio_priv(indio_dev); 674 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */ 675 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 676} 677 678static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) 679{ 680 struct stm32_adc *adc = iio_priv(indio_dev); 681 int ret; 682 u32 val; 683 684 /* Exit deep power down, then enable ADC voltage regulator */ 685 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 686 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 687 688 if (adc->common->rate > STM32H7_BOOST_CLKRATE) 689 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 690 691 /* Wait for startup time */ 692 if (!adc->cfg->has_vregready) { 693 usleep_range(10, 20); 694 return 0; 695 } 696 697 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 698 val & STM32MP1_VREGREADY, 100, 699 STM32_ADC_TIMEOUT_US); 700 if (ret) { 701 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 702 dev_err(&indio_dev->dev, "Failed to exit power down\n"); 703 } 704 705 return ret; 706} 707 708static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 709{ 710 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 711 712 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 713 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 714} 715 716static int stm32h7_adc_enable(struct iio_dev *indio_dev) 717{ 718 struct stm32_adc *adc = iio_priv(indio_dev); 719 int ret; 720 u32 val; 721 722 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 723 724 /* Poll for ADRDY to be set (after adc startup time) */ 725 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 726 val & STM32H7_ADRDY, 727 100, STM32_ADC_TIMEOUT_US); 728 if (ret) { 729 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 730 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 731 } else { 732 /* Clear ADRDY by writing one */ 733 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 734 } 735 736 return ret; 737} 738 739static void stm32h7_adc_disable(struct iio_dev *indio_dev) 740{ 741 struct stm32_adc *adc = iio_priv(indio_dev); 742 int ret; 743 u32 val; 744 745 /* Disable ADC and wait until it's effectively disabled */ 746 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 747 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 748 !(val & STM32H7_ADEN), 100, 749 STM32_ADC_TIMEOUT_US); 750 if (ret) 751 dev_warn(&indio_dev->dev, "Failed to disable\n"); 752} 753 754/** 755 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 756 * @indio_dev: IIO device instance 757 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable 758 */ 759static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev) 760{ 761 struct stm32_adc *adc = iio_priv(indio_dev); 762 int i, ret; 763 u32 lincalrdyw_mask, val; 764 765 /* Read linearity calibration */ 766 lincalrdyw_mask = STM32H7_LINCALRDYW6; 767 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 768 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 769 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 770 771 /* Poll: wait calib data to be ready in CALFACT2 register */ 772 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 773 !(val & lincalrdyw_mask), 774 100, STM32_ADC_TIMEOUT_US); 775 if (ret) { 776 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 777 return ret; 778 } 779 780 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 781 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 782 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 783 784 lincalrdyw_mask >>= 1; 785 } 786 787 /* Read offset calibration */ 788 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); 789 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); 790 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; 791 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); 792 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; 793 adc->cal.calibrated = true; 794 795 return 0; 796} 797 798/** 799 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 800 * @indio_dev: IIO device instance 801 * Note: ADC must be enabled, with no on-going conversions. 802 */ 803static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev) 804{ 805 struct stm32_adc *adc = iio_priv(indio_dev); 806 int i, ret; 807 u32 lincalrdyw_mask, val; 808 809 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | 810 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); 811 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); 812 813 lincalrdyw_mask = STM32H7_LINCALRDYW6; 814 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 815 /* 816 * Write saved calibration data to shadow registers: 817 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 818 * data write. Then poll to wait for complete transfer. 819 */ 820 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 821 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 823 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 824 val & lincalrdyw_mask, 825 100, STM32_ADC_TIMEOUT_US); 826 if (ret) { 827 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 828 return ret; 829 } 830 831 /* 832 * Read back calibration data, has two effects: 833 * - It ensures bits LINCALRDYW[6..1] are kept cleared 834 * for next time calibration needs to be restored. 835 * - BTW, bit clear triggers a read, then check data has been 836 * correctly written. 837 */ 838 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 839 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 840 !(val & lincalrdyw_mask), 841 100, STM32_ADC_TIMEOUT_US); 842 if (ret) { 843 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 844 return ret; 845 } 846 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 847 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 848 dev_err(&indio_dev->dev, "calfact not consistent\n"); 849 return -EIO; 850 } 851 852 lincalrdyw_mask >>= 1; 853 } 854 855 return 0; 856} 857 858/** 859 * Fixed timeout value for ADC calibration. 860 * worst cases: 861 * - low clock frequency 862 * - maximum prescalers 863 * Calibration requires: 864 * - 131,072 ADC clock cycle for the linear calibration 865 * - 20 ADC clock cycle for the offset calibration 866 * 867 * Set to 100ms for now 868 */ 869#define STM32H7_ADC_CALIB_TIMEOUT_US 100000 870 871/** 872 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC 873 * @indio_dev: IIO device instance 874 * Note: Must be called once ADC is out of power down. 875 */ 876static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev) 877{ 878 struct stm32_adc *adc = iio_priv(indio_dev); 879 int ret; 880 u32 val; 881 882 if (adc->cal.calibrated) 883 return true; 884 885 /* 886 * Select calibration mode: 887 * - Offset calibration for single ended inputs 888 * - No linearity calibration (do it later, before reading it) 889 */ 890 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); 891 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); 892 893 /* Start calibration, then wait for completion */ 894 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 895 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 896 !(val & STM32H7_ADCAL), 100, 897 STM32H7_ADC_CALIB_TIMEOUT_US); 898 if (ret) { 899 dev_err(&indio_dev->dev, "calibration failed\n"); 900 goto out; 901 } 902 903 /* 904 * Select calibration mode, then start calibration: 905 * - Offset calibration for differential input 906 * - Linearity calibration (needs to be done only once for single/diff) 907 * will run simultaneously with offset calibration. 908 */ 909 stm32_adc_set_bits(adc, STM32H7_ADC_CR, 910 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 911 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 912 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 913 !(val & STM32H7_ADCAL), 100, 914 STM32H7_ADC_CALIB_TIMEOUT_US); 915 if (ret) { 916 dev_err(&indio_dev->dev, "calibration failed\n"); 917 goto out; 918 } 919 920out: 921 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, 922 STM32H7_ADCALDIF | STM32H7_ADCALLIN); 923 924 return ret; 925} 926 927/** 928 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 929 * @indio_dev: IIO device instance 930 * Leave power down mode. 931 * Configure channels as single ended or differential before enabling ADC. 932 * Enable ADC. 933 * Restore calibration data. 934 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 935 * - Only one input is selected for single ended (e.g. 'vinp') 936 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 937 */ 938static int stm32h7_adc_prepare(struct iio_dev *indio_dev) 939{ 940 struct stm32_adc *adc = iio_priv(indio_dev); 941 int calib, ret; 942 943 ret = stm32h7_adc_exit_pwr_down(indio_dev); 944 if (ret) 945 return ret; 946 947 ret = stm32h7_adc_selfcalib(indio_dev); 948 if (ret < 0) 949 goto pwr_dwn; 950 calib = ret; 951 952 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); 953 954 ret = stm32h7_adc_enable(indio_dev); 955 if (ret) 956 goto pwr_dwn; 957 958 /* Either restore or read calibration result for future reference */ 959 if (calib) 960 ret = stm32h7_adc_restore_selfcalib(indio_dev); 961 else 962 ret = stm32h7_adc_read_selfcalib(indio_dev); 963 if (ret) 964 goto disable; 965 966 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 967 968 return 0; 969 970disable: 971 stm32h7_adc_disable(indio_dev); 972pwr_dwn: 973 stm32h7_adc_enter_pwr_down(adc); 974 975 return ret; 976} 977 978static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) 979{ 980 struct stm32_adc *adc = iio_priv(indio_dev); 981 982 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 983 stm32h7_adc_disable(indio_dev); 984 stm32h7_adc_enter_pwr_down(adc); 985} 986 987/** 988 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 989 * @indio_dev: IIO device 990 * @scan_mask: channels to be converted 991 * 992 * Conversion sequence : 993 * Apply sampling time settings for all channels. 994 * Configure ADC scan sequence based on selected channels in scan_mask. 995 * Add channels to SQR registers, from scan_mask LSB to MSB, then 996 * program sequence len. 997 */ 998static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 999 const unsigned long *scan_mask) 1000{ 1001 struct stm32_adc *adc = iio_priv(indio_dev); 1002 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 1003 const struct iio_chan_spec *chan; 1004 u32 val, bit; 1005 int i = 0; 1006 1007 /* Apply sampling time settings */ 1008 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1009 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1010 1011 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { 1012 chan = indio_dev->channels + bit; 1013 /* 1014 * Assign one channel per SQ entry in regular 1015 * sequence, starting with SQ1. 1016 */ 1017 i++; 1018 if (i > STM32_ADC_MAX_SQ) 1019 return -EINVAL; 1020 1021 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1022 __func__, chan->channel, i); 1023 1024 val = stm32_adc_readl(adc, sqr[i].reg); 1025 val &= ~sqr[i].mask; 1026 val |= chan->channel << sqr[i].shift; 1027 stm32_adc_writel(adc, sqr[i].reg, val); 1028 } 1029 1030 if (!i) 1031 return -EINVAL; 1032 1033 /* Sequence len */ 1034 val = stm32_adc_readl(adc, sqr[0].reg); 1035 val &= ~sqr[0].mask; 1036 val |= ((i - 1) << sqr[0].shift); 1037 stm32_adc_writel(adc, sqr[0].reg, val); 1038 1039 return 0; 1040} 1041 1042/** 1043 * stm32_adc_get_trig_extsel() - Get external trigger selection 1044 * @indio_dev: IIO device structure 1045 * @trig: trigger 1046 * 1047 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1048 */ 1049static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1050 struct iio_trigger *trig) 1051{ 1052 struct stm32_adc *adc = iio_priv(indio_dev); 1053 int i; 1054 1055 /* lookup triggers registered by stm32 timer trigger driver */ 1056 for (i = 0; adc->cfg->trigs[i].name; i++) { 1057 /** 1058 * Checking both stm32 timer trigger type and trig name 1059 * should be safe against arbitrary trigger names. 1060 */ 1061 if ((is_stm32_timer_trigger(trig) || 1062 is_stm32_lptim_trigger(trig)) && 1063 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1064 return adc->cfg->trigs[i].extsel; 1065 } 1066 } 1067 1068 return -EINVAL; 1069} 1070 1071/** 1072 * stm32_adc_set_trig() - Set a regular trigger 1073 * @indio_dev: IIO device 1074 * @trig: IIO trigger 1075 * 1076 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1077 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1078 * - if HW trigger enabled, set source & polarity 1079 */ 1080static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1081 struct iio_trigger *trig) 1082{ 1083 struct stm32_adc *adc = iio_priv(indio_dev); 1084 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1085 unsigned long flags; 1086 int ret; 1087 1088 if (trig) { 1089 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1090 if (ret < 0) 1091 return ret; 1092 1093 /* set trigger source and polarity (default to rising edge) */ 1094 extsel = ret; 1095 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1096 } 1097 1098 spin_lock_irqsave(&adc->lock, flags); 1099 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1100 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1101 val |= exten << adc->cfg->regs->exten.shift; 1102 val |= extsel << adc->cfg->regs->extsel.shift; 1103 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1104 spin_unlock_irqrestore(&adc->lock, flags); 1105 1106 return 0; 1107} 1108 1109static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1110 const struct iio_chan_spec *chan, 1111 unsigned int type) 1112{ 1113 struct stm32_adc *adc = iio_priv(indio_dev); 1114 1115 adc->trigger_polarity = type; 1116 1117 return 0; 1118} 1119 1120static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1121 const struct iio_chan_spec *chan) 1122{ 1123 struct stm32_adc *adc = iio_priv(indio_dev); 1124 1125 return adc->trigger_polarity; 1126} 1127 1128static const char * const stm32_trig_pol_items[] = { 1129 "rising-edge", "falling-edge", "both-edges", 1130}; 1131 1132static const struct iio_enum stm32_adc_trig_pol = { 1133 .items = stm32_trig_pol_items, 1134 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1135 .get = stm32_adc_get_trig_pol, 1136 .set = stm32_adc_set_trig_pol, 1137}; 1138 1139/** 1140 * stm32_adc_single_conv() - Performs a single conversion 1141 * @indio_dev: IIO device 1142 * @chan: IIO channel 1143 * @res: conversion result 1144 * 1145 * The function performs a single conversion on a given channel: 1146 * - Apply sampling time settings 1147 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1148 * - Use SW trigger 1149 * - Start conversion, then wait for interrupt completion. 1150 */ 1151static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1152 const struct iio_chan_spec *chan, 1153 int *res) 1154{ 1155 struct stm32_adc *adc = iio_priv(indio_dev); 1156 struct device *dev = indio_dev->dev.parent; 1157 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1158 long timeout; 1159 u32 val; 1160 int ret; 1161 1162 reinit_completion(&adc->completion); 1163 1164 adc->bufi = 0; 1165 1166 ret = pm_runtime_get_sync(dev); 1167 if (ret < 0) { 1168 pm_runtime_put_noidle(dev); 1169 return ret; 1170 } 1171 1172 /* Apply sampling time settings */ 1173 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1174 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1175 1176 /* Program chan number in regular sequence (SQ1) */ 1177 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1178 val &= ~regs->sqr[1].mask; 1179 val |= chan->channel << regs->sqr[1].shift; 1180 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1181 1182 /* Set regular sequence len (0 for 1 conversion) */ 1183 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1184 1185 /* Trigger detection disabled (conversion can be launched in SW) */ 1186 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1187 1188 stm32_adc_conv_irq_enable(adc); 1189 1190 adc->cfg->start_conv(indio_dev, false); 1191 1192 timeout = wait_for_completion_interruptible_timeout( 1193 &adc->completion, STM32_ADC_TIMEOUT); 1194 if (timeout == 0) { 1195 ret = -ETIMEDOUT; 1196 } else if (timeout < 0) { 1197 ret = timeout; 1198 } else { 1199 *res = adc->buffer[0]; 1200 ret = IIO_VAL_INT; 1201 } 1202 1203 adc->cfg->stop_conv(indio_dev); 1204 1205 stm32_adc_conv_irq_disable(adc); 1206 1207 pm_runtime_mark_last_busy(dev); 1208 pm_runtime_put_autosuspend(dev); 1209 1210 return ret; 1211} 1212 1213static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1214 struct iio_chan_spec const *chan, 1215 int *val, int *val2, long mask) 1216{ 1217 struct stm32_adc *adc = iio_priv(indio_dev); 1218 int ret; 1219 1220 switch (mask) { 1221 case IIO_CHAN_INFO_RAW: 1222 ret = iio_device_claim_direct_mode(indio_dev); 1223 if (ret) 1224 return ret; 1225 if (chan->type == IIO_VOLTAGE) 1226 ret = stm32_adc_single_conv(indio_dev, chan, val); 1227 else 1228 ret = -EINVAL; 1229 iio_device_release_direct_mode(indio_dev); 1230 return ret; 1231 1232 case IIO_CHAN_INFO_SCALE: 1233 if (chan->differential) { 1234 *val = adc->common->vref_mv * 2; 1235 *val2 = chan->scan_type.realbits; 1236 } else { 1237 *val = adc->common->vref_mv; 1238 *val2 = chan->scan_type.realbits; 1239 } 1240 return IIO_VAL_FRACTIONAL_LOG2; 1241 1242 case IIO_CHAN_INFO_OFFSET: 1243 if (chan->differential) 1244 /* ADC_full_scale / 2 */ 1245 *val = -((1 << chan->scan_type.realbits) / 2); 1246 else 1247 *val = 0; 1248 return IIO_VAL_INT; 1249 1250 default: 1251 return -EINVAL; 1252 } 1253} 1254 1255static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 1256{ 1257 struct stm32_adc *adc = iio_priv(indio_dev); 1258 1259 adc->cfg->irq_clear(indio_dev, msk); 1260} 1261 1262static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) 1263{ 1264 struct iio_dev *indio_dev = data; 1265 struct stm32_adc *adc = iio_priv(indio_dev); 1266 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1267 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1268 1269 /* Check ovr status right now, as ovr mask should be already disabled */ 1270 if (status & regs->isr_ovr.mask) { 1271 /* 1272 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1273 * This requires to stop ADC first. OVR bit state in ISR, 1274 * is propaged to CSR register by hardware. 1275 */ 1276 adc->cfg->stop_conv(indio_dev); 1277 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); 1278 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); 1279 return IRQ_HANDLED; 1280 } 1281 1282 return IRQ_NONE; 1283} 1284 1285static irqreturn_t stm32_adc_isr(int irq, void *data) 1286{ 1287 struct iio_dev *indio_dev = data; 1288 struct stm32_adc *adc = iio_priv(indio_dev); 1289 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1290 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1291 1292 if (status & regs->isr_ovr.mask) { 1293 /* 1294 * Overrun occurred on regular conversions: data for wrong 1295 * channel may be read. Unconditionally disable interrupts 1296 * to stop processing data and print error message. 1297 * Restarting the capture can be done by disabling, then 1298 * re-enabling it (e.g. write 0, then 1 to buffer/enable). 1299 */ 1300 stm32_adc_ovr_irq_disable(adc); 1301 stm32_adc_conv_irq_disable(adc); 1302 return IRQ_WAKE_THREAD; 1303 } 1304 1305 if (status & regs->isr_eoc.mask) { 1306 /* Reading DR also clears EOC status flag */ 1307 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1308 if (iio_buffer_enabled(indio_dev)) { 1309 adc->bufi++; 1310 if (adc->bufi >= adc->num_conv) { 1311 stm32_adc_conv_irq_disable(adc); 1312 iio_trigger_poll(indio_dev->trig); 1313 } 1314 } else { 1315 complete(&adc->completion); 1316 } 1317 return IRQ_HANDLED; 1318 } 1319 1320 return IRQ_NONE; 1321} 1322 1323/** 1324 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1325 * @indio_dev: IIO device 1326 * @trig: new trigger 1327 * 1328 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1329 * driver, -EINVAL otherwise. 1330 */ 1331static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1332 struct iio_trigger *trig) 1333{ 1334 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1335} 1336 1337static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1338{ 1339 struct stm32_adc *adc = iio_priv(indio_dev); 1340 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1341 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1342 1343 /* 1344 * dma cyclic transfers are used, buffer is split into two periods. 1345 * There should be : 1346 * - always one buffer (period) dma is working on 1347 * - one buffer (period) driver can push with iio_trigger_poll(). 1348 */ 1349 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1350 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1351 1352 return 0; 1353} 1354 1355static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1356 const unsigned long *scan_mask) 1357{ 1358 struct stm32_adc *adc = iio_priv(indio_dev); 1359 struct device *dev = indio_dev->dev.parent; 1360 int ret; 1361 1362 ret = pm_runtime_get_sync(dev); 1363 if (ret < 0) { 1364 pm_runtime_put_noidle(dev); 1365 return ret; 1366 } 1367 1368 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); 1369 1370 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1371 pm_runtime_mark_last_busy(dev); 1372 pm_runtime_put_autosuspend(dev); 1373 1374 return ret; 1375} 1376 1377static int stm32_adc_of_xlate(struct iio_dev *indio_dev, 1378 const struct of_phandle_args *iiospec) 1379{ 1380 int i; 1381 1382 for (i = 0; i < indio_dev->num_channels; i++) 1383 if (indio_dev->channels[i].channel == iiospec->args[0]) 1384 return i; 1385 1386 return -EINVAL; 1387} 1388 1389/** 1390 * stm32_adc_debugfs_reg_access - read or write register value 1391 * @indio_dev: IIO device structure 1392 * @reg: register offset 1393 * @writeval: value to write 1394 * @readval: value to read 1395 * 1396 * To read a value from an ADC register: 1397 * echo [ADC reg offset] > direct_reg_access 1398 * cat direct_reg_access 1399 * 1400 * To write a value in a ADC register: 1401 * echo [ADC_reg_offset] [value] > direct_reg_access 1402 */ 1403static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1404 unsigned reg, unsigned writeval, 1405 unsigned *readval) 1406{ 1407 struct stm32_adc *adc = iio_priv(indio_dev); 1408 struct device *dev = indio_dev->dev.parent; 1409 int ret; 1410 1411 ret = pm_runtime_get_sync(dev); 1412 if (ret < 0) { 1413 pm_runtime_put_noidle(dev); 1414 return ret; 1415 } 1416 1417 if (!readval) 1418 stm32_adc_writel(adc, reg, writeval); 1419 else 1420 *readval = stm32_adc_readl(adc, reg); 1421 1422 pm_runtime_mark_last_busy(dev); 1423 pm_runtime_put_autosuspend(dev); 1424 1425 return 0; 1426} 1427 1428static const struct iio_info stm32_adc_iio_info = { 1429 .read_raw = stm32_adc_read_raw, 1430 .validate_trigger = stm32_adc_validate_trigger, 1431 .hwfifo_set_watermark = stm32_adc_set_watermark, 1432 .update_scan_mode = stm32_adc_update_scan_mode, 1433 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1434 .of_xlate = stm32_adc_of_xlate, 1435}; 1436 1437static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1438{ 1439 struct dma_tx_state state; 1440 enum dma_status status; 1441 1442 status = dmaengine_tx_status(adc->dma_chan, 1443 adc->dma_chan->cookie, 1444 &state); 1445 if (status == DMA_IN_PROGRESS) { 1446 /* Residue is size in bytes from end of buffer */ 1447 unsigned int i = adc->rx_buf_sz - state.residue; 1448 unsigned int size; 1449 1450 /* Return available bytes */ 1451 if (i >= adc->bufi) 1452 size = i - adc->bufi; 1453 else 1454 size = adc->rx_buf_sz + i - adc->bufi; 1455 1456 return size; 1457 } 1458 1459 return 0; 1460} 1461 1462static void stm32_adc_dma_buffer_done(void *data) 1463{ 1464 struct iio_dev *indio_dev = data; 1465 struct stm32_adc *adc = iio_priv(indio_dev); 1466 int residue = stm32_adc_dma_residue(adc); 1467 1468 /* 1469 * In DMA mode the trigger services of IIO are not used 1470 * (e.g. no call to iio_trigger_poll). 1471 * Calling irq handler associated to the hardware trigger is not 1472 * relevant as the conversions have already been done. Data 1473 * transfers are performed directly in DMA callback instead. 1474 * This implementation avoids to call trigger irq handler that 1475 * may sleep, in an atomic context (DMA irq handler context). 1476 */ 1477 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1478 1479 while (residue >= indio_dev->scan_bytes) { 1480 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1481 1482 iio_push_to_buffers(indio_dev, buffer); 1483 1484 residue -= indio_dev->scan_bytes; 1485 adc->bufi += indio_dev->scan_bytes; 1486 if (adc->bufi >= adc->rx_buf_sz) 1487 adc->bufi = 0; 1488 } 1489} 1490 1491static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1492{ 1493 struct stm32_adc *adc = iio_priv(indio_dev); 1494 struct dma_async_tx_descriptor *desc; 1495 dma_cookie_t cookie; 1496 int ret; 1497 1498 if (!adc->dma_chan) 1499 return 0; 1500 1501 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1502 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1503 1504 /* Prepare a DMA cyclic transaction */ 1505 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1506 adc->rx_dma_buf, 1507 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1508 DMA_DEV_TO_MEM, 1509 DMA_PREP_INTERRUPT); 1510 if (!desc) 1511 return -EBUSY; 1512 1513 desc->callback = stm32_adc_dma_buffer_done; 1514 desc->callback_param = indio_dev; 1515 1516 cookie = dmaengine_submit(desc); 1517 ret = dma_submit_error(cookie); 1518 if (ret) { 1519 dmaengine_terminate_sync(adc->dma_chan); 1520 return ret; 1521 } 1522 1523 /* Issue pending DMA requests */ 1524 dma_async_issue_pending(adc->dma_chan); 1525 1526 return 0; 1527} 1528 1529static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1530{ 1531 struct stm32_adc *adc = iio_priv(indio_dev); 1532 struct device *dev = indio_dev->dev.parent; 1533 int ret; 1534 1535 ret = pm_runtime_get_sync(dev); 1536 if (ret < 0) { 1537 pm_runtime_put_noidle(dev); 1538 return ret; 1539 } 1540 1541 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1542 if (ret) { 1543 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1544 goto err_pm_put; 1545 } 1546 1547 ret = stm32_adc_dma_start(indio_dev); 1548 if (ret) { 1549 dev_err(&indio_dev->dev, "Can't start dma\n"); 1550 goto err_clr_trig; 1551 } 1552 1553 /* Reset adc buffer index */ 1554 adc->bufi = 0; 1555 1556 stm32_adc_ovr_irq_enable(adc); 1557 1558 if (!adc->dma_chan) 1559 stm32_adc_conv_irq_enable(adc); 1560 1561 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); 1562 1563 return 0; 1564 1565err_clr_trig: 1566 stm32_adc_set_trig(indio_dev, NULL); 1567err_pm_put: 1568 pm_runtime_mark_last_busy(dev); 1569 pm_runtime_put_autosuspend(dev); 1570 1571 return ret; 1572} 1573 1574static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1575{ 1576 struct stm32_adc *adc = iio_priv(indio_dev); 1577 struct device *dev = indio_dev->dev.parent; 1578 1579 adc->cfg->stop_conv(indio_dev); 1580 if (!adc->dma_chan) 1581 stm32_adc_conv_irq_disable(adc); 1582 1583 stm32_adc_ovr_irq_disable(adc); 1584 1585 if (adc->dma_chan) 1586 dmaengine_terminate_sync(adc->dma_chan); 1587 1588 if (stm32_adc_set_trig(indio_dev, NULL)) 1589 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1590 1591 pm_runtime_mark_last_busy(dev); 1592 pm_runtime_put_autosuspend(dev); 1593 1594 return 0; 1595} 1596 1597static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1598 .postenable = &stm32_adc_buffer_postenable, 1599 .predisable = &stm32_adc_buffer_predisable, 1600}; 1601 1602static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1603{ 1604 struct iio_poll_func *pf = p; 1605 struct iio_dev *indio_dev = pf->indio_dev; 1606 struct stm32_adc *adc = iio_priv(indio_dev); 1607 1608 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1609 1610 if (!adc->dma_chan) { 1611 /* reset buffer index */ 1612 adc->bufi = 0; 1613 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, 1614 pf->timestamp); 1615 } else { 1616 int residue = stm32_adc_dma_residue(adc); 1617 1618 while (residue >= indio_dev->scan_bytes) { 1619 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1620 1621 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1622 pf->timestamp); 1623 residue -= indio_dev->scan_bytes; 1624 adc->bufi += indio_dev->scan_bytes; 1625 if (adc->bufi >= adc->rx_buf_sz) 1626 adc->bufi = 0; 1627 } 1628 } 1629 1630 iio_trigger_notify_done(indio_dev->trig); 1631 1632 /* re-enable eoc irq */ 1633 if (!adc->dma_chan) 1634 stm32_adc_conv_irq_enable(adc); 1635 1636 return IRQ_HANDLED; 1637} 1638 1639static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 1640 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 1641 { 1642 .name = "trigger_polarity_available", 1643 .shared = IIO_SHARED_BY_ALL, 1644 .read = iio_enum_available_read, 1645 .private = (uintptr_t)&stm32_adc_trig_pol, 1646 }, 1647 {}, 1648}; 1649 1650static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev) 1651{ 1652 struct device_node *node = indio_dev->dev.of_node; 1653 struct stm32_adc *adc = iio_priv(indio_dev); 1654 unsigned int i; 1655 u32 res; 1656 1657 if (of_property_read_u32(node, "assigned-resolution-bits", &res)) 1658 res = adc->cfg->adc_info->resolutions[0]; 1659 1660 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 1661 if (res == adc->cfg->adc_info->resolutions[i]) 1662 break; 1663 if (i >= adc->cfg->adc_info->num_res) { 1664 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 1665 return -EINVAL; 1666 } 1667 1668 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 1669 adc->res = i; 1670 1671 return 0; 1672} 1673 1674static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 1675{ 1676 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 1677 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 1678 unsigned int smp, r = smpr->reg; 1679 1680 /* Determine sampling time (ADC clock cycles) */ 1681 period_ns = NSEC_PER_SEC / adc->common->rate; 1682 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 1683 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 1684 break; 1685 if (smp > STM32_ADC_MAX_SMP) 1686 smp = STM32_ADC_MAX_SMP; 1687 1688 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 1689 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 1690} 1691 1692static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 1693 struct iio_chan_spec *chan, u32 vinp, 1694 u32 vinn, int scan_index, bool differential) 1695{ 1696 struct stm32_adc *adc = iio_priv(indio_dev); 1697 char *name = adc->chan_name[vinp]; 1698 1699 chan->type = IIO_VOLTAGE; 1700 chan->channel = vinp; 1701 if (differential) { 1702 chan->differential = 1; 1703 chan->channel2 = vinn; 1704 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 1705 } else { 1706 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 1707 } 1708 chan->datasheet_name = name; 1709 chan->scan_index = scan_index; 1710 chan->indexed = 1; 1711 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 1712 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 1713 BIT(IIO_CHAN_INFO_OFFSET); 1714 chan->scan_type.sign = 'u'; 1715 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 1716 chan->scan_type.storagebits = 16; 1717 chan->ext_info = stm32_adc_ext_info; 1718 1719 /* pre-build selected channels mask */ 1720 adc->pcsel |= BIT(chan->channel); 1721 if (differential) { 1722 /* pre-build diff channels mask */ 1723 adc->difsel |= BIT(chan->channel); 1724 /* Also add negative input to pre-selected channels */ 1725 adc->pcsel |= BIT(chan->channel2); 1726 } 1727} 1728 1729static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) 1730{ 1731 struct device_node *node = indio_dev->dev.of_node; 1732 struct stm32_adc *adc = iio_priv(indio_dev); 1733 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 1734 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 1735 struct property *prop; 1736 const __be32 *cur; 1737 struct iio_chan_spec *channels; 1738 int scan_index = 0, num_channels = 0, num_diff = 0, ret, i; 1739 u32 val, smp = 0; 1740 1741 ret = of_property_count_u32_elems(node, "st,adc-channels"); 1742 if (ret > adc_info->max_channels) { 1743 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 1744 return -EINVAL; 1745 } else if (ret > 0) { 1746 num_channels += ret; 1747 } 1748 1749 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", 1750 sizeof(*diff)); 1751 if (ret > adc_info->max_channels) { 1752 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 1753 return -EINVAL; 1754 } else if (ret > 0) { 1755 int size = ret * sizeof(*diff) / sizeof(u32); 1756 1757 num_diff = ret; 1758 num_channels += ret; 1759 ret = of_property_read_u32_array(node, "st,adc-diff-channels", 1760 (u32 *)diff, size); 1761 if (ret) 1762 return ret; 1763 } 1764 1765 if (!num_channels) { 1766 dev_err(&indio_dev->dev, "No channels configured\n"); 1767 return -ENODATA; 1768 } 1769 1770 /* Optional sample time is provided either for each, or all channels */ 1771 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs"); 1772 if (ret > 1 && ret != num_channels) { 1773 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 1774 return -EINVAL; 1775 } 1776 1777 channels = devm_kcalloc(&indio_dev->dev, num_channels, 1778 sizeof(struct iio_chan_spec), GFP_KERNEL); 1779 if (!channels) 1780 return -ENOMEM; 1781 1782 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { 1783 if (val >= adc_info->max_channels) { 1784 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); 1785 return -EINVAL; 1786 } 1787 1788 /* Channel can't be configured both as single-ended & diff */ 1789 for (i = 0; i < num_diff; i++) { 1790 if (val == diff[i].vinp) { 1791 dev_err(&indio_dev->dev, 1792 "channel %d miss-configured\n", val); 1793 return -EINVAL; 1794 } 1795 } 1796 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 1797 0, scan_index, false); 1798 scan_index++; 1799 } 1800 1801 for (i = 0; i < num_diff; i++) { 1802 if (diff[i].vinp >= adc_info->max_channels || 1803 diff[i].vinn >= adc_info->max_channels) { 1804 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 1805 diff[i].vinp, diff[i].vinn); 1806 return -EINVAL; 1807 } 1808 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 1809 diff[i].vinp, diff[i].vinn, scan_index, 1810 true); 1811 scan_index++; 1812 } 1813 1814 for (i = 0; i < scan_index; i++) { 1815 /* 1816 * Using of_property_read_u32_index(), smp value will only be 1817 * modified if valid u32 value can be decoded. This allows to 1818 * get either no value, 1 shared value for all indexes, or one 1819 * value per channel. 1820 */ 1821 of_property_read_u32_index(node, "st,min-sample-time-nsecs", 1822 i, &smp); 1823 /* Prepare sampling time settings */ 1824 stm32_adc_smpr_init(adc, channels[i].channel, smp); 1825 } 1826 1827 indio_dev->num_channels = scan_index; 1828 indio_dev->channels = channels; 1829 1830 return 0; 1831} 1832 1833static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) 1834{ 1835 struct stm32_adc *adc = iio_priv(indio_dev); 1836 struct dma_slave_config config; 1837 int ret; 1838 1839 adc->dma_chan = dma_request_chan(dev, "rx"); 1840 if (IS_ERR(adc->dma_chan)) { 1841 ret = PTR_ERR(adc->dma_chan); 1842 if (ret != -ENODEV) 1843 return dev_err_probe(dev, ret, 1844 "DMA channel request failed with\n"); 1845 1846 /* DMA is optional: fall back to IRQ mode */ 1847 adc->dma_chan = NULL; 1848 return 0; 1849 } 1850 1851 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 1852 STM32_DMA_BUFFER_SIZE, 1853 &adc->rx_dma_buf, GFP_KERNEL); 1854 if (!adc->rx_buf) { 1855 ret = -ENOMEM; 1856 goto err_release; 1857 } 1858 1859 /* Configure DMA channel to read data register */ 1860 memset(&config, 0, sizeof(config)); 1861 config.src_addr = (dma_addr_t)adc->common->phys_base; 1862 config.src_addr += adc->offset + adc->cfg->regs->dr; 1863 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1864 1865 ret = dmaengine_slave_config(adc->dma_chan, &config); 1866 if (ret) 1867 goto err_free; 1868 1869 return 0; 1870 1871err_free: 1872 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 1873 adc->rx_buf, adc->rx_dma_buf); 1874err_release: 1875 dma_release_channel(adc->dma_chan); 1876 1877 return ret; 1878} 1879 1880static int stm32_adc_probe(struct platform_device *pdev) 1881{ 1882 struct iio_dev *indio_dev; 1883 struct device *dev = &pdev->dev; 1884 irqreturn_t (*handler)(int irq, void *p) = NULL; 1885 struct stm32_adc *adc; 1886 int ret; 1887 1888 if (!pdev->dev.of_node) 1889 return -ENODEV; 1890 1891 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 1892 if (!indio_dev) 1893 return -ENOMEM; 1894 1895 adc = iio_priv(indio_dev); 1896 adc->common = dev_get_drvdata(pdev->dev.parent); 1897 spin_lock_init(&adc->lock); 1898 init_completion(&adc->completion); 1899 adc->cfg = (const struct stm32_adc_cfg *) 1900 of_match_device(dev->driver->of_match_table, dev)->data; 1901 1902 indio_dev->name = dev_name(&pdev->dev); 1903 indio_dev->dev.of_node = pdev->dev.of_node; 1904 indio_dev->info = &stm32_adc_iio_info; 1905 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 1906 1907 platform_set_drvdata(pdev, indio_dev); 1908 1909 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); 1910 if (ret != 0) { 1911 dev_err(&pdev->dev, "missing reg property\n"); 1912 return -EINVAL; 1913 } 1914 1915 adc->irq = platform_get_irq(pdev, 0); 1916 if (adc->irq < 0) 1917 return adc->irq; 1918 1919 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, 1920 stm32_adc_threaded_isr, 1921 0, pdev->name, indio_dev); 1922 if (ret) { 1923 dev_err(&pdev->dev, "failed to request IRQ\n"); 1924 return ret; 1925 } 1926 1927 adc->clk = devm_clk_get(&pdev->dev, NULL); 1928 if (IS_ERR(adc->clk)) { 1929 ret = PTR_ERR(adc->clk); 1930 if (ret == -ENOENT && !adc->cfg->clk_required) { 1931 adc->clk = NULL; 1932 } else { 1933 dev_err(&pdev->dev, "Can't get clock\n"); 1934 return ret; 1935 } 1936 } 1937 1938 ret = stm32_adc_of_get_resolution(indio_dev); 1939 if (ret < 0) 1940 return ret; 1941 1942 ret = stm32_adc_chan_of_init(indio_dev); 1943 if (ret < 0) 1944 return ret; 1945 1946 ret = stm32_adc_dma_request(dev, indio_dev); 1947 if (ret < 0) 1948 return ret; 1949 1950 if (!adc->dma_chan) 1951 handler = &stm32_adc_trigger_handler; 1952 1953 ret = iio_triggered_buffer_setup(indio_dev, 1954 &iio_pollfunc_store_time, handler, 1955 &stm32_adc_buffer_setup_ops); 1956 if (ret) { 1957 dev_err(&pdev->dev, "buffer setup failed\n"); 1958 goto err_dma_disable; 1959 } 1960 1961 /* Get stm32-adc-core PM online */ 1962 pm_runtime_get_noresume(dev); 1963 pm_runtime_set_active(dev); 1964 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS); 1965 pm_runtime_use_autosuspend(dev); 1966 pm_runtime_enable(dev); 1967 1968 ret = stm32_adc_hw_start(dev); 1969 if (ret) 1970 goto err_buffer_cleanup; 1971 1972 ret = iio_device_register(indio_dev); 1973 if (ret) { 1974 dev_err(&pdev->dev, "iio dev register failed\n"); 1975 goto err_hw_stop; 1976 } 1977 1978 pm_runtime_mark_last_busy(dev); 1979 pm_runtime_put_autosuspend(dev); 1980 1981 return 0; 1982 1983err_hw_stop: 1984 stm32_adc_hw_stop(dev); 1985 1986err_buffer_cleanup: 1987 pm_runtime_disable(dev); 1988 pm_runtime_set_suspended(dev); 1989 pm_runtime_put_noidle(dev); 1990 iio_triggered_buffer_cleanup(indio_dev); 1991 1992err_dma_disable: 1993 if (adc->dma_chan) { 1994 dma_free_coherent(adc->dma_chan->device->dev, 1995 STM32_DMA_BUFFER_SIZE, 1996 adc->rx_buf, adc->rx_dma_buf); 1997 dma_release_channel(adc->dma_chan); 1998 } 1999 2000 return ret; 2001} 2002 2003static int stm32_adc_remove(struct platform_device *pdev) 2004{ 2005 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2006 struct stm32_adc *adc = iio_priv(indio_dev); 2007 2008 pm_runtime_get_sync(&pdev->dev); 2009 iio_device_unregister(indio_dev); 2010 stm32_adc_hw_stop(&pdev->dev); 2011 pm_runtime_disable(&pdev->dev); 2012 pm_runtime_set_suspended(&pdev->dev); 2013 pm_runtime_put_noidle(&pdev->dev); 2014 iio_triggered_buffer_cleanup(indio_dev); 2015 if (adc->dma_chan) { 2016 dma_free_coherent(adc->dma_chan->device->dev, 2017 STM32_DMA_BUFFER_SIZE, 2018 adc->rx_buf, adc->rx_dma_buf); 2019 dma_release_channel(adc->dma_chan); 2020 } 2021 2022 return 0; 2023} 2024 2025#if defined(CONFIG_PM_SLEEP) 2026static int stm32_adc_suspend(struct device *dev) 2027{ 2028 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2029 2030 if (iio_buffer_enabled(indio_dev)) 2031 stm32_adc_buffer_predisable(indio_dev); 2032 2033 return pm_runtime_force_suspend(dev); 2034} 2035 2036static int stm32_adc_resume(struct device *dev) 2037{ 2038 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2039 int ret; 2040 2041 ret = pm_runtime_force_resume(dev); 2042 if (ret < 0) 2043 return ret; 2044 2045 if (!iio_buffer_enabled(indio_dev)) 2046 return 0; 2047 2048 ret = stm32_adc_update_scan_mode(indio_dev, 2049 indio_dev->active_scan_mask); 2050 if (ret < 0) 2051 return ret; 2052 2053 return stm32_adc_buffer_postenable(indio_dev); 2054} 2055#endif 2056 2057#if defined(CONFIG_PM) 2058static int stm32_adc_runtime_suspend(struct device *dev) 2059{ 2060 return stm32_adc_hw_stop(dev); 2061} 2062 2063static int stm32_adc_runtime_resume(struct device *dev) 2064{ 2065 return stm32_adc_hw_start(dev); 2066} 2067#endif 2068 2069static const struct dev_pm_ops stm32_adc_pm_ops = { 2070 SET_SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume) 2071 SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume, 2072 NULL) 2073}; 2074 2075static const struct stm32_adc_cfg stm32f4_adc_cfg = { 2076 .regs = &stm32f4_adc_regspec, 2077 .adc_info = &stm32f4_adc_info, 2078 .trigs = stm32f4_adc_trigs, 2079 .clk_required = true, 2080 .start_conv = stm32f4_adc_start_conv, 2081 .stop_conv = stm32f4_adc_stop_conv, 2082 .smp_cycles = stm32f4_adc_smp_cycles, 2083 .irq_clear = stm32f4_adc_irq_clear, 2084}; 2085 2086static const struct stm32_adc_cfg stm32h7_adc_cfg = { 2087 .regs = &stm32h7_adc_regspec, 2088 .adc_info = &stm32h7_adc_info, 2089 .trigs = stm32h7_adc_trigs, 2090 .start_conv = stm32h7_adc_start_conv, 2091 .stop_conv = stm32h7_adc_stop_conv, 2092 .prepare = stm32h7_adc_prepare, 2093 .unprepare = stm32h7_adc_unprepare, 2094 .smp_cycles = stm32h7_adc_smp_cycles, 2095 .irq_clear = stm32h7_adc_irq_clear, 2096}; 2097 2098static const struct stm32_adc_cfg stm32mp1_adc_cfg = { 2099 .regs = &stm32h7_adc_regspec, 2100 .adc_info = &stm32h7_adc_info, 2101 .trigs = stm32h7_adc_trigs, 2102 .has_vregready = true, 2103 .start_conv = stm32h7_adc_start_conv, 2104 .stop_conv = stm32h7_adc_stop_conv, 2105 .prepare = stm32h7_adc_prepare, 2106 .unprepare = stm32h7_adc_unprepare, 2107 .smp_cycles = stm32h7_adc_smp_cycles, 2108 .irq_clear = stm32h7_adc_irq_clear, 2109}; 2110 2111static const struct of_device_id stm32_adc_of_match[] = { 2112 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 2113 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 2114 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 2115 {}, 2116}; 2117MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 2118 2119static struct platform_driver stm32_adc_driver = { 2120 .probe = stm32_adc_probe, 2121 .remove = stm32_adc_remove, 2122 .driver = { 2123 .name = "stm32-adc", 2124 .of_match_table = stm32_adc_of_match, 2125 .pm = &stm32_adc_pm_ops, 2126 }, 2127}; 2128module_platform_driver(stm32_adc_driver); 2129 2130MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 2131MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 2132MODULE_LICENSE("GPL v2"); 2133MODULE_ALIAS("platform:stm32-adc"); 2134