1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 */
9
10#ifndef __STM32_ADC_H
11#define __STM32_ADC_H
12
13/*
14 * STM32 - ADC global register map
15 * ________________________________________________________
16 * | Offset |                 Register                    |
17 * --------------------------------------------------------
18 * | 0x000  |                Master ADC1                  |
19 * --------------------------------------------------------
20 * | 0x100  |                Slave ADC2                   |
21 * --------------------------------------------------------
22 * | 0x200  |                Slave ADC3                   |
23 * --------------------------------------------------------
24 * | 0x300  |         Master & Slave common regs          |
25 * --------------------------------------------------------
26 */
27#define STM32_ADC_MAX_ADCS		3
28#define STM32_ADC_OFFSET		0x100
29#define STM32_ADCX_COMN_OFFSET		0x300
30
31/* STM32F4 - Registers for each ADC instance */
32#define STM32F4_ADC_SR			0x00
33#define STM32F4_ADC_CR1			0x04
34#define STM32F4_ADC_CR2			0x08
35#define STM32F4_ADC_SMPR1		0x0C
36#define STM32F4_ADC_SMPR2		0x10
37#define STM32F4_ADC_HTR			0x24
38#define STM32F4_ADC_LTR			0x28
39#define STM32F4_ADC_SQR1		0x2C
40#define STM32F4_ADC_SQR2		0x30
41#define STM32F4_ADC_SQR3		0x34
42#define STM32F4_ADC_JSQR		0x38
43#define STM32F4_ADC_JDR1		0x3C
44#define STM32F4_ADC_JDR2		0x40
45#define STM32F4_ADC_JDR3		0x44
46#define STM32F4_ADC_JDR4		0x48
47#define STM32F4_ADC_DR			0x4C
48
49/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
50#define STM32F4_ADC_CSR			(STM32_ADCX_COMN_OFFSET + 0x00)
51#define STM32F4_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x04)
52
53/* STM32F4_ADC_SR - bit fields */
54#define STM32F4_OVR			BIT(5)
55#define STM32F4_STRT			BIT(4)
56#define STM32F4_EOC			BIT(1)
57
58/* STM32F4_ADC_CR1 - bit fields */
59#define STM32F4_OVRIE			BIT(26)
60#define STM32F4_RES_SHIFT		24
61#define STM32F4_RES_MASK		GENMASK(25, 24)
62#define STM32F4_SCAN			BIT(8)
63#define STM32F4_EOCIE			BIT(5)
64
65/* STM32F4_ADC_CR2 - bit fields */
66#define STM32F4_SWSTART			BIT(30)
67#define STM32F4_EXTEN_SHIFT		28
68#define STM32F4_EXTEN_MASK		GENMASK(29, 28)
69#define STM32F4_EXTSEL_SHIFT		24
70#define STM32F4_EXTSEL_MASK		GENMASK(27, 24)
71#define STM32F4_EOCS			BIT(10)
72#define STM32F4_DDS			BIT(9)
73#define STM32F4_DMA			BIT(8)
74#define STM32F4_ADON			BIT(0)
75
76/* STM32F4_ADC_CSR - bit fields */
77#define STM32F4_OVR3			BIT(21)
78#define STM32F4_EOC3			BIT(17)
79#define STM32F4_OVR2			BIT(13)
80#define STM32F4_EOC2			BIT(9)
81#define STM32F4_OVR1			BIT(5)
82#define STM32F4_EOC1			BIT(1)
83
84/* STM32F4_ADC_CCR - bit fields */
85#define STM32F4_ADC_ADCPRE_SHIFT	16
86#define STM32F4_ADC_ADCPRE_MASK		GENMASK(17, 16)
87
88/* STM32H7 - Registers for each ADC instance */
89#define STM32H7_ADC_ISR			0x00
90#define STM32H7_ADC_IER			0x04
91#define STM32H7_ADC_CR			0x08
92#define STM32H7_ADC_CFGR		0x0C
93#define STM32H7_ADC_SMPR1		0x14
94#define STM32H7_ADC_SMPR2		0x18
95#define STM32H7_ADC_PCSEL		0x1C
96#define STM32H7_ADC_SQR1		0x30
97#define STM32H7_ADC_SQR2		0x34
98#define STM32H7_ADC_SQR3		0x38
99#define STM32H7_ADC_SQR4		0x3C
100#define STM32H7_ADC_DR			0x40
101#define STM32H7_ADC_DIFSEL		0xC0
102#define STM32H7_ADC_CALFACT		0xC4
103#define STM32H7_ADC_CALFACT2		0xC8
104
105/* STM32H7 - common registers for all ADC instances */
106#define STM32H7_ADC_CSR			(STM32_ADCX_COMN_OFFSET + 0x00)
107#define STM32H7_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x08)
108
109/* STM32H7_ADC_ISR - bit fields */
110#define STM32MP1_VREGREADY		BIT(12)
111#define STM32H7_OVR			BIT(4)
112#define STM32H7_EOC			BIT(2)
113#define STM32H7_ADRDY			BIT(0)
114
115/* STM32H7_ADC_IER - bit fields */
116#define STM32H7_OVRIE			STM32H7_OVR
117#define STM32H7_EOCIE			STM32H7_EOC
118
119/* STM32H7_ADC_CR - bit fields */
120#define STM32H7_ADCAL			BIT(31)
121#define STM32H7_ADCALDIF		BIT(30)
122#define STM32H7_DEEPPWD			BIT(29)
123#define STM32H7_ADVREGEN		BIT(28)
124#define STM32H7_LINCALRDYW6		BIT(27)
125#define STM32H7_LINCALRDYW5		BIT(26)
126#define STM32H7_LINCALRDYW4		BIT(25)
127#define STM32H7_LINCALRDYW3		BIT(24)
128#define STM32H7_LINCALRDYW2		BIT(23)
129#define STM32H7_LINCALRDYW1		BIT(22)
130#define STM32H7_ADCALLIN		BIT(16)
131#define STM32H7_BOOST			BIT(8)
132#define STM32H7_ADSTP			BIT(4)
133#define STM32H7_ADSTART			BIT(2)
134#define STM32H7_ADDIS			BIT(1)
135#define STM32H7_ADEN			BIT(0)
136
137/* STM32H7_ADC_CFGR bit fields */
138#define STM32H7_EXTEN_SHIFT		10
139#define STM32H7_EXTEN_MASK		GENMASK(11, 10)
140#define STM32H7_EXTSEL_SHIFT		5
141#define STM32H7_EXTSEL_MASK		GENMASK(9, 5)
142#define STM32H7_RES_SHIFT		2
143#define STM32H7_RES_MASK		GENMASK(4, 2)
144#define STM32H7_DMNGT_SHIFT		0
145#define STM32H7_DMNGT_MASK		GENMASK(1, 0)
146
147enum stm32h7_adc_dmngt {
148	STM32H7_DMNGT_DR_ONLY,		/* Regular data in DR only */
149	STM32H7_DMNGT_DMA_ONESHOT,	/* DMA one shot mode */
150	STM32H7_DMNGT_DFSDM,		/* DFSDM mode */
151	STM32H7_DMNGT_DMA_CIRC,		/* DMA circular mode */
152};
153
154/* STM32H7_ADC_CALFACT - bit fields */
155#define STM32H7_CALFACT_D_SHIFT		16
156#define STM32H7_CALFACT_D_MASK		GENMASK(26, 16)
157#define STM32H7_CALFACT_S_SHIFT		0
158#define STM32H7_CALFACT_S_MASK		GENMASK(10, 0)
159
160/* STM32H7_ADC_CALFACT2 - bit fields */
161#define STM32H7_LINCALFACT_SHIFT	0
162#define STM32H7_LINCALFACT_MASK		GENMASK(29, 0)
163
164/* STM32H7_ADC_CSR - bit fields */
165#define STM32H7_OVR_SLV			BIT(20)
166#define STM32H7_EOC_SLV			BIT(18)
167#define STM32H7_OVR_MST			BIT(4)
168#define STM32H7_EOC_MST			BIT(2)
169
170/* STM32H7_ADC_CCR - bit fields */
171#define STM32H7_PRESC_SHIFT		18
172#define STM32H7_PRESC_MASK		GENMASK(21, 18)
173#define STM32H7_CKMODE_SHIFT		16
174#define STM32H7_CKMODE_MASK		GENMASK(17, 16)
175
176/**
177 * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
178 * @base:		control registers base cpu addr
179 * @phys_base:		control registers base physical addr
180 * @rate:		clock rate used for analog circuitry
181 * @vref_mv:		vref voltage (mv)
182 */
183struct stm32_adc_common {
184	void __iomem			*base;
185	phys_addr_t			phys_base;
186	unsigned long			rate;
187	int				vref_mv;
188};
189
190#endif
191