1// SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * iio/adc/max1027.c
4  * Copyright (C) 2014 Philippe Reynes
5  *
6  * based on linux/drivers/iio/ad7923.c
7  * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
8  * Copyright 2012 CS Systemes d'Information
9  *
10  * max1027.c
11  *
12  * Partial support for max1027 and similar chips.
13  */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mod_devicetable.h>
18#include <linux/spi/spi.h>
19#include <linux/delay.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/trigger.h>
24#include <linux/iio/trigger_consumer.h>
25#include <linux/iio/triggered_buffer.h>
26
27#define MAX1027_CONV_REG  BIT(7)
28#define MAX1027_SETUP_REG BIT(6)
29#define MAX1027_AVG_REG   BIT(5)
30#define MAX1027_RST_REG   BIT(4)
31
32/* conversion register */
33#define MAX1027_TEMP      BIT(0)
34#define MAX1027_SCAN_0_N  (0x00 << 1)
35#define MAX1027_SCAN_N_M  (0x01 << 1)
36#define MAX1027_SCAN_N    (0x02 << 1)
37#define MAX1027_NOSCAN    (0x03 << 1)
38#define MAX1027_CHAN(n)   ((n) << 3)
39
40/* setup register */
41#define MAX1027_UNIPOLAR  0x02
42#define MAX1027_BIPOLAR   0x03
43#define MAX1027_REF_MODE0 (0x00 << 2)
44#define MAX1027_REF_MODE1 (0x01 << 2)
45#define MAX1027_REF_MODE2 (0x02 << 2)
46#define MAX1027_REF_MODE3 (0x03 << 2)
47#define MAX1027_CKS_MODE0 (0x00 << 4)
48#define MAX1027_CKS_MODE1 (0x01 << 4)
49#define MAX1027_CKS_MODE2 (0x02 << 4)
50#define MAX1027_CKS_MODE3 (0x03 << 4)
51
52/* averaging register */
53#define MAX1027_NSCAN_4   0x00
54#define MAX1027_NSCAN_8   0x01
55#define MAX1027_NSCAN_12  0x02
56#define MAX1027_NSCAN_16  0x03
57#define MAX1027_NAVG_4    (0x00 << 2)
58#define MAX1027_NAVG_8    (0x01 << 2)
59#define MAX1027_NAVG_16   (0x02 << 2)
60#define MAX1027_NAVG_32   (0x03 << 2)
61#define MAX1027_AVG_EN    BIT(4)
62
63enum max1027_id {
64	max1027,
65	max1029,
66	max1031,
67	max1227,
68	max1229,
69	max1231,
70};
71
72static const struct spi_device_id max1027_id[] = {
73	{"max1027", max1027},
74	{"max1029", max1029},
75	{"max1031", max1031},
76	{"max1227", max1227},
77	{"max1229", max1229},
78	{"max1231", max1231},
79	{}
80};
81MODULE_DEVICE_TABLE(spi, max1027_id);
82
83static const struct of_device_id max1027_adc_dt_ids[] = {
84	{ .compatible = "maxim,max1027" },
85	{ .compatible = "maxim,max1029" },
86	{ .compatible = "maxim,max1031" },
87	{ .compatible = "maxim,max1227" },
88	{ .compatible = "maxim,max1229" },
89	{ .compatible = "maxim,max1231" },
90	{},
91};
92MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
93
94#define MAX1027_V_CHAN(index, depth)					\
95	{								\
96		.type = IIO_VOLTAGE,					\
97		.indexed = 1,						\
98		.channel = index,					\
99		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
100		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
101		.scan_index = index + 1,				\
102		.scan_type = {						\
103			.sign = 'u',					\
104			.realbits = depth,				\
105			.storagebits = 16,				\
106			.shift = (depth == 10) ? 2 : 0,			\
107			.endianness = IIO_BE,				\
108		},							\
109	}
110
111#define MAX1027_T_CHAN							\
112	{								\
113		.type = IIO_TEMP,					\
114		.channel = 0,						\
115		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
116		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
117		.scan_index = 0,					\
118		.scan_type = {						\
119			.sign = 'u',					\
120			.realbits = 12,					\
121			.storagebits = 16,				\
122			.endianness = IIO_BE,				\
123		},							\
124	}
125
126#define MAX1X27_CHANNELS(depth)			\
127	MAX1027_T_CHAN,				\
128	MAX1027_V_CHAN(0, depth),		\
129	MAX1027_V_CHAN(1, depth),		\
130	MAX1027_V_CHAN(2, depth),		\
131	MAX1027_V_CHAN(3, depth),		\
132	MAX1027_V_CHAN(4, depth),		\
133	MAX1027_V_CHAN(5, depth),		\
134	MAX1027_V_CHAN(6, depth),		\
135	MAX1027_V_CHAN(7, depth)
136
137#define MAX1X29_CHANNELS(depth)			\
138	MAX1X27_CHANNELS(depth),		\
139	MAX1027_V_CHAN(8, depth),		\
140	MAX1027_V_CHAN(9, depth),		\
141	MAX1027_V_CHAN(10, depth),		\
142	MAX1027_V_CHAN(11, depth)
143
144#define MAX1X31_CHANNELS(depth)			\
145	MAX1X29_CHANNELS(depth),		\
146	MAX1027_V_CHAN(12, depth),		\
147	MAX1027_V_CHAN(13, depth),		\
148	MAX1027_V_CHAN(14, depth),		\
149	MAX1027_V_CHAN(15, depth)
150
151static const struct iio_chan_spec max1027_channels[] = {
152	MAX1X27_CHANNELS(10),
153};
154
155static const struct iio_chan_spec max1029_channels[] = {
156	MAX1X29_CHANNELS(10),
157};
158
159static const struct iio_chan_spec max1031_channels[] = {
160	MAX1X31_CHANNELS(10),
161};
162
163static const struct iio_chan_spec max1227_channels[] = {
164	MAX1X27_CHANNELS(12),
165};
166
167static const struct iio_chan_spec max1229_channels[] = {
168	MAX1X29_CHANNELS(12),
169};
170
171static const struct iio_chan_spec max1231_channels[] = {
172	MAX1X31_CHANNELS(12),
173};
174
175static const unsigned long max1027_available_scan_masks[] = {
176	0x000001ff,
177	0x00000000,
178};
179
180static const unsigned long max1029_available_scan_masks[] = {
181	0x00001fff,
182	0x00000000,
183};
184
185static const unsigned long max1031_available_scan_masks[] = {
186	0x0001ffff,
187	0x00000000,
188};
189
190struct max1027_chip_info {
191	const struct iio_chan_spec *channels;
192	unsigned int num_channels;
193	const unsigned long *available_scan_masks;
194};
195
196static const struct max1027_chip_info max1027_chip_info_tbl[] = {
197	[max1027] = {
198		.channels = max1027_channels,
199		.num_channels = ARRAY_SIZE(max1027_channels),
200		.available_scan_masks = max1027_available_scan_masks,
201	},
202	[max1029] = {
203		.channels = max1029_channels,
204		.num_channels = ARRAY_SIZE(max1029_channels),
205		.available_scan_masks = max1029_available_scan_masks,
206	},
207	[max1031] = {
208		.channels = max1031_channels,
209		.num_channels = ARRAY_SIZE(max1031_channels),
210		.available_scan_masks = max1031_available_scan_masks,
211	},
212	[max1227] = {
213		.channels = max1227_channels,
214		.num_channels = ARRAY_SIZE(max1227_channels),
215		.available_scan_masks = max1027_available_scan_masks,
216	},
217	[max1229] = {
218		.channels = max1229_channels,
219		.num_channels = ARRAY_SIZE(max1229_channels),
220		.available_scan_masks = max1029_available_scan_masks,
221	},
222	[max1231] = {
223		.channels = max1231_channels,
224		.num_channels = ARRAY_SIZE(max1231_channels),
225		.available_scan_masks = max1031_available_scan_masks,
226	},
227};
228
229struct max1027_state {
230	const struct max1027_chip_info	*info;
231	struct spi_device		*spi;
232	struct iio_trigger		*trig;
233	__be16				*buffer;
234	struct mutex			lock;
235
236	u8				reg ____cacheline_aligned;
237};
238
239static int max1027_read_single_value(struct iio_dev *indio_dev,
240				     struct iio_chan_spec const *chan,
241				     int *val)
242{
243	int ret;
244	struct max1027_state *st = iio_priv(indio_dev);
245
246	if (iio_buffer_enabled(indio_dev)) {
247		dev_warn(&indio_dev->dev, "trigger mode already enabled");
248		return -EBUSY;
249	}
250
251	/* Start acquisition on conversion register write */
252	st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
253	ret = spi_write(st->spi, &st->reg, 1);
254	if (ret < 0) {
255		dev_err(&indio_dev->dev,
256			"Failed to configure setup register\n");
257		return ret;
258	}
259
260	/* Configure conversion register with the requested chan */
261	st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
262		  MAX1027_NOSCAN;
263	if (chan->type == IIO_TEMP)
264		st->reg |= MAX1027_TEMP;
265	ret = spi_write(st->spi, &st->reg, 1);
266	if (ret < 0) {
267		dev_err(&indio_dev->dev,
268			"Failed to configure conversion register\n");
269		return ret;
270	}
271
272	/*
273	 * For an unknown reason, when we use the mode "10" (write
274	 * conversion register), the interrupt doesn't occur every time.
275	 * So we just wait 1 ms.
276	 */
277	mdelay(1);
278
279	/* Read result */
280	ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
281	if (ret < 0)
282		return ret;
283
284	*val = be16_to_cpu(st->buffer[0]);
285
286	return IIO_VAL_INT;
287}
288
289static int max1027_read_raw(struct iio_dev *indio_dev,
290			    struct iio_chan_spec const *chan,
291			    int *val, int *val2, long mask)
292{
293	int ret = 0;
294	struct max1027_state *st = iio_priv(indio_dev);
295
296	mutex_lock(&st->lock);
297
298	switch (mask) {
299	case IIO_CHAN_INFO_RAW:
300		ret = max1027_read_single_value(indio_dev, chan, val);
301		break;
302	case IIO_CHAN_INFO_SCALE:
303		switch (chan->type) {
304		case IIO_TEMP:
305			*val = 1;
306			*val2 = 8;
307			ret = IIO_VAL_FRACTIONAL;
308			break;
309		case IIO_VOLTAGE:
310			*val = 2500;
311			*val2 = chan->scan_type.realbits;
312			ret = IIO_VAL_FRACTIONAL_LOG2;
313			break;
314		default:
315			ret = -EINVAL;
316			break;
317		}
318		break;
319	default:
320		ret = -EINVAL;
321		break;
322	}
323
324	mutex_unlock(&st->lock);
325
326	return ret;
327}
328
329static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
330				      unsigned reg, unsigned writeval,
331				      unsigned *readval)
332{
333	struct max1027_state *st = iio_priv(indio_dev);
334	u8 *val = (u8 *)st->buffer;
335
336	if (readval) {
337		int ret = spi_read(st->spi, val, 2);
338		*readval = be16_to_cpu(st->buffer[0]);
339		return ret;
340	}
341
342	*val = (u8)writeval;
343	return spi_write(st->spi, val, 1);
344}
345
346static int max1027_validate_trigger(struct iio_dev *indio_dev,
347				    struct iio_trigger *trig)
348{
349	struct max1027_state *st = iio_priv(indio_dev);
350
351	if (st->trig != trig)
352		return -EINVAL;
353
354	return 0;
355}
356
357static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
358{
359	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
360	struct max1027_state *st = iio_priv(indio_dev);
361	int ret;
362
363	if (state) {
364		/* Start acquisition on cnvst */
365		st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
366			  MAX1027_REF_MODE2;
367		ret = spi_write(st->spi, &st->reg, 1);
368		if (ret < 0)
369			return ret;
370
371		/* Scan from 0 to max */
372		st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
373			  MAX1027_SCAN_N_M | MAX1027_TEMP;
374		ret = spi_write(st->spi, &st->reg, 1);
375		if (ret < 0)
376			return ret;
377	} else {
378		/* Start acquisition on conversion register write */
379		st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2	|
380			  MAX1027_REF_MODE2;
381		ret = spi_write(st->spi, &st->reg, 1);
382		if (ret < 0)
383			return ret;
384	}
385
386	return 0;
387}
388
389static irqreturn_t max1027_trigger_handler(int irq, void *private)
390{
391	struct iio_poll_func *pf = private;
392	struct iio_dev *indio_dev = pf->indio_dev;
393	struct max1027_state *st = iio_priv(indio_dev);
394
395	pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
396
397	/* fill buffer with all channel */
398	spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
399
400	iio_push_to_buffers(indio_dev, st->buffer);
401
402	iio_trigger_notify_done(indio_dev->trig);
403
404	return IRQ_HANDLED;
405}
406
407static const struct iio_trigger_ops max1027_trigger_ops = {
408	.validate_device = &iio_trigger_validate_own_device,
409	.set_trigger_state = &max1027_set_trigger_state,
410};
411
412static const struct iio_info max1027_info = {
413	.read_raw = &max1027_read_raw,
414	.validate_trigger = &max1027_validate_trigger,
415	.debugfs_reg_access = &max1027_debugfs_reg_access,
416};
417
418static int max1027_probe(struct spi_device *spi)
419{
420	int ret;
421	struct iio_dev *indio_dev;
422	struct max1027_state *st;
423
424	pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
425
426	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
427	if (indio_dev == NULL) {
428		pr_err("Can't allocate iio device\n");
429		return -ENOMEM;
430	}
431
432	spi_set_drvdata(spi, indio_dev);
433
434	st = iio_priv(indio_dev);
435	st->spi = spi;
436	st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
437
438	mutex_init(&st->lock);
439
440	indio_dev->name = spi_get_device_id(spi)->name;
441	indio_dev->info = &max1027_info;
442	indio_dev->modes = INDIO_DIRECT_MODE;
443	indio_dev->channels = st->info->channels;
444	indio_dev->num_channels = st->info->num_channels;
445	indio_dev->available_scan_masks = st->info->available_scan_masks;
446
447	st->buffer = devm_kmalloc_array(&indio_dev->dev,
448				  indio_dev->num_channels, 2,
449				  GFP_KERNEL);
450	if (st->buffer == NULL) {
451		dev_err(&indio_dev->dev, "Can't allocate buffer\n");
452		return -ENOMEM;
453	}
454
455	if (spi->irq) {
456		ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
457						      &iio_pollfunc_store_time,
458						      &max1027_trigger_handler,
459						      NULL);
460		if (ret < 0) {
461			dev_err(&indio_dev->dev, "Failed to setup buffer\n");
462			return ret;
463		}
464
465		st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
466						  indio_dev->name);
467		if (st->trig == NULL) {
468			ret = -ENOMEM;
469			dev_err(&indio_dev->dev,
470				"Failed to allocate iio trigger\n");
471			return ret;
472		}
473
474		st->trig->ops = &max1027_trigger_ops;
475		st->trig->dev.parent = &spi->dev;
476		iio_trigger_set_drvdata(st->trig, indio_dev);
477		ret = devm_iio_trigger_register(&indio_dev->dev,
478						st->trig);
479		if (ret < 0) {
480			dev_err(&indio_dev->dev,
481				"Failed to register iio trigger\n");
482			return ret;
483		}
484
485		ret = devm_request_threaded_irq(&spi->dev, spi->irq,
486						iio_trigger_generic_data_rdy_poll,
487						NULL,
488						IRQF_TRIGGER_FALLING,
489						spi->dev.driver->name,
490						st->trig);
491		if (ret < 0) {
492			dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
493			return ret;
494		}
495	}
496
497	/* Internal reset */
498	st->reg = MAX1027_RST_REG;
499	ret = spi_write(st->spi, &st->reg, 1);
500	if (ret < 0) {
501		dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
502		return ret;
503	}
504
505	/* Disable averaging */
506	st->reg = MAX1027_AVG_REG;
507	ret = spi_write(st->spi, &st->reg, 1);
508	if (ret < 0) {
509		dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
510		return ret;
511	}
512
513	return devm_iio_device_register(&spi->dev, indio_dev);
514}
515
516static struct spi_driver max1027_driver = {
517	.driver = {
518		.name	= "max1027",
519		.of_match_table = max1027_adc_dt_ids,
520	},
521	.probe		= max1027_probe,
522	.id_table	= max1027_id,
523};
524module_spi_driver(max1027_driver);
525
526MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
527MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC");
528MODULE_LICENSE("GPL v2");
529