1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for the ADC present in the Atmel AT91 evaluation boards. 4 * 5 * Copyright 2011 Free Electrons 6 */ 7 8#include <linux/bitmap.h> 9#include <linux/bitops.h> 10#include <linux/clk.h> 11#include <linux/err.h> 12#include <linux/io.h> 13#include <linux/input.h> 14#include <linux/interrupt.h> 15#include <linux/jiffies.h> 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/of_device.h> 20#include <linux/platform_device.h> 21#include <linux/sched.h> 22#include <linux/slab.h> 23#include <linux/wait.h> 24 25#include <linux/platform_data/at91_adc.h> 26 27#include <linux/iio/iio.h> 28#include <linux/iio/buffer.h> 29#include <linux/iio/trigger.h> 30#include <linux/iio/trigger_consumer.h> 31#include <linux/iio/triggered_buffer.h> 32#include <linux/pinctrl/consumer.h> 33 34/* Registers */ 35#define AT91_ADC_CR 0x00 /* Control Register */ 36#define AT91_ADC_SWRST (1 << 0) /* Software Reset */ 37#define AT91_ADC_START (1 << 1) /* Start Conversion */ 38 39#define AT91_ADC_MR 0x04 /* Mode Register */ 40#define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ 41#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ 42#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ 43#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ 44#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ 45#define AT91_ADC_TRGSEL_TC0 (0 << 1) 46#define AT91_ADC_TRGSEL_TC1 (1 << 1) 47#define AT91_ADC_TRGSEL_TC2 (2 << 1) 48#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) 49#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ 50#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ 51#define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ 52#define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ 53#define AT91_ADC_PRESCAL_9G45 (0xff << 8) 54#define AT91_ADC_PRESCAL_(x) ((x) << 8) 55#define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ 56#define AT91_ADC_STARTUP_9G45 (0x7f << 16) 57#define AT91_ADC_STARTUP_9X5 (0xf << 16) 58#define AT91_ADC_STARTUP_(x) ((x) << 16) 59#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ 60#define AT91_ADC_SHTIM_(x) ((x) << 24) 61#define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ 62#define AT91_ADC_PENDBC_(x) ((x) << 28) 63 64#define AT91_ADC_TSR 0x0C 65#define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ 66#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) 67 68#define AT91_ADC_CHER 0x10 /* Channel Enable Register */ 69#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ 70#define AT91_ADC_CHSR 0x18 /* Channel Status Register */ 71#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ 72 73#define AT91_ADC_SR 0x1C /* Status Register */ 74#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ 75#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ 76#define AT91_ADC_DRDY (1 << 16) /* Data Ready */ 77#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ 78#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ 79#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ 80 81#define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ 82#define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ 83 84#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ 85#define AT91_ADC_LDATA (0x3ff) 86 87#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ 88#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ 89#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ 90#define AT91RL_ADC_IER_PEN (1 << 20) 91#define AT91RL_ADC_IER_NOPEN (1 << 21) 92#define AT91_ADC_IER_PEN (1 << 29) 93#define AT91_ADC_IER_NOPEN (1 << 30) 94#define AT91_ADC_IER_XRDY (1 << 20) 95#define AT91_ADC_IER_YRDY (1 << 21) 96#define AT91_ADC_IER_PRDY (1 << 22) 97#define AT91_ADC_ISR_PENS (1 << 31) 98 99#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ 100#define AT91_ADC_DATA (0x3ff) 101 102#define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ 103 104#define AT91_ADC_ACR 0x94 /* Analog Control Register */ 105#define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ 106 107#define AT91_ADC_TSMR 0xB0 108#define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ 109#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) 110#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) 111#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) 112#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) 113#define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ 114#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) 115#define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ 116#define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16) 117#define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ 118#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) 119#define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ 120#define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ 121#define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ 122 123#define AT91_ADC_TSXPOSR 0xB4 124#define AT91_ADC_TSYPOSR 0xB8 125#define AT91_ADC_TSPRESSR 0xBC 126 127#define AT91_ADC_TRGR_9260 AT91_ADC_MR 128#define AT91_ADC_TRGR_9G45 0x08 129#define AT91_ADC_TRGR_9X5 0xC0 130 131/* Trigger Register bit field */ 132#define AT91_ADC_TRGR_TRGPER (0xffff << 16) 133#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) 134#define AT91_ADC_TRGR_TRGMOD (0x7 << 0) 135#define AT91_ADC_TRGR_NONE (0 << 0) 136#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) 137 138#define AT91_ADC_CHAN(st, ch) \ 139 (st->registers->channel_base + (ch * 4)) 140#define at91_adc_readl(st, reg) \ 141 (readl_relaxed(st->reg_base + reg)) 142#define at91_adc_writel(st, reg, val) \ 143 (writel_relaxed(val, st->reg_base + reg)) 144 145#define DRIVER_NAME "at91_adc" 146#define MAX_POS_BITS 12 147 148#define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 149#define TOUCH_PEN_DETECT_DEBOUNCE_US 200 150 151#define MAX_RLPOS_BITS 10 152#define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ 153#define TOUCH_SHTIM 0xa 154#define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */ 155 156/** 157 * struct at91_adc_reg_desc - Various informations relative to registers 158 * @channel_base: Base offset for the channel data registers 159 * @drdy_mask: Mask of the DRDY field in the relevant registers 160 * (Interruptions registers mostly) 161 * @status_register: Offset of the Interrupt Status Register 162 * @trigger_register: Offset of the Trigger setup register 163 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register 164 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register 165 */ 166struct at91_adc_reg_desc { 167 u8 channel_base; 168 u32 drdy_mask; 169 u8 status_register; 170 u8 trigger_register; 171 u32 mr_prescal_mask; 172 u32 mr_startup_mask; 173}; 174 175struct at91_adc_caps { 176 bool has_ts; /* Support touch screen */ 177 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ 178 /* 179 * Numbers of sampling data will be averaged. Can be 0~3. 180 * Hardware can average (2 ^ ts_filter_average) sample data. 181 */ 182 u8 ts_filter_average; 183 /* Pen Detection input pull-up resistor, can be 0~3 */ 184 u8 ts_pen_detect_sensitivity; 185 186 /* startup time calculate function */ 187 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); 188 189 u8 num_channels; 190 struct at91_adc_reg_desc registers; 191}; 192 193struct at91_adc_state { 194 struct clk *adc_clk; 195 u16 *buffer; 196 unsigned long channels_mask; 197 struct clk *clk; 198 bool done; 199 int irq; 200 u16 last_value; 201 int chnb; 202 struct mutex lock; 203 u8 num_channels; 204 void __iomem *reg_base; 205 struct at91_adc_reg_desc *registers; 206 u32 startup_time; 207 u8 sample_hold_time; 208 bool sleep_mode; 209 struct iio_trigger **trig; 210 struct at91_adc_trigger *trigger_list; 211 u32 trigger_number; 212 bool use_external; 213 u32 vref_mv; 214 u32 res; /* resolution used for convertions */ 215 bool low_res; /* the resolution corresponds to the lowest one */ 216 wait_queue_head_t wq_data_avail; 217 struct at91_adc_caps *caps; 218 219 /* 220 * Following ADC channels are shared by touchscreen: 221 * 222 * CH0 -- Touch screen XP/UL 223 * CH1 -- Touch screen XM/UR 224 * CH2 -- Touch screen YP/LL 225 * CH3 -- Touch screen YM/Sense 226 * CH4 -- Touch screen LR(5-wire only) 227 * 228 * The bitfields below represents the reserved channel in the 229 * touchscreen mode. 230 */ 231#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) 232#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) 233 enum atmel_adc_ts_type touchscreen_type; 234 struct input_dev *ts_input; 235 236 u16 ts_sample_period_val; 237 u32 ts_pressure_threshold; 238 u16 ts_pendbc; 239 240 bool ts_bufferedmeasure; 241 u32 ts_prev_absx; 242 u32 ts_prev_absy; 243}; 244 245static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 246{ 247 struct iio_poll_func *pf = p; 248 struct iio_dev *idev = pf->indio_dev; 249 struct at91_adc_state *st = iio_priv(idev); 250 struct iio_chan_spec const *chan; 251 int i, j = 0; 252 253 for (i = 0; i < idev->masklength; i++) { 254 if (!test_bit(i, idev->active_scan_mask)) 255 continue; 256 chan = idev->channels + i; 257 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); 258 j++; 259 } 260 261 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); 262 263 iio_trigger_notify_done(idev->trig); 264 265 /* Needed to ACK the DRDY interruption */ 266 at91_adc_readl(st, AT91_ADC_LCDR); 267 268 enable_irq(st->irq); 269 270 return IRQ_HANDLED; 271} 272 273/* Handler for classic adc channel eoc trigger */ 274static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) 275{ 276 struct at91_adc_state *st = iio_priv(idev); 277 278 if (iio_buffer_enabled(idev)) { 279 disable_irq_nosync(irq); 280 iio_trigger_poll(idev->trig); 281 } else { 282 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); 283 /* Needed to ACK the DRDY interruption */ 284 at91_adc_readl(st, AT91_ADC_LCDR); 285 st->done = true; 286 wake_up_interruptible(&st->wq_data_avail); 287 } 288} 289 290static int at91_ts_sample(struct iio_dev *idev) 291{ 292 struct at91_adc_state *st = iio_priv(idev); 293 unsigned int xscale, yscale, reg, z1, z2; 294 unsigned int x, y, pres, xpos, ypos; 295 unsigned int rxp = 1; 296 unsigned int factor = 1000; 297 298 unsigned int xyz_mask_bits = st->res; 299 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; 300 301 /* calculate position */ 302 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ 303 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); 304 xpos = reg & xyz_mask; 305 x = (xpos << MAX_POS_BITS) - xpos; 306 xscale = (reg >> 16) & xyz_mask; 307 if (xscale == 0) { 308 dev_err(&idev->dev, "Error: xscale == 0!\n"); 309 return -1; 310 } 311 x /= xscale; 312 313 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ 314 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); 315 ypos = reg & xyz_mask; 316 y = (ypos << MAX_POS_BITS) - ypos; 317 yscale = (reg >> 16) & xyz_mask; 318 if (yscale == 0) { 319 dev_err(&idev->dev, "Error: yscale == 0!\n"); 320 return -1; 321 } 322 y /= yscale; 323 324 /* calculate the pressure */ 325 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); 326 z1 = reg & xyz_mask; 327 z2 = (reg >> 16) & xyz_mask; 328 329 if (z1 != 0) 330 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) 331 / factor; 332 else 333 pres = st->ts_pressure_threshold; /* no pen contacted */ 334 335 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", 336 xpos, xscale, ypos, yscale, z1, z2, pres); 337 338 if (pres < st->ts_pressure_threshold) { 339 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", 340 x, y, pres / factor); 341 input_report_abs(st->ts_input, ABS_X, x); 342 input_report_abs(st->ts_input, ABS_Y, y); 343 input_report_abs(st->ts_input, ABS_PRESSURE, pres); 344 input_report_key(st->ts_input, BTN_TOUCH, 1); 345 input_sync(st->ts_input); 346 } else { 347 dev_dbg(&idev->dev, "pressure too low: not reporting\n"); 348 } 349 350 return 0; 351} 352 353static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) 354{ 355 struct iio_dev *idev = private; 356 struct at91_adc_state *st = iio_priv(idev); 357 u32 status = at91_adc_readl(st, st->registers->status_register); 358 unsigned int reg; 359 360 status &= at91_adc_readl(st, AT91_ADC_IMR); 361 if (status & GENMASK(st->num_channels - 1, 0)) 362 handle_adc_eoc_trigger(irq, idev); 363 364 if (status & AT91RL_ADC_IER_PEN) { 365 /* Disabling pen debounce is required to get a NOPEN irq */ 366 reg = at91_adc_readl(st, AT91_ADC_MR); 367 reg &= ~AT91_ADC_PENDBC; 368 at91_adc_writel(st, AT91_ADC_MR, reg); 369 370 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 371 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN 372 | AT91_ADC_EOC(3)); 373 /* Set up period trigger for sampling */ 374 at91_adc_writel(st, st->registers->trigger_register, 375 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 376 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 377 } else if (status & AT91RL_ADC_IER_NOPEN) { 378 reg = at91_adc_readl(st, AT91_ADC_MR); 379 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 380 at91_adc_writel(st, AT91_ADC_MR, reg); 381 at91_adc_writel(st, st->registers->trigger_register, 382 AT91_ADC_TRGR_NONE); 383 384 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN 385 | AT91_ADC_EOC(3)); 386 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 387 st->ts_bufferedmeasure = false; 388 input_report_key(st->ts_input, BTN_TOUCH, 0); 389 input_sync(st->ts_input); 390 } else if (status & AT91_ADC_EOC(3) && st->ts_input) { 391 /* Conversion finished and we've a touchscreen */ 392 if (st->ts_bufferedmeasure) { 393 /* 394 * Last measurement is always discarded, since it can 395 * be erroneous. 396 * Always report previous measurement 397 */ 398 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); 399 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); 400 input_report_key(st->ts_input, BTN_TOUCH, 1); 401 input_sync(st->ts_input); 402 } else 403 st->ts_bufferedmeasure = true; 404 405 /* Now make new measurement */ 406 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) 407 << MAX_RLPOS_BITS; 408 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); 409 410 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) 411 << MAX_RLPOS_BITS; 412 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); 413 } 414 415 return IRQ_HANDLED; 416} 417 418static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) 419{ 420 struct iio_dev *idev = private; 421 struct at91_adc_state *st = iio_priv(idev); 422 u32 status = at91_adc_readl(st, st->registers->status_register); 423 const uint32_t ts_data_irq_mask = 424 AT91_ADC_IER_XRDY | 425 AT91_ADC_IER_YRDY | 426 AT91_ADC_IER_PRDY; 427 428 if (status & GENMASK(st->num_channels - 1, 0)) 429 handle_adc_eoc_trigger(irq, idev); 430 431 if (status & AT91_ADC_IER_PEN) { 432 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 433 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | 434 ts_data_irq_mask); 435 /* Set up period trigger for sampling */ 436 at91_adc_writel(st, st->registers->trigger_register, 437 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 438 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 439 } else if (status & AT91_ADC_IER_NOPEN) { 440 at91_adc_writel(st, st->registers->trigger_register, 0); 441 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | 442 ts_data_irq_mask); 443 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 444 445 input_report_key(st->ts_input, BTN_TOUCH, 0); 446 input_sync(st->ts_input); 447 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { 448 /* Now all touchscreen data is ready */ 449 450 if (status & AT91_ADC_ISR_PENS) { 451 /* validate data by pen contact */ 452 at91_ts_sample(idev); 453 } else { 454 /* triggered by event that is no pen contact, just read 455 * them to clean the interrupt and discard all. 456 */ 457 at91_adc_readl(st, AT91_ADC_TSXPOSR); 458 at91_adc_readl(st, AT91_ADC_TSYPOSR); 459 at91_adc_readl(st, AT91_ADC_TSPRESSR); 460 } 461 } 462 463 return IRQ_HANDLED; 464} 465 466static int at91_adc_channel_init(struct iio_dev *idev) 467{ 468 struct at91_adc_state *st = iio_priv(idev); 469 struct iio_chan_spec *chan_array, *timestamp; 470 int bit, idx = 0; 471 unsigned long rsvd_mask = 0; 472 473 /* If touchscreen is enable, then reserve the adc channels */ 474 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 475 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; 476 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) 477 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; 478 479 /* set up the channel mask to reserve touchscreen channels */ 480 st->channels_mask &= ~rsvd_mask; 481 482 idev->num_channels = bitmap_weight(&st->channels_mask, 483 st->num_channels) + 1; 484 485 chan_array = devm_kzalloc(&idev->dev, 486 ((idev->num_channels + 1) * 487 sizeof(struct iio_chan_spec)), 488 GFP_KERNEL); 489 490 if (!chan_array) 491 return -ENOMEM; 492 493 for_each_set_bit(bit, &st->channels_mask, st->num_channels) { 494 struct iio_chan_spec *chan = chan_array + idx; 495 496 chan->type = IIO_VOLTAGE; 497 chan->indexed = 1; 498 chan->channel = bit; 499 chan->scan_index = idx; 500 chan->scan_type.sign = 'u'; 501 chan->scan_type.realbits = st->res; 502 chan->scan_type.storagebits = 16; 503 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 504 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 505 idx++; 506 } 507 timestamp = chan_array + idx; 508 509 timestamp->type = IIO_TIMESTAMP; 510 timestamp->channel = -1; 511 timestamp->scan_index = idx; 512 timestamp->scan_type.sign = 's'; 513 timestamp->scan_type.realbits = 64; 514 timestamp->scan_type.storagebits = 64; 515 516 idev->channels = chan_array; 517 return idev->num_channels; 518} 519 520static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, 521 struct at91_adc_trigger *triggers, 522 const char *trigger_name) 523{ 524 struct at91_adc_state *st = iio_priv(idev); 525 int i; 526 527 for (i = 0; i < st->trigger_number; i++) { 528 char *name = kasprintf(GFP_KERNEL, 529 "%s-dev%d-%s", 530 idev->name, 531 idev->id, 532 triggers[i].name); 533 if (!name) 534 return -ENOMEM; 535 536 if (strcmp(trigger_name, name) == 0) { 537 kfree(name); 538 if (triggers[i].value == 0) 539 return -EINVAL; 540 return triggers[i].value; 541 } 542 543 kfree(name); 544 } 545 546 return -EINVAL; 547} 548 549static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 550{ 551 struct iio_dev *idev = iio_trigger_get_drvdata(trig); 552 struct at91_adc_state *st = iio_priv(idev); 553 struct at91_adc_reg_desc *reg = st->registers; 554 u32 status = at91_adc_readl(st, reg->trigger_register); 555 int value; 556 u8 bit; 557 558 value = at91_adc_get_trigger_value_by_name(idev, 559 st->trigger_list, 560 idev->trig->name); 561 if (value < 0) 562 return value; 563 564 if (state) { 565 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); 566 if (st->buffer == NULL) 567 return -ENOMEM; 568 569 at91_adc_writel(st, reg->trigger_register, 570 status | value); 571 572 for_each_set_bit(bit, idev->active_scan_mask, 573 st->num_channels) { 574 struct iio_chan_spec const *chan = idev->channels + bit; 575 at91_adc_writel(st, AT91_ADC_CHER, 576 AT91_ADC_CH(chan->channel)); 577 } 578 579 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); 580 581 } else { 582 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); 583 584 at91_adc_writel(st, reg->trigger_register, 585 status & ~value); 586 587 for_each_set_bit(bit, idev->active_scan_mask, 588 st->num_channels) { 589 struct iio_chan_spec const *chan = idev->channels + bit; 590 at91_adc_writel(st, AT91_ADC_CHDR, 591 AT91_ADC_CH(chan->channel)); 592 } 593 kfree(st->buffer); 594 } 595 596 return 0; 597} 598 599static const struct iio_trigger_ops at91_adc_trigger_ops = { 600 .set_trigger_state = &at91_adc_configure_trigger, 601}; 602 603static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, 604 struct at91_adc_trigger *trigger) 605{ 606 struct iio_trigger *trig; 607 int ret; 608 609 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, 610 idev->id, trigger->name); 611 if (trig == NULL) 612 return NULL; 613 614 trig->dev.parent = idev->dev.parent; 615 iio_trigger_set_drvdata(trig, idev); 616 trig->ops = &at91_adc_trigger_ops; 617 618 ret = iio_trigger_register(trig); 619 if (ret) { 620 iio_trigger_free(trig); 621 return NULL; 622 } 623 624 return trig; 625} 626 627static int at91_adc_trigger_init(struct iio_dev *idev) 628{ 629 struct at91_adc_state *st = iio_priv(idev); 630 int i, ret; 631 632 st->trig = devm_kcalloc(&idev->dev, 633 st->trigger_number, sizeof(*st->trig), 634 GFP_KERNEL); 635 636 if (st->trig == NULL) { 637 ret = -ENOMEM; 638 goto error_ret; 639 } 640 641 for (i = 0; i < st->trigger_number; i++) { 642 if (st->trigger_list[i].is_external && !(st->use_external)) 643 continue; 644 645 st->trig[i] = at91_adc_allocate_trigger(idev, 646 st->trigger_list + i); 647 if (st->trig[i] == NULL) { 648 dev_err(&idev->dev, 649 "Could not allocate trigger %d\n", i); 650 ret = -ENOMEM; 651 goto error_trigger; 652 } 653 } 654 655 return 0; 656 657error_trigger: 658 for (i--; i >= 0; i--) { 659 iio_trigger_unregister(st->trig[i]); 660 iio_trigger_free(st->trig[i]); 661 } 662error_ret: 663 return ret; 664} 665 666static void at91_adc_trigger_remove(struct iio_dev *idev) 667{ 668 struct at91_adc_state *st = iio_priv(idev); 669 int i; 670 671 for (i = 0; i < st->trigger_number; i++) { 672 iio_trigger_unregister(st->trig[i]); 673 iio_trigger_free(st->trig[i]); 674 } 675} 676 677static int at91_adc_buffer_init(struct iio_dev *idev) 678{ 679 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, 680 &at91_adc_trigger_handler, NULL); 681} 682 683static void at91_adc_buffer_remove(struct iio_dev *idev) 684{ 685 iio_triggered_buffer_cleanup(idev); 686} 687 688static int at91_adc_read_raw(struct iio_dev *idev, 689 struct iio_chan_spec const *chan, 690 int *val, int *val2, long mask) 691{ 692 struct at91_adc_state *st = iio_priv(idev); 693 int ret; 694 695 switch (mask) { 696 case IIO_CHAN_INFO_RAW: 697 mutex_lock(&st->lock); 698 699 st->chnb = chan->channel; 700 at91_adc_writel(st, AT91_ADC_CHER, 701 AT91_ADC_CH(chan->channel)); 702 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); 703 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); 704 705 ret = wait_event_interruptible_timeout(st->wq_data_avail, 706 st->done, 707 msecs_to_jiffies(1000)); 708 709 /* Disable interrupts, regardless if adc conversion was 710 * successful or not 711 */ 712 at91_adc_writel(st, AT91_ADC_CHDR, 713 AT91_ADC_CH(chan->channel)); 714 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); 715 716 if (ret > 0) { 717 /* a valid conversion took place */ 718 *val = st->last_value; 719 st->last_value = 0; 720 st->done = false; 721 ret = IIO_VAL_INT; 722 } else if (ret == 0) { 723 /* conversion timeout */ 724 dev_err(&idev->dev, "ADC Channel %d timeout.\n", 725 chan->channel); 726 ret = -ETIMEDOUT; 727 } 728 729 mutex_unlock(&st->lock); 730 return ret; 731 732 case IIO_CHAN_INFO_SCALE: 733 *val = st->vref_mv; 734 *val2 = chan->scan_type.realbits; 735 return IIO_VAL_FRACTIONAL_LOG2; 736 default: 737 break; 738 } 739 return -EINVAL; 740} 741 742static int at91_adc_of_get_resolution(struct iio_dev *idev, 743 struct platform_device *pdev) 744{ 745 struct at91_adc_state *st = iio_priv(idev); 746 struct device_node *np = pdev->dev.of_node; 747 int count, i, ret = 0; 748 char *res_name, *s; 749 u32 *resolutions; 750 751 count = of_property_count_strings(np, "atmel,adc-res-names"); 752 if (count < 2) { 753 dev_err(&idev->dev, "You must specified at least two resolution names for " 754 "adc-res-names property in the DT\n"); 755 return count; 756 } 757 758 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL); 759 if (!resolutions) 760 return -ENOMEM; 761 762 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { 763 dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); 764 ret = -ENODEV; 765 goto ret; 766 } 767 768 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) 769 res_name = "highres"; 770 771 for (i = 0; i < count; i++) { 772 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) 773 continue; 774 775 if (strcmp(res_name, s)) 776 continue; 777 778 st->res = resolutions[i]; 779 if (!strcmp(res_name, "lowres")) 780 st->low_res = true; 781 else 782 st->low_res = false; 783 784 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); 785 goto ret; 786 } 787 788 dev_err(&idev->dev, "There is no resolution for %s\n", res_name); 789 790ret: 791 kfree(resolutions); 792 return ret; 793} 794 795static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) 796{ 797 /* 798 * Number of ticks needed to cover the startup time of the ADC 799 * as defined in the electrical characteristics of the board, 800 * divided by 8. The formula thus is : 801 * Startup Time = (ticks + 1) * 8 / ADC Clock 802 */ 803 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; 804} 805 806static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) 807{ 808 /* 809 * For sama5d3x and at91sam9x5, the formula changes to: 810 * Startup Time = <lookup_table_value> / ADC Clock 811 */ 812 static const int startup_lookup[] = { 813 0, 8, 16, 24, 814 64, 80, 96, 112, 815 512, 576, 640, 704, 816 768, 832, 896, 960 817 }; 818 int i, size = ARRAY_SIZE(startup_lookup); 819 unsigned int ticks; 820 821 ticks = startup_time * adc_clk_khz / 1000; 822 for (i = 0; i < size; i++) 823 if (ticks < startup_lookup[i]) 824 break; 825 826 ticks = i; 827 if (ticks == size) 828 /* Reach the end of lookup table */ 829 ticks = size - 1; 830 831 return ticks; 832} 833 834static const struct of_device_id at91_adc_dt_ids[]; 835 836static int at91_adc_probe_dt_ts(struct device_node *node, 837 struct at91_adc_state *st, struct device *dev) 838{ 839 int ret; 840 u32 prop; 841 842 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); 843 if (ret) { 844 dev_info(dev, "ADC Touch screen is disabled.\n"); 845 return 0; 846 } 847 848 switch (prop) { 849 case 4: 850 case 5: 851 st->touchscreen_type = prop; 852 break; 853 default: 854 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); 855 return -EINVAL; 856 } 857 858 if (!st->caps->has_tsmr) 859 return 0; 860 prop = 0; 861 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); 862 st->ts_pressure_threshold = prop; 863 if (st->ts_pressure_threshold) { 864 return 0; 865 } else { 866 dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); 867 return -EINVAL; 868 } 869} 870 871static int at91_adc_probe_dt(struct iio_dev *idev, 872 struct platform_device *pdev) 873{ 874 struct at91_adc_state *st = iio_priv(idev); 875 struct device_node *node = pdev->dev.of_node; 876 struct device_node *trig_node; 877 int i = 0, ret; 878 u32 prop; 879 880 if (!node) 881 return -EINVAL; 882 883 st->caps = (struct at91_adc_caps *) 884 of_match_device(at91_adc_dt_ids, &pdev->dev)->data; 885 886 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); 887 888 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { 889 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); 890 ret = -EINVAL; 891 goto error_ret; 892 } 893 st->channels_mask = prop; 894 895 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); 896 897 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { 898 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); 899 ret = -EINVAL; 900 goto error_ret; 901 } 902 st->startup_time = prop; 903 904 prop = 0; 905 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); 906 st->sample_hold_time = prop; 907 908 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { 909 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); 910 ret = -EINVAL; 911 goto error_ret; 912 } 913 st->vref_mv = prop; 914 915 ret = at91_adc_of_get_resolution(idev, pdev); 916 if (ret) 917 goto error_ret; 918 919 st->registers = &st->caps->registers; 920 st->num_channels = st->caps->num_channels; 921 st->trigger_number = of_get_child_count(node); 922 st->trigger_list = devm_kcalloc(&idev->dev, 923 st->trigger_number, 924 sizeof(struct at91_adc_trigger), 925 GFP_KERNEL); 926 if (!st->trigger_list) { 927 dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); 928 ret = -ENOMEM; 929 goto error_ret; 930 } 931 932 for_each_child_of_node(node, trig_node) { 933 struct at91_adc_trigger *trig = st->trigger_list + i; 934 const char *name; 935 936 if (of_property_read_string(trig_node, "trigger-name", &name)) { 937 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); 938 ret = -EINVAL; 939 goto error_ret; 940 } 941 trig->name = name; 942 943 if (of_property_read_u32(trig_node, "trigger-value", &prop)) { 944 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); 945 ret = -EINVAL; 946 goto error_ret; 947 } 948 trig->value = prop; 949 trig->is_external = of_property_read_bool(trig_node, "trigger-external"); 950 i++; 951 } 952 953 /* Check if touchscreen is supported. */ 954 if (st->caps->has_ts) 955 return at91_adc_probe_dt_ts(node, st, &idev->dev); 956 else 957 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n"); 958 959 return 0; 960 961error_ret: 962 return ret; 963} 964 965static int at91_adc_probe_pdata(struct at91_adc_state *st, 966 struct platform_device *pdev) 967{ 968 struct at91_adc_data *pdata = pdev->dev.platform_data; 969 970 if (!pdata) 971 return -EINVAL; 972 973 st->caps = (struct at91_adc_caps *) 974 platform_get_device_id(pdev)->driver_data; 975 976 st->use_external = pdata->use_external_triggers; 977 st->vref_mv = pdata->vref; 978 st->channels_mask = pdata->channels_used; 979 st->num_channels = st->caps->num_channels; 980 st->startup_time = pdata->startup_time; 981 st->trigger_number = pdata->trigger_number; 982 st->trigger_list = pdata->trigger_list; 983 st->registers = &st->caps->registers; 984 st->touchscreen_type = pdata->touchscreen_type; 985 986 return 0; 987} 988 989static const struct iio_info at91_adc_info = { 990 .read_raw = &at91_adc_read_raw, 991}; 992 993/* Touchscreen related functions */ 994static int atmel_ts_open(struct input_dev *dev) 995{ 996 struct at91_adc_state *st = input_get_drvdata(dev); 997 998 if (st->caps->has_tsmr) 999 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 1000 else 1001 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 1002 return 0; 1003} 1004 1005static void atmel_ts_close(struct input_dev *dev) 1006{ 1007 struct at91_adc_state *st = input_get_drvdata(dev); 1008 1009 if (st->caps->has_tsmr) 1010 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 1011 else 1012 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 1013} 1014 1015static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz) 1016{ 1017 struct at91_adc_state *st = iio_priv(idev); 1018 u32 reg = 0; 1019 u32 tssctim = 0; 1020 int i = 0; 1021 1022 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid 1023 * pen detect noise. 1024 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock 1025 */ 1026 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / 1027 1000, 1); 1028 1029 while (st->ts_pendbc >> ++i) 1030 ; /* Empty! Find the shift offset */ 1031 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) 1032 st->ts_pendbc = i; 1033 else 1034 st->ts_pendbc = i - 1; 1035 1036 if (!st->caps->has_tsmr) { 1037 reg = at91_adc_readl(st, AT91_ADC_MR); 1038 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; 1039 1040 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 1041 at91_adc_writel(st, AT91_ADC_MR, reg); 1042 1043 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; 1044 at91_adc_writel(st, AT91_ADC_TSR, reg); 1045 1046 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * 1047 adc_clk_khz / 1000) - 1, 1); 1048 1049 return 0; 1050 } 1051 1052 /* Touchscreen Switches Closure time needed for allowing the value to 1053 * stabilize. 1054 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods 1055 */ 1056 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4); 1057 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n", 1058 adc_clk_khz, tssctim); 1059 1060 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 1061 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; 1062 else 1063 reg = AT91_ADC_TSMR_TSMODE_5WIRE; 1064 1065 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; 1066 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) 1067 & AT91_ADC_TSMR_TSAV; 1068 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; 1069 reg |= AT91_ADC_TSMR_NOTSDMA; 1070 reg |= AT91_ADC_TSMR_PENDET_ENA; 1071 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ 1072 1073 at91_adc_writel(st, AT91_ADC_TSMR, reg); 1074 1075 /* Change adc internal resistor value for better pen detection, 1076 * default value is 100 kOhm. 1077 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm 1078 * option only available on ES2 and higher 1079 */ 1080 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity 1081 & AT91_ADC_ACR_PENDETSENS); 1082 1083 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 1084 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * 1085 adc_clk_khz / 1000) - 1, 1); 1086 1087 return 0; 1088} 1089 1090static int at91_ts_register(struct iio_dev *idev, 1091 struct platform_device *pdev) 1092{ 1093 struct at91_adc_state *st = iio_priv(idev); 1094 struct input_dev *input; 1095 int ret; 1096 1097 input = input_allocate_device(); 1098 if (!input) { 1099 dev_err(&idev->dev, "Failed to allocate TS device!\n"); 1100 return -ENOMEM; 1101 } 1102 1103 input->name = DRIVER_NAME; 1104 input->id.bustype = BUS_HOST; 1105 input->dev.parent = &pdev->dev; 1106 input->open = atmel_ts_open; 1107 input->close = atmel_ts_close; 1108 1109 __set_bit(EV_ABS, input->evbit); 1110 __set_bit(EV_KEY, input->evbit); 1111 __set_bit(BTN_TOUCH, input->keybit); 1112 if (st->caps->has_tsmr) { 1113 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, 1114 0, 0); 1115 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, 1116 0, 0); 1117 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); 1118 } else { 1119 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { 1120 dev_err(&pdev->dev, 1121 "This touchscreen controller only support 4 wires\n"); 1122 ret = -EINVAL; 1123 goto err; 1124 } 1125 1126 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, 1127 0, 0); 1128 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, 1129 0, 0); 1130 } 1131 1132 st->ts_input = input; 1133 input_set_drvdata(input, st); 1134 1135 ret = input_register_device(input); 1136 if (ret) 1137 goto err; 1138 1139 return ret; 1140 1141err: 1142 input_free_device(st->ts_input); 1143 return ret; 1144} 1145 1146static void at91_ts_unregister(struct at91_adc_state *st) 1147{ 1148 input_unregister_device(st->ts_input); 1149} 1150 1151static int at91_adc_probe(struct platform_device *pdev) 1152{ 1153 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; 1154 int ret; 1155 struct iio_dev *idev; 1156 struct at91_adc_state *st; 1157 u32 reg; 1158 1159 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); 1160 if (!idev) 1161 return -ENOMEM; 1162 1163 st = iio_priv(idev); 1164 1165 if (pdev->dev.of_node) 1166 ret = at91_adc_probe_dt(idev, pdev); 1167 else 1168 ret = at91_adc_probe_pdata(st, pdev); 1169 1170 if (ret) { 1171 dev_err(&pdev->dev, "No platform data available.\n"); 1172 return -EINVAL; 1173 } 1174 1175 platform_set_drvdata(pdev, idev); 1176 1177 idev->name = dev_name(&pdev->dev); 1178 idev->modes = INDIO_DIRECT_MODE; 1179 idev->info = &at91_adc_info; 1180 1181 st->irq = platform_get_irq(pdev, 0); 1182 if (st->irq < 0) 1183 return -ENODEV; 1184 1185 st->reg_base = devm_platform_ioremap_resource(pdev, 0); 1186 if (IS_ERR(st->reg_base)) 1187 return PTR_ERR(st->reg_base); 1188 1189 1190 /* 1191 * Disable all IRQs before setting up the handler 1192 */ 1193 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); 1194 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); 1195 1196 if (st->caps->has_tsmr) 1197 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, 1198 pdev->dev.driver->name, idev); 1199 else 1200 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, 1201 pdev->dev.driver->name, idev); 1202 if (ret) { 1203 dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); 1204 return ret; 1205 } 1206 1207 st->clk = devm_clk_get(&pdev->dev, "adc_clk"); 1208 if (IS_ERR(st->clk)) { 1209 dev_err(&pdev->dev, "Failed to get the clock.\n"); 1210 ret = PTR_ERR(st->clk); 1211 goto error_free_irq; 1212 } 1213 1214 ret = clk_prepare_enable(st->clk); 1215 if (ret) { 1216 dev_err(&pdev->dev, 1217 "Could not prepare or enable the clock.\n"); 1218 goto error_free_irq; 1219 } 1220 1221 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); 1222 if (IS_ERR(st->adc_clk)) { 1223 dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); 1224 ret = PTR_ERR(st->adc_clk); 1225 goto error_disable_clk; 1226 } 1227 1228 ret = clk_prepare_enable(st->adc_clk); 1229 if (ret) { 1230 dev_err(&pdev->dev, 1231 "Could not prepare or enable the ADC clock.\n"); 1232 goto error_disable_clk; 1233 } 1234 1235 /* 1236 * Prescaler rate computation using the formula from the Atmel's 1237 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being 1238 * specified by the electrical characteristics of the board. 1239 */ 1240 mstrclk = clk_get_rate(st->clk); 1241 adc_clk = clk_get_rate(st->adc_clk); 1242 adc_clk_khz = adc_clk / 1000; 1243 1244 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", 1245 mstrclk, adc_clk); 1246 1247 prsc = (mstrclk / (2 * adc_clk)) - 1; 1248 1249 if (!st->startup_time) { 1250 dev_err(&pdev->dev, "No startup time available.\n"); 1251 ret = -EINVAL; 1252 goto error_disable_adc_clk; 1253 } 1254 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); 1255 1256 /* 1257 * a minimal Sample and Hold Time is necessary for the ADC to guarantee 1258 * the best converted final value between two channels selection 1259 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock 1260 */ 1261 if (st->sample_hold_time > 0) 1262 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) 1263 - 1, 1); 1264 else 1265 shtim = 0; 1266 1267 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; 1268 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; 1269 if (st->low_res) 1270 reg |= AT91_ADC_LOWRES; 1271 if (st->sleep_mode) 1272 reg |= AT91_ADC_SLEEP; 1273 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; 1274 at91_adc_writel(st, AT91_ADC_MR, reg); 1275 1276 /* Setup the ADC channels available on the board */ 1277 ret = at91_adc_channel_init(idev); 1278 if (ret < 0) { 1279 dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); 1280 goto error_disable_adc_clk; 1281 } 1282 1283 init_waitqueue_head(&st->wq_data_avail); 1284 mutex_init(&st->lock); 1285 1286 /* 1287 * Since touch screen will set trigger register as period trigger. So 1288 * when touch screen is enabled, then we have to disable hardware 1289 * trigger for classic adc. 1290 */ 1291 if (!st->touchscreen_type) { 1292 ret = at91_adc_buffer_init(idev); 1293 if (ret < 0) { 1294 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); 1295 goto error_disable_adc_clk; 1296 } 1297 1298 ret = at91_adc_trigger_init(idev); 1299 if (ret < 0) { 1300 dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); 1301 at91_adc_buffer_remove(idev); 1302 goto error_disable_adc_clk; 1303 } 1304 } else { 1305 ret = at91_ts_register(idev, pdev); 1306 if (ret) 1307 goto error_disable_adc_clk; 1308 1309 at91_ts_hw_init(idev, adc_clk_khz); 1310 } 1311 1312 ret = iio_device_register(idev); 1313 if (ret < 0) { 1314 dev_err(&pdev->dev, "Couldn't register the device.\n"); 1315 goto error_iio_device_register; 1316 } 1317 1318 return 0; 1319 1320error_iio_device_register: 1321 if (!st->touchscreen_type) { 1322 at91_adc_trigger_remove(idev); 1323 at91_adc_buffer_remove(idev); 1324 } else { 1325 at91_ts_unregister(st); 1326 } 1327error_disable_adc_clk: 1328 clk_disable_unprepare(st->adc_clk); 1329error_disable_clk: 1330 clk_disable_unprepare(st->clk); 1331error_free_irq: 1332 free_irq(st->irq, idev); 1333 return ret; 1334} 1335 1336static int at91_adc_remove(struct platform_device *pdev) 1337{ 1338 struct iio_dev *idev = platform_get_drvdata(pdev); 1339 struct at91_adc_state *st = iio_priv(idev); 1340 1341 iio_device_unregister(idev); 1342 if (!st->touchscreen_type) { 1343 at91_adc_trigger_remove(idev); 1344 at91_adc_buffer_remove(idev); 1345 } else { 1346 at91_ts_unregister(st); 1347 } 1348 clk_disable_unprepare(st->adc_clk); 1349 clk_disable_unprepare(st->clk); 1350 free_irq(st->irq, idev); 1351 1352 return 0; 1353} 1354 1355#ifdef CONFIG_PM_SLEEP 1356static int at91_adc_suspend(struct device *dev) 1357{ 1358 struct iio_dev *idev = dev_get_drvdata(dev); 1359 struct at91_adc_state *st = iio_priv(idev); 1360 1361 pinctrl_pm_select_sleep_state(dev); 1362 clk_disable_unprepare(st->clk); 1363 1364 return 0; 1365} 1366 1367static int at91_adc_resume(struct device *dev) 1368{ 1369 struct iio_dev *idev = dev_get_drvdata(dev); 1370 struct at91_adc_state *st = iio_priv(idev); 1371 1372 clk_prepare_enable(st->clk); 1373 pinctrl_pm_select_default_state(dev); 1374 1375 return 0; 1376} 1377#endif 1378 1379static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); 1380 1381static struct at91_adc_caps at91sam9260_caps = { 1382 .calc_startup_ticks = calc_startup_ticks_9260, 1383 .num_channels = 4, 1384 .registers = { 1385 .channel_base = AT91_ADC_CHR(0), 1386 .drdy_mask = AT91_ADC_DRDY, 1387 .status_register = AT91_ADC_SR, 1388 .trigger_register = AT91_ADC_TRGR_9260, 1389 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1390 .mr_startup_mask = AT91_ADC_STARTUP_9260, 1391 }, 1392}; 1393 1394static struct at91_adc_caps at91sam9rl_caps = { 1395 .has_ts = true, 1396 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1397 .num_channels = 6, 1398 .registers = { 1399 .channel_base = AT91_ADC_CHR(0), 1400 .drdy_mask = AT91_ADC_DRDY, 1401 .status_register = AT91_ADC_SR, 1402 .trigger_register = AT91_ADC_TRGR_9G45, 1403 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1404 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1405 }, 1406}; 1407 1408static struct at91_adc_caps at91sam9g45_caps = { 1409 .has_ts = true, 1410 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1411 .num_channels = 8, 1412 .registers = { 1413 .channel_base = AT91_ADC_CHR(0), 1414 .drdy_mask = AT91_ADC_DRDY, 1415 .status_register = AT91_ADC_SR, 1416 .trigger_register = AT91_ADC_TRGR_9G45, 1417 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1418 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1419 }, 1420}; 1421 1422static struct at91_adc_caps at91sam9x5_caps = { 1423 .has_ts = true, 1424 .has_tsmr = true, 1425 .ts_filter_average = 3, 1426 .ts_pen_detect_sensitivity = 2, 1427 .calc_startup_ticks = calc_startup_ticks_9x5, 1428 .num_channels = 12, 1429 .registers = { 1430 .channel_base = AT91_ADC_CDR0_9X5, 1431 .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1432 .status_register = AT91_ADC_SR_9X5, 1433 .trigger_register = AT91_ADC_TRGR_9X5, 1434 /* prescal mask is same as 9G45 */ 1435 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1436 .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1437 }, 1438}; 1439 1440static const struct of_device_id at91_adc_dt_ids[] = { 1441 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, 1442 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, 1443 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, 1444 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, 1445 {}, 1446}; 1447MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); 1448 1449static const struct platform_device_id at91_adc_ids[] = { 1450 { 1451 .name = "at91sam9260-adc", 1452 .driver_data = (unsigned long)&at91sam9260_caps, 1453 }, { 1454 .name = "at91sam9rl-adc", 1455 .driver_data = (unsigned long)&at91sam9rl_caps, 1456 }, { 1457 .name = "at91sam9g45-adc", 1458 .driver_data = (unsigned long)&at91sam9g45_caps, 1459 }, { 1460 .name = "at91sam9x5-adc", 1461 .driver_data = (unsigned long)&at91sam9x5_caps, 1462 }, { 1463 /* terminator */ 1464 } 1465}; 1466MODULE_DEVICE_TABLE(platform, at91_adc_ids); 1467 1468static struct platform_driver at91_adc_driver = { 1469 .probe = at91_adc_probe, 1470 .remove = at91_adc_remove, 1471 .id_table = at91_adc_ids, 1472 .driver = { 1473 .name = DRIVER_NAME, 1474 .of_match_table = at91_adc_dt_ids, 1475 .pm = &at91_adc_pm_ops, 1476 }, 1477}; 1478 1479module_platform_driver(at91_adc_driver); 1480 1481MODULE_LICENSE("GPL"); 1482MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); 1483MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1484