1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Atmel ADC driver for SAMA5D2 devices and compatible. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <linux/bitops.h> 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/dma-mapping.h> 13#include <linux/dmaengine.h> 14#include <linux/interrupt.h> 15#include <linux/io.h> 16#include <linux/module.h> 17#include <linux/of_device.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/wait.h> 21#include <linux/iio/iio.h> 22#include <linux/iio/sysfs.h> 23#include <linux/iio/buffer.h> 24#include <linux/iio/trigger.h> 25#include <linux/iio/trigger_consumer.h> 26#include <linux/iio/triggered_buffer.h> 27#include <linux/pinctrl/consumer.h> 28#include <linux/regulator/consumer.h> 29 30/* Control Register */ 31#define AT91_SAMA5D2_CR 0x00 32/* Software Reset */ 33#define AT91_SAMA5D2_CR_SWRST BIT(0) 34/* Start Conversion */ 35#define AT91_SAMA5D2_CR_START BIT(1) 36/* Touchscreen Calibration */ 37#define AT91_SAMA5D2_CR_TSCALIB BIT(2) 38/* Comparison Restart */ 39#define AT91_SAMA5D2_CR_CMPRST BIT(4) 40 41/* Mode Register */ 42#define AT91_SAMA5D2_MR 0x04 43/* Trigger Selection */ 44#define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 45/* ADTRG */ 46#define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 47/* TIOA0 */ 48#define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 49/* TIOA1 */ 50#define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 51/* TIOA2 */ 52#define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 53/* PWM event line 0 */ 54#define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 55/* PWM event line 1 */ 56#define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 57/* TIOA3 */ 58#define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 59/* RTCOUT0 */ 60#define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 61/* Sleep Mode */ 62#define AT91_SAMA5D2_MR_SLEEP BIT(5) 63/* Fast Wake Up */ 64#define AT91_SAMA5D2_MR_FWUP BIT(6) 65/* Prescaler Rate Selection */ 66#define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 67#define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 68#define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 69#define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8) 70/* Startup Time */ 71#define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 72#define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) 73/* Analog Change */ 74#define AT91_SAMA5D2_MR_ANACH BIT(23) 75/* Tracking Time */ 76#define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 77#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf 78/* Transfer Time */ 79#define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 80#define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 81/* Use Sequence Enable */ 82#define AT91_SAMA5D2_MR_USEQ BIT(31) 83 84/* Channel Sequence Register 1 */ 85#define AT91_SAMA5D2_SEQR1 0x08 86/* Channel Sequence Register 2 */ 87#define AT91_SAMA5D2_SEQR2 0x0c 88/* Channel Enable Register */ 89#define AT91_SAMA5D2_CHER 0x10 90/* Channel Disable Register */ 91#define AT91_SAMA5D2_CHDR 0x14 92/* Channel Status Register */ 93#define AT91_SAMA5D2_CHSR 0x18 94/* Last Converted Data Register */ 95#define AT91_SAMA5D2_LCDR 0x20 96/* Interrupt Enable Register */ 97#define AT91_SAMA5D2_IER 0x24 98/* Interrupt Enable Register - TS X measurement ready */ 99#define AT91_SAMA5D2_IER_XRDY BIT(20) 100/* Interrupt Enable Register - TS Y measurement ready */ 101#define AT91_SAMA5D2_IER_YRDY BIT(21) 102/* Interrupt Enable Register - TS pressure measurement ready */ 103#define AT91_SAMA5D2_IER_PRDY BIT(22) 104/* Interrupt Enable Register - Data ready */ 105#define AT91_SAMA5D2_IER_DRDY BIT(24) 106/* Interrupt Enable Register - general overrun error */ 107#define AT91_SAMA5D2_IER_GOVRE BIT(25) 108/* Interrupt Enable Register - Pen detect */ 109#define AT91_SAMA5D2_IER_PEN BIT(29) 110/* Interrupt Enable Register - No pen detect */ 111#define AT91_SAMA5D2_IER_NOPEN BIT(30) 112/* Interrupt Disable Register */ 113#define AT91_SAMA5D2_IDR 0x28 114/* Interrupt Mask Register */ 115#define AT91_SAMA5D2_IMR 0x2c 116/* Interrupt Status Register */ 117#define AT91_SAMA5D2_ISR 0x30 118/* Interrupt Status Register - Pen touching sense status */ 119#define AT91_SAMA5D2_ISR_PENS BIT(31) 120/* Last Channel Trigger Mode Register */ 121#define AT91_SAMA5D2_LCTMR 0x34 122/* Last Channel Compare Window Register */ 123#define AT91_SAMA5D2_LCCWR 0x38 124/* Overrun Status Register */ 125#define AT91_SAMA5D2_OVER 0x3c 126/* Extended Mode Register */ 127#define AT91_SAMA5D2_EMR 0x40 128/* Extended Mode Register - Oversampling rate */ 129#define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) 130#define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) 131#define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 132#define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 133#define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 134 135/* Extended Mode Register - Averaging on single trigger event */ 136#define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) 137/* Compare Window Register */ 138#define AT91_SAMA5D2_CWR 0x44 139/* Channel Gain Register */ 140#define AT91_SAMA5D2_CGR 0x48 141 142/* Channel Offset Register */ 143#define AT91_SAMA5D2_COR 0x4c 144#define AT91_SAMA5D2_COR_DIFF_OFFSET 16 145 146/* Channel Data Register 0 */ 147#define AT91_SAMA5D2_CDR0 0x50 148/* Analog Control Register */ 149#define AT91_SAMA5D2_ACR 0x94 150/* Analog Control Register - Pen detect sensitivity mask */ 151#define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) 152 153/* Touchscreen Mode Register */ 154#define AT91_SAMA5D2_TSMR 0xb0 155/* Touchscreen Mode Register - No touch mode */ 156#define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 157/* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ 158#define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1 159/* Touchscreen Mode Register - 4 wire screen, pressure measurement */ 160#define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2 161/* Touchscreen Mode Register - 5 wire screen */ 162#define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3 163/* Touchscreen Mode Register - Average samples mask */ 164#define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4) 165/* Touchscreen Mode Register - Average samples */ 166#define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4) 167/* Touchscreen Mode Register - Touch/trigger frequency ratio mask */ 168#define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8) 169/* Touchscreen Mode Register - Touch/trigger frequency ratio */ 170#define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8) 171/* Touchscreen Mode Register - Pen Debounce Time mask */ 172#define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28) 173/* Touchscreen Mode Register - Pen Debounce Time */ 174#define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28) 175/* Touchscreen Mode Register - No DMA for touch measurements */ 176#define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) 177/* Touchscreen Mode Register - Disable pen detection */ 178#define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24) 179/* Touchscreen Mode Register - Enable pen detection */ 180#define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) 181 182/* Touchscreen X Position Register */ 183#define AT91_SAMA5D2_XPOSR 0xb4 184/* Touchscreen Y Position Register */ 185#define AT91_SAMA5D2_YPOSR 0xb8 186/* Touchscreen Pressure Register */ 187#define AT91_SAMA5D2_PRESSR 0xbc 188/* Trigger Register */ 189#define AT91_SAMA5D2_TRGR 0xc0 190/* Mask for TRGMOD field of TRGR register */ 191#define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) 192/* No trigger, only software trigger can start conversions */ 193#define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0 194/* Trigger Mode external trigger rising edge */ 195#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1 196/* Trigger Mode external trigger falling edge */ 197#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2 198/* Trigger Mode external trigger any edge */ 199#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3 200/* Trigger Mode internal periodic */ 201#define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5 202/* Trigger Mode - trigger period mask */ 203#define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16) 204/* Trigger Mode - trigger period */ 205#define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) 206 207/* Correction Select Register */ 208#define AT91_SAMA5D2_COSR 0xd0 209/* Correction Value Register */ 210#define AT91_SAMA5D2_CVR 0xd4 211/* Channel Error Correction Register */ 212#define AT91_SAMA5D2_CECR 0xd8 213/* Write Protection Mode Register */ 214#define AT91_SAMA5D2_WPMR 0xe4 215/* Write Protection Status Register */ 216#define AT91_SAMA5D2_WPSR 0xe8 217/* Version Register */ 218#define AT91_SAMA5D2_VERSION 0xfc 219 220#define AT91_SAMA5D2_HW_TRIG_CNT 3 221#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 222#define AT91_SAMA5D2_DIFF_CHAN_CNT 6 223 224#define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 225 AT91_SAMA5D2_DIFF_CHAN_CNT + 1) 226 227#define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 228 AT91_SAMA5D2_DIFF_CHAN_CNT * 2) 229#define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) 230#define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) 231#define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX 232 233#define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 234#define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 235 236#define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0) 237 238#define AT91_SAMA5D2_MAX_POS_BITS 12 239 240/* 241 * Maximum number of bytes to hold conversion from all channels 242 * without the timestamp. 243 */ 244#define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 245 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) 246 247/* This total must also include the timestamp */ 248#define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) 249 250#define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) 251 252#define AT91_HWFIFO_MAX_SIZE_STR "128" 253#define AT91_HWFIFO_MAX_SIZE 128 254 255/* Possible values for oversampling ratio */ 256#define AT91_OSR_1SAMPLES 1 257#define AT91_OSR_4SAMPLES 4 258#define AT91_OSR_16SAMPLES 16 259 260#define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ 261 { \ 262 .type = IIO_VOLTAGE, \ 263 .channel = num, \ 264 .address = addr, \ 265 .scan_index = num, \ 266 .scan_type = { \ 267 .sign = 'u', \ 268 .realbits = 14, \ 269 .storagebits = 16, \ 270 }, \ 271 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 272 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 273 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 274 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 275 .datasheet_name = "CH"#num, \ 276 .indexed = 1, \ 277 } 278 279#define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ 280 { \ 281 .type = IIO_VOLTAGE, \ 282 .differential = 1, \ 283 .channel = num, \ 284 .channel2 = num2, \ 285 .address = addr, \ 286 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ 287 .scan_type = { \ 288 .sign = 's', \ 289 .realbits = 14, \ 290 .storagebits = 16, \ 291 }, \ 292 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 293 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 294 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 295 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 296 .datasheet_name = "CH"#num"-CH"#num2, \ 297 .indexed = 1, \ 298 } 299 300#define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \ 301 { \ 302 .type = IIO_POSITIONRELATIVE, \ 303 .modified = 1, \ 304 .channel = num, \ 305 .channel2 = mod, \ 306 .scan_index = num, \ 307 .scan_type = { \ 308 .sign = 'u', \ 309 .realbits = 12, \ 310 .storagebits = 16, \ 311 }, \ 312 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 313 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 314 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 315 .datasheet_name = name, \ 316 } 317#define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ 318 { \ 319 .type = IIO_PRESSURE, \ 320 .channel = num, \ 321 .scan_index = num, \ 322 .scan_type = { \ 323 .sign = 'u', \ 324 .realbits = 12, \ 325 .storagebits = 16, \ 326 }, \ 327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 328 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 329 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 330 .datasheet_name = name, \ 331 } 332 333#define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) 334#define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) 335 336struct at91_adc_soc_info { 337 unsigned startup_time; 338 unsigned min_sample_rate; 339 unsigned max_sample_rate; 340}; 341 342struct at91_adc_trigger { 343 char *name; 344 unsigned int trgmod_value; 345 unsigned int edge_type; 346 bool hw_trig; 347}; 348 349/** 350 * struct at91_adc_dma - at91-sama5d2 dma information struct 351 * @dma_chan: the dma channel acquired 352 * @rx_buf: dma coherent allocated area 353 * @rx_dma_buf: dma handler for the buffer 354 * @phys_addr: physical address of the ADC base register 355 * @buf_idx: index inside the dma buffer where reading was last done 356 * @rx_buf_sz: size of buffer used by DMA operation 357 * @watermark: number of conversions to copy before DMA triggers irq 358 * @dma_ts: hold the start timestamp of dma operation 359 */ 360struct at91_adc_dma { 361 struct dma_chan *dma_chan; 362 u8 *rx_buf; 363 dma_addr_t rx_dma_buf; 364 phys_addr_t phys_addr; 365 int buf_idx; 366 int rx_buf_sz; 367 int watermark; 368 s64 dma_ts; 369}; 370 371/** 372 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct 373 * @sample_period_val: the value for periodic trigger interval 374 * @touching: is the pen touching the screen or not 375 * @x_pos: temporary placeholder for pressure computation 376 * @channels_bitmask: bitmask with the touchscreen channels enabled 377 * @workq: workqueue for buffer data pushing 378 */ 379struct at91_adc_touch { 380 u16 sample_period_val; 381 bool touching; 382 u16 x_pos; 383 unsigned long channels_bitmask; 384 struct work_struct workq; 385}; 386 387struct at91_adc_state { 388 void __iomem *base; 389 int irq; 390 struct clk *per_clk; 391 struct regulator *reg; 392 struct regulator *vref; 393 int vref_uv; 394 unsigned int current_sample_rate; 395 struct iio_trigger *trig; 396 const struct at91_adc_trigger *selected_trig; 397 const struct iio_chan_spec *chan; 398 bool conversion_done; 399 u32 conversion_value; 400 unsigned int oversampling_ratio; 401 struct at91_adc_soc_info soc_info; 402 wait_queue_head_t wq_data_available; 403 struct at91_adc_dma dma_st; 404 struct at91_adc_touch touch_st; 405 struct iio_dev *indio_dev; 406 /* Ensure naturally aligned timestamp */ 407 u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8); 408 /* 409 * lock to prevent concurrent 'single conversion' requests through 410 * sysfs. 411 */ 412 struct mutex lock; 413}; 414 415static const struct at91_adc_trigger at91_adc_trigger_list[] = { 416 { 417 .name = "external_rising", 418 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE, 419 .edge_type = IRQ_TYPE_EDGE_RISING, 420 .hw_trig = true, 421 }, 422 { 423 .name = "external_falling", 424 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL, 425 .edge_type = IRQ_TYPE_EDGE_FALLING, 426 .hw_trig = true, 427 }, 428 { 429 .name = "external_any", 430 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY, 431 .edge_type = IRQ_TYPE_EDGE_BOTH, 432 .hw_trig = true, 433 }, 434 { 435 .name = "software", 436 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER, 437 .edge_type = IRQ_TYPE_NONE, 438 .hw_trig = false, 439 }, 440}; 441 442static const struct iio_chan_spec at91_adc_channels[] = { 443 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50), 444 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54), 445 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58), 446 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c), 447 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60), 448 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64), 449 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68), 450 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c), 451 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70), 452 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74), 453 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78), 454 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c), 455 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50), 456 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58), 457 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60), 458 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68), 459 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70), 460 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78), 461 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX), 462 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X), 463 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y), 464 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"), 465}; 466 467static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) 468{ 469 int i; 470 471 for (i = 0; i < indio_dev->num_channels; i++) { 472 if (indio_dev->channels[i].scan_index == chan) 473 return i; 474 } 475 return -EINVAL; 476} 477 478static inline struct iio_chan_spec const * 479at91_adc_chan_get(struct iio_dev *indio_dev, int chan) 480{ 481 int index = at91_adc_chan_xlate(indio_dev, chan); 482 483 if (index < 0) 484 return NULL; 485 return indio_dev->channels + index; 486} 487 488static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, 489 const struct of_phandle_args *iiospec) 490{ 491 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); 492} 493 494static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) 495{ 496 u32 mask = 0; 497 u8 bit; 498 499 for_each_set_bit(bit, indio_dev->active_scan_mask, 500 indio_dev->num_channels) { 501 struct iio_chan_spec const *chan = 502 at91_adc_chan_get(indio_dev, bit); 503 mask |= BIT(chan->channel); 504 } 505 506 return mask & GENMASK(11, 0); 507} 508 509static void at91_adc_config_emr(struct at91_adc_state *st) 510{ 511 /* configure the extended mode register */ 512 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR); 513 514 /* select oversampling per single trigger event */ 515 emr |= AT91_SAMA5D2_EMR_ASTE(1); 516 517 /* delete leftover content if it's the case */ 518 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; 519 520 /* select oversampling ratio from configuration */ 521 switch (st->oversampling_ratio) { 522 case AT91_OSR_1SAMPLES: 523 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & 524 AT91_SAMA5D2_EMR_OSR_MASK; 525 break; 526 case AT91_OSR_4SAMPLES: 527 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & 528 AT91_SAMA5D2_EMR_OSR_MASK; 529 break; 530 case AT91_OSR_16SAMPLES: 531 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & 532 AT91_SAMA5D2_EMR_OSR_MASK; 533 break; 534 } 535 536 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr); 537} 538 539static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) 540{ 541 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) { 542 /* 543 * in this case we only have 12 bits of real data, but channel 544 * is registered as 14 bits, so shift left two bits 545 */ 546 *val <<= 2; 547 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) { 548 /* 549 * in this case we have 13 bits of real data, but channel 550 * is registered as 14 bits, so left shift one bit 551 */ 552 *val <<= 1; 553 } 554 555 return IIO_VAL_INT; 556} 557 558static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, 559 int len) 560{ 561 int i = 0, val; 562 u16 *buf_u16 = (u16 *) buf; 563 564 /* 565 * We are converting each two bytes (each sample). 566 * First convert the byte based array to u16, and convert each sample 567 * separately. 568 * Each value is two bytes in an array of chars, so to not shift 569 * more than we need, save the value separately. 570 * len is in bytes, so divide by two to get number of samples. 571 */ 572 while (i < len / 2) { 573 val = buf_u16[i]; 574 at91_adc_adjust_val_osr(st, &val); 575 buf_u16[i] = val; 576 i++; 577 } 578} 579 580static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) 581{ 582 u32 clk_khz = st->current_sample_rate / 1000; 583 int i = 0; 584 u16 pendbc; 585 u32 tsmr, acr; 586 587 if (!state) { 588 /* disabling touch IRQs and setting mode to no touch enabled */ 589 at91_adc_writel(st, AT91_SAMA5D2_IDR, 590 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); 591 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0); 592 return 0; 593 } 594 /* 595 * debounce time is in microseconds, we need it in milliseconds to 596 * multiply with kilohertz, so, divide by 1000, but after the multiply. 597 * round up to make sure pendbc is at least 1 598 */ 599 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US * 600 clk_khz / 1000, 1); 601 602 /* get the required exponent */ 603 while (pendbc >> i++) 604 ; 605 606 pendbc = i; 607 608 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS; 609 610 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK; 611 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) & 612 AT91_SAMA5D2_TSMR_PENDBC_MASK; 613 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA; 614 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; 615 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; 616 617 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr); 618 619 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR); 620 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; 621 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; 622 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr); 623 624 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 625 st->touch_st.sample_period_val = 626 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * 627 clk_khz / 1000) - 1, 1); 628 /* enable pen detect IRQ */ 629 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 630 631 return 0; 632} 633 634static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) 635{ 636 u32 val; 637 u32 scale, result, pos; 638 639 /* 640 * to obtain the actual position we must divide by scale 641 * and multiply with max, where 642 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 643 */ 644 /* first half of register is the x or y, second half is the scale */ 645 val = at91_adc_readl(st, reg); 646 if (!val) 647 dev_dbg(&st->indio_dev->dev, "pos is 0\n"); 648 649 pos = val & AT91_SAMA5D2_XYZ_MASK; 650 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; 651 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 652 if (scale == 0) { 653 dev_err(&st->indio_dev->dev, "scale is 0\n"); 654 return 0; 655 } 656 result /= scale; 657 658 return result; 659} 660 661static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) 662{ 663 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR); 664 return st->touch_st.x_pos; 665} 666 667static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) 668{ 669 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR); 670} 671 672static u16 at91_adc_touch_pressure(struct at91_adc_state *st) 673{ 674 u32 val; 675 u32 z1, z2; 676 u32 pres; 677 u32 rxp = 1; 678 u32 factor = 1000; 679 680 /* calculate the pressure */ 681 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 682 z1 = val & AT91_SAMA5D2_XYZ_MASK; 683 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 684 685 if (z1 != 0) 686 pres = rxp * (st->touch_st.x_pos * factor / 1024) * 687 (z2 * factor / z1 - factor) / 688 factor; 689 else 690 pres = 0xFFFF; /* no pen contact */ 691 692 /* 693 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0. 694 * We compute it this way, but let's return it in the expected way, 695 * growing from 0 to 0xFFFF. 696 */ 697 return 0xFFFF - pres; 698} 699 700static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) 701{ 702 *val = 0; 703 if (!st->touch_st.touching) 704 return -ENODATA; 705 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX) 706 *val = at91_adc_touch_x_pos(st); 707 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX) 708 *val = at91_adc_touch_y_pos(st); 709 else 710 return -ENODATA; 711 712 return IIO_VAL_INT; 713} 714 715static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) 716{ 717 *val = 0; 718 if (!st->touch_st.touching) 719 return -ENODATA; 720 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX) 721 *val = at91_adc_touch_pressure(st); 722 else 723 return -ENODATA; 724 725 return IIO_VAL_INT; 726} 727 728static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 729{ 730 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 731 struct at91_adc_state *st = iio_priv(indio); 732 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR); 733 734 /* clear TRGMOD */ 735 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; 736 737 if (state) 738 status |= st->selected_trig->trgmod_value; 739 740 /* set/unset hw trigger */ 741 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status); 742 743 return 0; 744} 745 746static int at91_adc_reenable_trigger(struct iio_trigger *trig) 747{ 748 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 749 struct at91_adc_state *st = iio_priv(indio); 750 751 /* if we are using DMA, we must not reenable irq after each trigger */ 752 if (st->dma_st.dma_chan) 753 return 0; 754 755 enable_irq(st->irq); 756 757 /* Needed to ACK the DRDY interruption */ 758 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 759 760 return 0; 761} 762 763static const struct iio_trigger_ops at91_adc_trigger_ops = { 764 .set_trigger_state = &at91_adc_configure_trigger, 765 .try_reenable = &at91_adc_reenable_trigger, 766 .validate_device = iio_trigger_validate_own_device, 767}; 768 769static int at91_adc_dma_size_done(struct at91_adc_state *st) 770{ 771 struct dma_tx_state state; 772 enum dma_status status; 773 int i, size; 774 775 status = dmaengine_tx_status(st->dma_st.dma_chan, 776 st->dma_st.dma_chan->cookie, 777 &state); 778 if (status != DMA_IN_PROGRESS) 779 return 0; 780 781 /* Transferred length is size in bytes from end of buffer */ 782 i = st->dma_st.rx_buf_sz - state.residue; 783 784 /* Return available bytes */ 785 if (i >= st->dma_st.buf_idx) 786 size = i - st->dma_st.buf_idx; 787 else 788 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; 789 return size; 790} 791 792static void at91_dma_buffer_done(void *data) 793{ 794 struct iio_dev *indio_dev = data; 795 796 iio_trigger_poll_chained(indio_dev->trig); 797} 798 799static int at91_adc_dma_start(struct iio_dev *indio_dev) 800{ 801 struct at91_adc_state *st = iio_priv(indio_dev); 802 struct dma_async_tx_descriptor *desc; 803 dma_cookie_t cookie; 804 int ret; 805 u8 bit; 806 807 if (!st->dma_st.dma_chan) 808 return 0; 809 810 /* we start a new DMA, so set buffer index to start */ 811 st->dma_st.buf_idx = 0; 812 813 /* 814 * compute buffer size w.r.t. watermark and enabled channels. 815 * scan_bytes is aligned so we need an exact size for DMA 816 */ 817 st->dma_st.rx_buf_sz = 0; 818 819 for_each_set_bit(bit, indio_dev->active_scan_mask, 820 indio_dev->num_channels) { 821 struct iio_chan_spec const *chan = 822 at91_adc_chan_get(indio_dev, bit); 823 824 if (!chan) 825 continue; 826 827 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; 828 } 829 st->dma_st.rx_buf_sz *= st->dma_st.watermark; 830 831 /* Prepare a DMA cyclic transaction */ 832 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, 833 st->dma_st.rx_dma_buf, 834 st->dma_st.rx_buf_sz, 835 st->dma_st.rx_buf_sz / 2, 836 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 837 838 if (!desc) { 839 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); 840 return -EBUSY; 841 } 842 843 desc->callback = at91_dma_buffer_done; 844 desc->callback_param = indio_dev; 845 846 cookie = dmaengine_submit(desc); 847 ret = dma_submit_error(cookie); 848 if (ret) { 849 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); 850 dmaengine_terminate_async(st->dma_st.dma_chan); 851 return ret; 852 } 853 854 /* enable general overrun error signaling */ 855 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE); 856 /* Issue pending DMA requests */ 857 dma_async_issue_pending(st->dma_st.dma_chan); 858 859 /* consider current time as DMA start time for timestamps */ 860 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 861 862 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); 863 864 return 0; 865} 866 867static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio, 868 struct at91_adc_state *st) 869{ 870 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ 871 if (st->dma_st.dma_chan) 872 return false; 873 /* if the trigger is not ours, then it has its own IRQ */ 874 if (iio_trigger_validate_own_device(indio->trig, indio)) 875 return false; 876 return true; 877} 878 879static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) 880{ 881 struct at91_adc_state *st = iio_priv(indio_dev); 882 883 return !!bitmap_subset(indio_dev->active_scan_mask, 884 &st->touch_st.channels_bitmask, 885 AT91_SAMA5D2_MAX_CHAN_IDX + 1); 886} 887 888static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) 889{ 890 int ret; 891 u8 bit; 892 struct at91_adc_state *st = iio_priv(indio_dev); 893 894 /* check if we are enabling triggered buffer or the touchscreen */ 895 if (at91_adc_current_chan_is_touch(indio_dev)) 896 return at91_adc_configure_touch(st, true); 897 898 /* if we are not in triggered mode, we cannot enable the buffer. */ 899 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 900 return -EINVAL; 901 902 /* we continue with the triggered buffer */ 903 ret = at91_adc_dma_start(indio_dev); 904 if (ret) { 905 dev_err(&indio_dev->dev, "buffer prepare failed\n"); 906 return ret; 907 } 908 909 for_each_set_bit(bit, indio_dev->active_scan_mask, 910 indio_dev->num_channels) { 911 struct iio_chan_spec const *chan = 912 at91_adc_chan_get(indio_dev, bit); 913 u32 cor; 914 915 if (!chan) 916 continue; 917 /* these channel types cannot be handled by this trigger */ 918 if (chan->type == IIO_POSITIONRELATIVE || 919 chan->type == IIO_PRESSURE) 920 continue; 921 922 cor = at91_adc_readl(st, AT91_SAMA5D2_COR); 923 924 if (chan->differential) 925 cor |= (BIT(chan->channel) | BIT(chan->channel2)) << 926 AT91_SAMA5D2_COR_DIFF_OFFSET; 927 else 928 cor &= ~(BIT(chan->channel) << 929 AT91_SAMA5D2_COR_DIFF_OFFSET); 930 931 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 932 933 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 934 } 935 936 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 937 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY); 938 939 return 0; 940} 941 942static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) 943{ 944 struct at91_adc_state *st = iio_priv(indio_dev); 945 u8 bit; 946 947 /* check if we are disabling triggered buffer or the touchscreen */ 948 if (at91_adc_current_chan_is_touch(indio_dev)) 949 return at91_adc_configure_touch(st, false); 950 951 /* if we are not in triggered mode, nothing to do here */ 952 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 953 return -EINVAL; 954 955 /* 956 * For each enable channel we must disable it in hardware. 957 * In the case of DMA, we must read the last converted value 958 * to clear EOC status and not get a possible interrupt later. 959 * This value is being read by DMA from LCDR anyway, so it's not lost. 960 */ 961 for_each_set_bit(bit, indio_dev->active_scan_mask, 962 indio_dev->num_channels) { 963 struct iio_chan_spec const *chan = 964 at91_adc_chan_get(indio_dev, bit); 965 966 if (!chan) 967 continue; 968 /* these channel types are virtual, no need to do anything */ 969 if (chan->type == IIO_POSITIONRELATIVE || 970 chan->type == IIO_PRESSURE) 971 continue; 972 973 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 974 975 if (st->dma_st.dma_chan) 976 at91_adc_readl(st, chan->address); 977 } 978 979 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 980 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY); 981 982 /* read overflow register to clear possible overflow status */ 983 at91_adc_readl(st, AT91_SAMA5D2_OVER); 984 985 /* if we are using DMA we must clear registers and end DMA */ 986 if (st->dma_st.dma_chan) 987 dmaengine_terminate_sync(st->dma_st.dma_chan); 988 989 return 0; 990} 991 992static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { 993 .postdisable = &at91_adc_buffer_postdisable, 994}; 995 996static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, 997 char *trigger_name) 998{ 999 struct iio_trigger *trig; 1000 int ret; 1001 1002 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, 1003 indio->id, trigger_name); 1004 if (!trig) 1005 return ERR_PTR(-ENOMEM); 1006 1007 trig->dev.parent = indio->dev.parent; 1008 iio_trigger_set_drvdata(trig, indio); 1009 trig->ops = &at91_adc_trigger_ops; 1010 1011 ret = devm_iio_trigger_register(&indio->dev, trig); 1012 if (ret) 1013 return ERR_PTR(ret); 1014 1015 return trig; 1016} 1017 1018static int at91_adc_trigger_init(struct iio_dev *indio) 1019{ 1020 struct at91_adc_state *st = iio_priv(indio); 1021 1022 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); 1023 if (IS_ERR(st->trig)) { 1024 dev_err(&indio->dev, 1025 "could not allocate trigger\n"); 1026 return PTR_ERR(st->trig); 1027 } 1028 1029 return 0; 1030} 1031 1032static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, 1033 struct iio_poll_func *pf) 1034{ 1035 struct at91_adc_state *st = iio_priv(indio_dev); 1036 int i = 0; 1037 int val; 1038 u8 bit; 1039 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); 1040 unsigned int timeout = 50; 1041 1042 /* 1043 * Check if the conversion is ready. If not, wait a little bit, and 1044 * in case of timeout exit with an error. 1045 */ 1046 while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask && 1047 timeout) { 1048 usleep_range(50, 100); 1049 timeout--; 1050 } 1051 1052 /* Cannot read data, not ready. Continue without reporting data */ 1053 if (!timeout) 1054 return; 1055 1056 for_each_set_bit(bit, indio_dev->active_scan_mask, 1057 indio_dev->num_channels) { 1058 struct iio_chan_spec const *chan = 1059 at91_adc_chan_get(indio_dev, bit); 1060 1061 if (!chan) 1062 continue; 1063 /* 1064 * Our external trigger only supports the voltage channels. 1065 * In case someone requested a different type of channel 1066 * just put zeroes to buffer. 1067 * This should not happen because we check the scan mode 1068 * and scan mask when we enable the buffer, and we don't allow 1069 * the buffer to start with a mixed mask (voltage and something 1070 * else). 1071 * Thus, emit a warning. 1072 */ 1073 if (chan->type == IIO_VOLTAGE) { 1074 val = at91_adc_readl(st, chan->address); 1075 at91_adc_adjust_val_osr(st, &val); 1076 st->buffer[i] = val; 1077 } else { 1078 st->buffer[i] = 0; 1079 WARN(true, "This trigger cannot handle this type of channel"); 1080 } 1081 i++; 1082 } 1083 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, 1084 pf->timestamp); 1085} 1086 1087static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) 1088{ 1089 struct at91_adc_state *st = iio_priv(indio_dev); 1090 int transferred_len = at91_adc_dma_size_done(st); 1091 s64 ns = iio_get_time_ns(indio_dev); 1092 s64 interval; 1093 int sample_index = 0, sample_count, sample_size; 1094 1095 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1096 /* if we reached this point, we cannot sample faster */ 1097 if (status & AT91_SAMA5D2_IER_GOVRE) 1098 pr_info_ratelimited("%s: conversion overrun detected\n", 1099 indio_dev->name); 1100 1101 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); 1102 1103 sample_count = div_s64(transferred_len, sample_size); 1104 1105 /* 1106 * interval between samples is total time since last transfer handling 1107 * divided by the number of samples (total size divided by sample size) 1108 */ 1109 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); 1110 1111 while (transferred_len >= sample_size) { 1112 /* 1113 * for all the values in the current sample, 1114 * adjust the values inside the buffer for oversampling 1115 */ 1116 at91_adc_adjust_val_osr_array(st, 1117 &st->dma_st.rx_buf[st->dma_st.buf_idx], 1118 sample_size); 1119 1120 iio_push_to_buffers_with_timestamp(indio_dev, 1121 (st->dma_st.rx_buf + st->dma_st.buf_idx), 1122 (st->dma_st.dma_ts + interval * sample_index)); 1123 /* adjust remaining length */ 1124 transferred_len -= sample_size; 1125 /* adjust buffer index */ 1126 st->dma_st.buf_idx += sample_size; 1127 /* in case of reaching end of buffer, reset index */ 1128 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) 1129 st->dma_st.buf_idx = 0; 1130 sample_index++; 1131 } 1132 /* adjust saved time for next transfer handling */ 1133 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1134} 1135 1136static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 1137{ 1138 struct iio_poll_func *pf = p; 1139 struct iio_dev *indio_dev = pf->indio_dev; 1140 struct at91_adc_state *st = iio_priv(indio_dev); 1141 1142 /* 1143 * If it's not our trigger, start a conversion now, as we are 1144 * actually polling the trigger now. 1145 */ 1146 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) 1147 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1148 1149 if (st->dma_st.dma_chan) 1150 at91_adc_trigger_handler_dma(indio_dev); 1151 else 1152 at91_adc_trigger_handler_nodma(indio_dev, pf); 1153 1154 iio_trigger_notify_done(indio_dev->trig); 1155 1156 return IRQ_HANDLED; 1157} 1158 1159static int at91_adc_buffer_init(struct iio_dev *indio) 1160{ 1161 return devm_iio_triggered_buffer_setup(&indio->dev, indio, 1162 &iio_pollfunc_store_time, 1163 &at91_adc_trigger_handler, &at91_buffer_setup_ops); 1164} 1165 1166static unsigned at91_adc_startup_time(unsigned startup_time_min, 1167 unsigned adc_clk_khz) 1168{ 1169 static const unsigned int startup_lookup[] = { 1170 0, 8, 16, 24, 1171 64, 80, 96, 112, 1172 512, 576, 640, 704, 1173 768, 832, 896, 960 1174 }; 1175 unsigned ticks_min, i; 1176 1177 /* 1178 * Since the adc frequency is checked before, there is no reason 1179 * to not meet the startup time constraint. 1180 */ 1181 1182 ticks_min = startup_time_min * adc_clk_khz / 1000; 1183 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 1184 if (startup_lookup[i] > ticks_min) 1185 break; 1186 1187 return i; 1188} 1189 1190static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq) 1191{ 1192 struct at91_adc_state *st = iio_priv(indio_dev); 1193 unsigned f_per, prescal, startup, mr; 1194 1195 f_per = clk_get_rate(st->per_clk); 1196 prescal = (f_per / (2 * freq)) - 1; 1197 1198 startup = at91_adc_startup_time(st->soc_info.startup_time, 1199 freq / 1000); 1200 1201 mr = at91_adc_readl(st, AT91_SAMA5D2_MR); 1202 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); 1203 mr |= AT91_SAMA5D2_MR_STARTUP(startup); 1204 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); 1205 at91_adc_writel(st, AT91_SAMA5D2_MR, mr); 1206 1207 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", 1208 freq, startup, prescal); 1209 st->current_sample_rate = freq; 1210} 1211 1212static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 1213{ 1214 return st->current_sample_rate; 1215} 1216 1217static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) 1218{ 1219 struct at91_adc_state *st = iio_priv(indio_dev); 1220 u8 bit; 1221 u16 val; 1222 int i = 0; 1223 1224 for_each_set_bit(bit, indio_dev->active_scan_mask, 1225 AT91_SAMA5D2_MAX_CHAN_IDX + 1) { 1226 struct iio_chan_spec const *chan = 1227 at91_adc_chan_get(indio_dev, bit); 1228 1229 if (chan->type == IIO_POSITIONRELATIVE) 1230 at91_adc_read_position(st, chan->channel, &val); 1231 else if (chan->type == IIO_PRESSURE) 1232 at91_adc_read_pressure(st, chan->channel, &val); 1233 else 1234 continue; 1235 st->buffer[i] = val; 1236 i++; 1237 } 1238 /* 1239 * Schedule work to push to buffers. 1240 * This is intended to push to the callback buffer that another driver 1241 * registered. We are still in a handler from our IRQ. If we push 1242 * directly, it means the other driver has it's callback called 1243 * from our IRQ context. Which is something we better avoid. 1244 * Let's schedule it after our IRQ is completed. 1245 */ 1246 schedule_work(&st->touch_st.workq); 1247} 1248 1249static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) 1250{ 1251 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN); 1252 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN | 1253 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1254 AT91_SAMA5D2_IER_PRDY); 1255 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1256 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | 1257 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); 1258 st->touch_st.touching = true; 1259} 1260 1261static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev) 1262{ 1263 struct at91_adc_state *st = iio_priv(indio_dev); 1264 1265 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1266 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); 1267 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN | 1268 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1269 AT91_SAMA5D2_IER_PRDY); 1270 st->touch_st.touching = false; 1271 1272 at91_adc_touch_data_handler(indio_dev); 1273 1274 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 1275} 1276 1277static void at91_adc_workq_handler(struct work_struct *workq) 1278{ 1279 struct at91_adc_touch *touch_st = container_of(workq, 1280 struct at91_adc_touch, workq); 1281 struct at91_adc_state *st = container_of(touch_st, 1282 struct at91_adc_state, touch_st); 1283 struct iio_dev *indio_dev = st->indio_dev; 1284 1285 iio_push_to_buffers(indio_dev, st->buffer); 1286} 1287 1288static irqreturn_t at91_adc_interrupt(int irq, void *private) 1289{ 1290 struct iio_dev *indio = private; 1291 struct at91_adc_state *st = iio_priv(indio); 1292 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1293 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR); 1294 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1295 AT91_SAMA5D2_IER_PRDY; 1296 1297 if (!(status & imr)) 1298 return IRQ_NONE; 1299 if (status & AT91_SAMA5D2_IER_PEN) { 1300 /* pen detected IRQ */ 1301 at91_adc_pen_detect_interrupt(st); 1302 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) { 1303 /* nopen detected IRQ */ 1304 at91_adc_no_pen_detect_interrupt(indio); 1305 } else if ((status & AT91_SAMA5D2_ISR_PENS) && 1306 ((status & rdy_mask) == rdy_mask)) { 1307 /* periodic trigger IRQ - during pen sense */ 1308 at91_adc_touch_data_handler(indio); 1309 } else if (status & AT91_SAMA5D2_ISR_PENS) { 1310 /* 1311 * touching, but the measurements are not ready yet. 1312 * read and ignore. 1313 */ 1314 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); 1315 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); 1316 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 1317 } else if (iio_buffer_enabled(indio) && 1318 (status & AT91_SAMA5D2_IER_DRDY)) { 1319 /* triggered buffer without DMA */ 1320 disable_irq_nosync(irq); 1321 iio_trigger_poll(indio->trig); 1322 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { 1323 /* triggered buffer with DMA - should not happen */ 1324 disable_irq_nosync(irq); 1325 WARN(true, "Unexpected irq occurred\n"); 1326 } else if (!iio_buffer_enabled(indio)) { 1327 /* software requested conversion */ 1328 st->conversion_value = at91_adc_readl(st, st->chan->address); 1329 st->conversion_done = true; 1330 wake_up_interruptible(&st->wq_data_available); 1331 } 1332 return IRQ_HANDLED; 1333} 1334 1335static int at91_adc_read_info_raw(struct iio_dev *indio_dev, 1336 struct iio_chan_spec const *chan, int *val) 1337{ 1338 struct at91_adc_state *st = iio_priv(indio_dev); 1339 u32 cor = 0; 1340 u16 tmp_val; 1341 int ret; 1342 1343 /* 1344 * Keep in mind that we cannot use software trigger or touchscreen 1345 * if external trigger is enabled 1346 */ 1347 if (chan->type == IIO_POSITIONRELATIVE) { 1348 ret = iio_device_claim_direct_mode(indio_dev); 1349 if (ret) 1350 return ret; 1351 mutex_lock(&st->lock); 1352 1353 ret = at91_adc_read_position(st, chan->channel, 1354 &tmp_val); 1355 *val = tmp_val; 1356 if (ret > 0) 1357 ret = at91_adc_adjust_val_osr(st, val); 1358 mutex_unlock(&st->lock); 1359 iio_device_release_direct_mode(indio_dev); 1360 1361 return ret; 1362 } 1363 if (chan->type == IIO_PRESSURE) { 1364 ret = iio_device_claim_direct_mode(indio_dev); 1365 if (ret) 1366 return ret; 1367 mutex_lock(&st->lock); 1368 1369 ret = at91_adc_read_pressure(st, chan->channel, 1370 &tmp_val); 1371 *val = tmp_val; 1372 if (ret > 0) 1373 ret = at91_adc_adjust_val_osr(st, val); 1374 mutex_unlock(&st->lock); 1375 iio_device_release_direct_mode(indio_dev); 1376 1377 return ret; 1378 } 1379 1380 /* in this case we have a voltage channel */ 1381 1382 ret = iio_device_claim_direct_mode(indio_dev); 1383 if (ret) 1384 return ret; 1385 mutex_lock(&st->lock); 1386 1387 st->chan = chan; 1388 1389 if (chan->differential) 1390 cor = (BIT(chan->channel) | BIT(chan->channel2)) << 1391 AT91_SAMA5D2_COR_DIFF_OFFSET; 1392 1393 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 1394 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 1395 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); 1396 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1397 1398 ret = wait_event_interruptible_timeout(st->wq_data_available, 1399 st->conversion_done, 1400 msecs_to_jiffies(1000)); 1401 if (ret == 0) 1402 ret = -ETIMEDOUT; 1403 1404 if (ret > 0) { 1405 *val = st->conversion_value; 1406 ret = at91_adc_adjust_val_osr(st, val); 1407 if (chan->scan_type.sign == 's') 1408 *val = sign_extend32(*val, 1409 chan->scan_type.realbits - 1); 1410 st->conversion_done = false; 1411 } 1412 1413 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); 1414 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 1415 1416 /* Needed to ACK the DRDY interruption */ 1417 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 1418 1419 mutex_unlock(&st->lock); 1420 1421 iio_device_release_direct_mode(indio_dev); 1422 return ret; 1423} 1424 1425static int at91_adc_read_raw(struct iio_dev *indio_dev, 1426 struct iio_chan_spec const *chan, 1427 int *val, int *val2, long mask) 1428{ 1429 struct at91_adc_state *st = iio_priv(indio_dev); 1430 1431 switch (mask) { 1432 case IIO_CHAN_INFO_RAW: 1433 return at91_adc_read_info_raw(indio_dev, chan, val); 1434 case IIO_CHAN_INFO_SCALE: 1435 *val = st->vref_uv / 1000; 1436 if (chan->differential) 1437 *val *= 2; 1438 *val2 = chan->scan_type.realbits; 1439 return IIO_VAL_FRACTIONAL_LOG2; 1440 1441 case IIO_CHAN_INFO_SAMP_FREQ: 1442 *val = at91_adc_get_sample_freq(st); 1443 return IIO_VAL_INT; 1444 1445 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1446 *val = st->oversampling_ratio; 1447 return IIO_VAL_INT; 1448 1449 default: 1450 return -EINVAL; 1451 } 1452} 1453 1454static int at91_adc_write_raw(struct iio_dev *indio_dev, 1455 struct iio_chan_spec const *chan, 1456 int val, int val2, long mask) 1457{ 1458 struct at91_adc_state *st = iio_priv(indio_dev); 1459 1460 switch (mask) { 1461 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1462 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) && 1463 (val != AT91_OSR_16SAMPLES)) 1464 return -EINVAL; 1465 /* if no change, optimize out */ 1466 if (val == st->oversampling_ratio) 1467 return 0; 1468 mutex_lock(&st->lock); 1469 st->oversampling_ratio = val; 1470 /* update ratio */ 1471 at91_adc_config_emr(st); 1472 mutex_unlock(&st->lock); 1473 return 0; 1474 case IIO_CHAN_INFO_SAMP_FREQ: 1475 if (val < st->soc_info.min_sample_rate || 1476 val > st->soc_info.max_sample_rate) 1477 return -EINVAL; 1478 1479 mutex_lock(&st->lock); 1480 at91_adc_setup_samp_freq(indio_dev, val); 1481 mutex_unlock(&st->lock); 1482 return 0; 1483 default: 1484 return -EINVAL; 1485 }; 1486} 1487 1488static void at91_adc_dma_init(struct platform_device *pdev) 1489{ 1490 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1491 struct at91_adc_state *st = iio_priv(indio_dev); 1492 struct dma_slave_config config = {0}; 1493 /* 1494 * We make the buffer double the size of the fifo, 1495 * such that DMA uses one half of the buffer (full fifo size) 1496 * and the software uses the other half to read/write. 1497 */ 1498 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1499 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1500 PAGE_SIZE); 1501 1502 if (st->dma_st.dma_chan) 1503 return; 1504 1505 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx"); 1506 if (IS_ERR(st->dma_st.dma_chan)) { 1507 dev_info(&pdev->dev, "can't get DMA channel\n"); 1508 st->dma_st.dma_chan = NULL; 1509 goto dma_exit; 1510 } 1511 1512 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, 1513 pages * PAGE_SIZE, 1514 &st->dma_st.rx_dma_buf, 1515 GFP_KERNEL); 1516 if (!st->dma_st.rx_buf) { 1517 dev_info(&pdev->dev, "can't allocate coherent DMA area\n"); 1518 goto dma_chan_disable; 1519 } 1520 1521 /* Configure DMA channel to read data register */ 1522 config.direction = DMA_DEV_TO_MEM; 1523 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr 1524 + AT91_SAMA5D2_LCDR); 1525 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1526 config.src_maxburst = 1; 1527 config.dst_maxburst = 1; 1528 1529 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { 1530 dev_info(&pdev->dev, "can't configure DMA slave\n"); 1531 goto dma_free_area; 1532 } 1533 1534 dev_info(&pdev->dev, "using %s for rx DMA transfers\n", 1535 dma_chan_name(st->dma_st.dma_chan)); 1536 1537 return; 1538 1539dma_free_area: 1540 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1541 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1542dma_chan_disable: 1543 dma_release_channel(st->dma_st.dma_chan); 1544 st->dma_st.dma_chan = NULL; 1545dma_exit: 1546 dev_info(&pdev->dev, "continuing without DMA support\n"); 1547} 1548 1549static void at91_adc_dma_disable(struct platform_device *pdev) 1550{ 1551 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1552 struct at91_adc_state *st = iio_priv(indio_dev); 1553 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1554 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1555 PAGE_SIZE); 1556 1557 /* if we are not using DMA, just return */ 1558 if (!st->dma_st.dma_chan) 1559 return; 1560 1561 /* wait for all transactions to be terminated first*/ 1562 dmaengine_terminate_sync(st->dma_st.dma_chan); 1563 1564 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1565 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1566 dma_release_channel(st->dma_st.dma_chan); 1567 st->dma_st.dma_chan = NULL; 1568 1569 dev_info(&pdev->dev, "continuing without DMA support\n"); 1570} 1571 1572static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1573{ 1574 struct at91_adc_state *st = iio_priv(indio_dev); 1575 int ret; 1576 1577 if (val > AT91_HWFIFO_MAX_SIZE) 1578 return -EINVAL; 1579 1580 if (!st->selected_trig->hw_trig) { 1581 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); 1582 return 0; 1583 } 1584 1585 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); 1586 st->dma_st.watermark = val; 1587 1588 /* 1589 * The logic here is: if we have watermark 1, it means we do 1590 * each conversion with it's own IRQ, thus we don't need DMA. 1591 * If the watermark is higher, we do DMA to do all the transfers in bulk 1592 */ 1593 1594 if (val == 1) 1595 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); 1596 else if (val > 1) 1597 at91_adc_dma_init(to_platform_device(&indio_dev->dev)); 1598 1599 /* 1600 * We can start the DMA only after setting the watermark and 1601 * having the DMA initialization completed 1602 */ 1603 ret = at91_adc_buffer_prepare(indio_dev); 1604 if (ret) 1605 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); 1606 1607 return ret; 1608} 1609 1610static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, 1611 const unsigned long *scan_mask) 1612{ 1613 struct at91_adc_state *st = iio_priv(indio_dev); 1614 1615 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, 1616 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1617 return 0; 1618 /* 1619 * if the new bitmap is a combination of touchscreen and regular 1620 * channels, then we are not fine 1621 */ 1622 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, 1623 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1624 return -EINVAL; 1625 return 0; 1626} 1627 1628static void at91_adc_hw_init(struct iio_dev *indio_dev) 1629{ 1630 struct at91_adc_state *st = iio_priv(indio_dev); 1631 1632 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1633 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff); 1634 /* 1635 * Transfer field must be set to 2 according to the datasheet and 1636 * allows different analog settings for each channel. 1637 */ 1638 at91_adc_writel(st, AT91_SAMA5D2_MR, 1639 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); 1640 1641 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); 1642 1643 /* configure extended mode register */ 1644 at91_adc_config_emr(st); 1645} 1646 1647static ssize_t at91_adc_get_fifo_state(struct device *dev, 1648 struct device_attribute *attr, char *buf) 1649{ 1650 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1651 struct at91_adc_state *st = iio_priv(indio_dev); 1652 1653 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan); 1654} 1655 1656static ssize_t at91_adc_get_watermark(struct device *dev, 1657 struct device_attribute *attr, char *buf) 1658{ 1659 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1660 struct at91_adc_state *st = iio_priv(indio_dev); 1661 1662 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); 1663} 1664 1665static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1666 at91_adc_get_fifo_state, NULL, 0); 1667static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1668 at91_adc_get_watermark, NULL, 0); 1669 1670static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); 1671static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 1672 1673static IIO_CONST_ATTR(oversampling_ratio_available, 1674 __stringify(AT91_OSR_1SAMPLES) " " 1675 __stringify(AT91_OSR_4SAMPLES) " " 1676 __stringify(AT91_OSR_16SAMPLES)); 1677 1678static struct attribute *at91_adc_attributes[] = { 1679 &iio_const_attr_oversampling_ratio_available.dev_attr.attr, 1680 NULL, 1681}; 1682 1683static const struct attribute_group at91_adc_attribute_group = { 1684 .attrs = at91_adc_attributes, 1685}; 1686 1687static const struct attribute *at91_adc_fifo_attributes[] = { 1688 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1689 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1690 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1691 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1692 NULL, 1693}; 1694 1695static const struct iio_info at91_adc_info = { 1696 .attrs = &at91_adc_attribute_group, 1697 .read_raw = &at91_adc_read_raw, 1698 .write_raw = &at91_adc_write_raw, 1699 .update_scan_mode = &at91_adc_update_scan_mode, 1700 .of_xlate = &at91_adc_of_xlate, 1701 .hwfifo_set_watermark = &at91_adc_set_watermark, 1702}; 1703 1704static int at91_adc_probe(struct platform_device *pdev) 1705{ 1706 struct iio_dev *indio_dev; 1707 struct at91_adc_state *st; 1708 struct resource *res; 1709 int ret, i; 1710 u32 edge_type = IRQ_TYPE_NONE; 1711 1712 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 1713 if (!indio_dev) 1714 return -ENOMEM; 1715 1716 indio_dev->name = dev_name(&pdev->dev); 1717 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1718 indio_dev->info = &at91_adc_info; 1719 indio_dev->channels = at91_adc_channels; 1720 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); 1721 1722 st = iio_priv(indio_dev); 1723 st->indio_dev = indio_dev; 1724 1725 bitmap_set(&st->touch_st.channels_bitmask, 1726 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1); 1727 bitmap_set(&st->touch_st.channels_bitmask, 1728 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1); 1729 bitmap_set(&st->touch_st.channels_bitmask, 1730 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1); 1731 1732 st->oversampling_ratio = AT91_OSR_1SAMPLES; 1733 1734 ret = of_property_read_u32(pdev->dev.of_node, 1735 "atmel,min-sample-rate-hz", 1736 &st->soc_info.min_sample_rate); 1737 if (ret) { 1738 dev_err(&pdev->dev, 1739 "invalid or missing value for atmel,min-sample-rate-hz\n"); 1740 return ret; 1741 } 1742 1743 ret = of_property_read_u32(pdev->dev.of_node, 1744 "atmel,max-sample-rate-hz", 1745 &st->soc_info.max_sample_rate); 1746 if (ret) { 1747 dev_err(&pdev->dev, 1748 "invalid or missing value for atmel,max-sample-rate-hz\n"); 1749 return ret; 1750 } 1751 1752 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms", 1753 &st->soc_info.startup_time); 1754 if (ret) { 1755 dev_err(&pdev->dev, 1756 "invalid or missing value for atmel,startup-time-ms\n"); 1757 return ret; 1758 } 1759 1760 ret = of_property_read_u32(pdev->dev.of_node, 1761 "atmel,trigger-edge-type", &edge_type); 1762 if (ret) { 1763 dev_dbg(&pdev->dev, 1764 "atmel,trigger-edge-type not specified, only software trigger available\n"); 1765 } 1766 1767 st->selected_trig = NULL; 1768 1769 /* find the right trigger, or no trigger at all */ 1770 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++) 1771 if (at91_adc_trigger_list[i].edge_type == edge_type) { 1772 st->selected_trig = &at91_adc_trigger_list[i]; 1773 break; 1774 } 1775 1776 if (!st->selected_trig) { 1777 dev_err(&pdev->dev, "invalid external trigger edge value\n"); 1778 return -EINVAL; 1779 } 1780 1781 init_waitqueue_head(&st->wq_data_available); 1782 mutex_init(&st->lock); 1783 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); 1784 1785 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1786 if (IS_ERR(st->base)) 1787 return PTR_ERR(st->base); 1788 1789 /* if we plan to use DMA, we need the physical address of the regs */ 1790 st->dma_st.phys_addr = res->start; 1791 1792 st->irq = platform_get_irq(pdev, 0); 1793 if (st->irq <= 0) { 1794 if (!st->irq) 1795 st->irq = -ENXIO; 1796 1797 return st->irq; 1798 } 1799 1800 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 1801 if (IS_ERR(st->per_clk)) 1802 return PTR_ERR(st->per_clk); 1803 1804 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 1805 if (IS_ERR(st->reg)) 1806 return PTR_ERR(st->reg); 1807 1808 st->vref = devm_regulator_get(&pdev->dev, "vref"); 1809 if (IS_ERR(st->vref)) 1810 return PTR_ERR(st->vref); 1811 1812 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 1813 pdev->dev.driver->name, indio_dev); 1814 if (ret) 1815 return ret; 1816 1817 ret = regulator_enable(st->reg); 1818 if (ret) 1819 return ret; 1820 1821 ret = regulator_enable(st->vref); 1822 if (ret) 1823 goto reg_disable; 1824 1825 st->vref_uv = regulator_get_voltage(st->vref); 1826 if (st->vref_uv <= 0) { 1827 ret = -EINVAL; 1828 goto vref_disable; 1829 } 1830 1831 at91_adc_hw_init(indio_dev); 1832 1833 ret = clk_prepare_enable(st->per_clk); 1834 if (ret) 1835 goto vref_disable; 1836 1837 platform_set_drvdata(pdev, indio_dev); 1838 1839 ret = at91_adc_buffer_init(indio_dev); 1840 if (ret < 0) { 1841 dev_err(&pdev->dev, "couldn't initialize the buffer.\n"); 1842 goto per_clk_disable_unprepare; 1843 } 1844 1845 if (st->selected_trig->hw_trig) { 1846 ret = at91_adc_trigger_init(indio_dev); 1847 if (ret < 0) { 1848 dev_err(&pdev->dev, "couldn't setup the triggers.\n"); 1849 goto per_clk_disable_unprepare; 1850 } 1851 /* 1852 * Initially the iio buffer has a length of 2 and 1853 * a watermark of 1 1854 */ 1855 st->dma_st.watermark = 1; 1856 1857 iio_buffer_set_attrs(indio_dev->buffer, 1858 at91_adc_fifo_attributes); 1859 } 1860 1861 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) 1862 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); 1863 1864 ret = iio_device_register(indio_dev); 1865 if (ret < 0) 1866 goto dma_disable; 1867 1868 if (st->selected_trig->hw_trig) 1869 dev_info(&pdev->dev, "setting up trigger as %s\n", 1870 st->selected_trig->name); 1871 1872 dev_info(&pdev->dev, "version: %x\n", 1873 readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); 1874 1875 return 0; 1876 1877dma_disable: 1878 at91_adc_dma_disable(pdev); 1879per_clk_disable_unprepare: 1880 clk_disable_unprepare(st->per_clk); 1881vref_disable: 1882 regulator_disable(st->vref); 1883reg_disable: 1884 regulator_disable(st->reg); 1885 return ret; 1886} 1887 1888static int at91_adc_remove(struct platform_device *pdev) 1889{ 1890 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1891 struct at91_adc_state *st = iio_priv(indio_dev); 1892 1893 iio_device_unregister(indio_dev); 1894 1895 at91_adc_dma_disable(pdev); 1896 1897 clk_disable_unprepare(st->per_clk); 1898 1899 regulator_disable(st->vref); 1900 regulator_disable(st->reg); 1901 1902 return 0; 1903} 1904 1905static __maybe_unused int at91_adc_suspend(struct device *dev) 1906{ 1907 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1908 struct at91_adc_state *st = iio_priv(indio_dev); 1909 1910 if (iio_buffer_enabled(indio_dev)) 1911 at91_adc_buffer_postdisable(indio_dev); 1912 1913 /* 1914 * Do a sofware reset of the ADC before we go to suspend. 1915 * this will ensure that all pins are free from being muxed by the ADC 1916 * and can be used by for other devices. 1917 * Otherwise, ADC will hog them and we can't go to suspend mode. 1918 */ 1919 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1920 1921 clk_disable_unprepare(st->per_clk); 1922 regulator_disable(st->vref); 1923 regulator_disable(st->reg); 1924 1925 return pinctrl_pm_select_sleep_state(dev); 1926} 1927 1928static __maybe_unused int at91_adc_resume(struct device *dev) 1929{ 1930 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1931 struct at91_adc_state *st = iio_priv(indio_dev); 1932 int ret; 1933 1934 ret = pinctrl_pm_select_default_state(dev); 1935 if (ret) 1936 goto resume_failed; 1937 1938 ret = regulator_enable(st->reg); 1939 if (ret) 1940 goto resume_failed; 1941 1942 ret = regulator_enable(st->vref); 1943 if (ret) 1944 goto reg_disable_resume; 1945 1946 ret = clk_prepare_enable(st->per_clk); 1947 if (ret) 1948 goto vref_disable_resume; 1949 1950 at91_adc_hw_init(indio_dev); 1951 1952 /* reconfiguring trigger hardware state */ 1953 if (!iio_buffer_enabled(indio_dev)) 1954 return 0; 1955 1956 ret = at91_adc_buffer_prepare(indio_dev); 1957 if (ret) 1958 goto vref_disable_resume; 1959 1960 return at91_adc_configure_trigger(st->trig, true); 1961 1962vref_disable_resume: 1963 regulator_disable(st->vref); 1964reg_disable_resume: 1965 regulator_disable(st->reg); 1966resume_failed: 1967 dev_err(&indio_dev->dev, "failed to resume\n"); 1968 return ret; 1969} 1970 1971static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); 1972 1973static const struct of_device_id at91_adc_dt_match[] = { 1974 { 1975 .compatible = "atmel,sama5d2-adc", 1976 }, { 1977 /* sentinel */ 1978 } 1979}; 1980MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 1981 1982static struct platform_driver at91_adc_driver = { 1983 .probe = at91_adc_probe, 1984 .remove = at91_adc_remove, 1985 .driver = { 1986 .name = "at91-sama5d2_adc", 1987 .of_match_table = at91_adc_dt_match, 1988 .pm = &at91_adc_pm_ops, 1989 }, 1990}; 1991module_platform_driver(at91_adc_driver) 1992 1993MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 1994MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 1995MODULE_LICENSE("GPL v2"); 1996