1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8#include <linux/module.h> 9#include <linux/device.h> 10#include <linux/kernel.h> 11#include <linux/slab.h> 12#include <linux/spi/spi.h> 13#include <linux/err.h> 14#include <linux/delay.h> 15#include <linux/gpio/consumer.h> 16#include <linux/of_device.h> 17 18 19#include <linux/iio/iio.h> 20#include <linux/iio/sysfs.h> 21 22#include <linux/clk.h> 23 24#include <linux/iio/adc/adi-axi-adc.h> 25 26/* 27 * ADI High-Speed ADC common spi interface registers 28 * See Application-Note AN-877: 29 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 30 */ 31 32#define AN877_ADC_REG_CHIP_PORT_CONF 0x00 33#define AN877_ADC_REG_CHIP_ID 0x01 34#define AN877_ADC_REG_CHIP_GRADE 0x02 35#define AN877_ADC_REG_CHAN_INDEX 0x05 36#define AN877_ADC_REG_TRANSFER 0xFF 37#define AN877_ADC_REG_MODES 0x08 38#define AN877_ADC_REG_TEST_IO 0x0D 39#define AN877_ADC_REG_ADC_INPUT 0x0F 40#define AN877_ADC_REG_OFFSET 0x10 41#define AN877_ADC_REG_OUTPUT_MODE 0x14 42#define AN877_ADC_REG_OUTPUT_ADJUST 0x15 43#define AN877_ADC_REG_OUTPUT_PHASE 0x16 44#define AN877_ADC_REG_OUTPUT_DELAY 0x17 45#define AN877_ADC_REG_VREF 0x18 46#define AN877_ADC_REG_ANALOG_INPUT 0x2C 47 48/* AN877_ADC_REG_TEST_IO */ 49#define AN877_ADC_TESTMODE_OFF 0x0 50#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 51#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 52#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 53#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 54#define AN877_ADC_TESTMODE_PN23_SEQ 0x5 55#define AN877_ADC_TESTMODE_PN9_SEQ 0x6 56#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 57#define AN877_ADC_TESTMODE_USER 0x8 58#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 59#define AN877_ADC_TESTMODE_SYNC 0xA 60#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 61#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 62#define AN877_ADC_TESTMODE_RAMP 0xF 63 64/* AN877_ADC_REG_TRANSFER */ 65#define AN877_ADC_TRANSFER_SYNC 0x1 66 67/* AN877_ADC_REG_OUTPUT_MODE */ 68#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 69#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 70#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 71 72/* AN877_ADC_REG_OUTPUT_PHASE */ 73#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 74#define AN877_ADC_INVERT_DCO_CLK 0x80 75 76/* AN877_ADC_REG_OUTPUT_DELAY */ 77#define AN877_ADC_DCO_DELAY_ENABLE 0x80 78 79/* 80 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 81 */ 82 83#define CHIPID_AD9265 0x64 84#define AD9265_DEF_OUTPUT_MODE 0x40 85#define AD9265_REG_VREF_MASK 0xC0 86 87/* 88 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 89 */ 90 91#define CHIPID_AD9434 0x6A 92#define AD9434_DEF_OUTPUT_MODE 0x00 93#define AD9434_REG_VREF_MASK 0xC0 94 95/* 96 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 97 */ 98 99#define CHIPID_AD9467 0x50 100#define AD9467_DEF_OUTPUT_MODE 0x08 101#define AD9467_REG_VREF_MASK 0x0F 102 103enum { 104 ID_AD9265, 105 ID_AD9434, 106 ID_AD9467, 107}; 108 109struct ad9467_chip_info { 110 struct adi_axi_adc_chip_info axi_adc_info; 111 unsigned int default_output_mode; 112 unsigned int vref_mask; 113}; 114 115#define to_ad9467_chip_info(_info) \ 116 container_of(_info, struct ad9467_chip_info, axi_adc_info) 117 118struct ad9467_state { 119 struct spi_device *spi; 120 struct clk *clk; 121 unsigned int output_mode; 122 unsigned int (*scales)[2]; 123 124 struct gpio_desc *pwrdown_gpio; 125}; 126 127static int ad9467_spi_read(struct spi_device *spi, unsigned int reg) 128{ 129 unsigned char tbuf[2], rbuf[1]; 130 int ret; 131 132 tbuf[0] = 0x80 | (reg >> 8); 133 tbuf[1] = reg & 0xFF; 134 135 ret = spi_write_then_read(spi, 136 tbuf, ARRAY_SIZE(tbuf), 137 rbuf, ARRAY_SIZE(rbuf)); 138 139 if (ret < 0) 140 return ret; 141 142 return rbuf[0]; 143} 144 145static int ad9467_spi_write(struct spi_device *spi, unsigned int reg, 146 unsigned int val) 147{ 148 unsigned char buf[3]; 149 150 buf[0] = reg >> 8; 151 buf[1] = reg & 0xFF; 152 buf[2] = val; 153 154 return spi_write(spi, buf, ARRAY_SIZE(buf)); 155} 156 157static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg, 158 unsigned int writeval, unsigned int *readval) 159{ 160 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 161 struct spi_device *spi = st->spi; 162 int ret; 163 164 if (readval == NULL) { 165 ret = ad9467_spi_write(spi, reg, writeval); 166 if (ret) 167 return ret; 168 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 169 AN877_ADC_TRANSFER_SYNC); 170 } 171 172 ret = ad9467_spi_read(spi, reg); 173 if (ret < 0) 174 return ret; 175 *readval = ret; 176 177 return 0; 178} 179 180static const unsigned int ad9265_scale_table[][2] = { 181 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 182}; 183 184static const unsigned int ad9434_scale_table[][2] = { 185 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 186 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 187 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 188 {1200, 0x0B}, {1180, 0x0C}, 189}; 190 191static const unsigned int ad9467_scale_table[][2] = { 192 {2000, 0}, {2100, 6}, {2200, 7}, 193 {2300, 8}, {2400, 9}, {2500, 10}, 194}; 195 196static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index, 197 unsigned int *val, unsigned int *val2) 198{ 199 const struct adi_axi_adc_chip_info *info = conv->chip_info; 200 const struct iio_chan_spec *chan = &info->channels[0]; 201 unsigned int tmp; 202 203 tmp = (info->scale_table[index][0] * 1000000ULL) >> 204 chan->scan_type.realbits; 205 *val = tmp / 1000000; 206 *val2 = tmp % 1000000; 207} 208 209#define AD9467_CHAN(_chan, _si, _bits, _sign) \ 210{ \ 211 .type = IIO_VOLTAGE, \ 212 .indexed = 1, \ 213 .channel = _chan, \ 214 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 215 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 216 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 217 .scan_index = _si, \ 218 .scan_type = { \ 219 .sign = _sign, \ 220 .realbits = _bits, \ 221 .storagebits = 16, \ 222 }, \ 223} 224 225static const struct iio_chan_spec ad9434_channels[] = { 226 AD9467_CHAN(0, 0, 12, 'S'), 227}; 228 229static const struct iio_chan_spec ad9467_channels[] = { 230 AD9467_CHAN(0, 0, 16, 'S'), 231}; 232 233static const struct ad9467_chip_info ad9467_chip_tbl[] = { 234 [ID_AD9265] = { 235 .axi_adc_info = { 236 .id = CHIPID_AD9265, 237 .max_rate = 125000000UL, 238 .scale_table = ad9265_scale_table, 239 .num_scales = ARRAY_SIZE(ad9265_scale_table), 240 .channels = ad9467_channels, 241 .num_channels = ARRAY_SIZE(ad9467_channels), 242 }, 243 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 244 .vref_mask = AD9265_REG_VREF_MASK, 245 }, 246 [ID_AD9434] = { 247 .axi_adc_info = { 248 .id = CHIPID_AD9434, 249 .max_rate = 500000000UL, 250 .scale_table = ad9434_scale_table, 251 .num_scales = ARRAY_SIZE(ad9434_scale_table), 252 .channels = ad9434_channels, 253 .num_channels = ARRAY_SIZE(ad9434_channels), 254 }, 255 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 256 .vref_mask = AD9434_REG_VREF_MASK, 257 }, 258 [ID_AD9467] = { 259 .axi_adc_info = { 260 .id = CHIPID_AD9467, 261 .max_rate = 250000000UL, 262 .scale_table = ad9467_scale_table, 263 .num_scales = ARRAY_SIZE(ad9467_scale_table), 264 .channels = ad9467_channels, 265 .num_channels = ARRAY_SIZE(ad9467_channels), 266 }, 267 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 268 .vref_mask = AD9467_REG_VREF_MASK, 269 }, 270}; 271 272static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2) 273{ 274 const struct adi_axi_adc_chip_info *info = conv->chip_info; 275 const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info); 276 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 277 unsigned int i, vref_val; 278 int ret; 279 280 ret = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF); 281 if (ret < 0) 282 return ret; 283 284 vref_val = ret & info1->vref_mask; 285 286 for (i = 0; i < info->num_scales; i++) { 287 if (vref_val == info->scale_table[i][1]) 288 break; 289 } 290 291 if (i == info->num_scales) 292 return -ERANGE; 293 294 __ad9467_get_scale(conv, i, val, val2); 295 296 return IIO_VAL_INT_PLUS_MICRO; 297} 298 299static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2) 300{ 301 const struct adi_axi_adc_chip_info *info = conv->chip_info; 302 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 303 unsigned int scale_val[2]; 304 unsigned int i; 305 int ret; 306 307 if (val != 0) 308 return -EINVAL; 309 310 for (i = 0; i < info->num_scales; i++) { 311 __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]); 312 if (scale_val[0] != val || scale_val[1] != val2) 313 continue; 314 315 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_VREF, 316 info->scale_table[i][1]); 317 if (ret < 0) 318 return ret; 319 320 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 321 AN877_ADC_TRANSFER_SYNC); 322 } 323 324 return -EINVAL; 325} 326 327static int ad9467_read_raw(struct adi_axi_adc_conv *conv, 328 struct iio_chan_spec const *chan, 329 int *val, int *val2, long m) 330{ 331 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 332 333 switch (m) { 334 case IIO_CHAN_INFO_SCALE: 335 return ad9467_get_scale(conv, val, val2); 336 case IIO_CHAN_INFO_SAMP_FREQ: 337 *val = clk_get_rate(st->clk); 338 339 return IIO_VAL_INT; 340 default: 341 return -EINVAL; 342 } 343} 344 345static int ad9467_write_raw(struct adi_axi_adc_conv *conv, 346 struct iio_chan_spec const *chan, 347 int val, int val2, long mask) 348{ 349 const struct adi_axi_adc_chip_info *info = conv->chip_info; 350 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 351 long r_clk; 352 353 switch (mask) { 354 case IIO_CHAN_INFO_SCALE: 355 return ad9467_set_scale(conv, val, val2); 356 case IIO_CHAN_INFO_SAMP_FREQ: 357 r_clk = clk_round_rate(st->clk, val); 358 if (r_clk < 0 || r_clk > info->max_rate) { 359 dev_warn(&st->spi->dev, 360 "Error setting ADC sample rate %ld", r_clk); 361 return -EINVAL; 362 } 363 364 return clk_set_rate(st->clk, r_clk); 365 default: 366 return -EINVAL; 367 } 368} 369 370static int ad9467_read_avail(struct adi_axi_adc_conv *conv, 371 struct iio_chan_spec const *chan, 372 const int **vals, int *type, int *length, 373 long mask) 374{ 375 const struct adi_axi_adc_chip_info *info = conv->chip_info; 376 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 377 378 switch (mask) { 379 case IIO_CHAN_INFO_SCALE: 380 *vals = (const int *)st->scales; 381 *type = IIO_VAL_INT_PLUS_MICRO; 382 /* Values are stored in a 2D matrix */ 383 *length = info->num_scales * 2; 384 return IIO_AVAIL_LIST; 385 default: 386 return -EINVAL; 387 } 388} 389 390static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode) 391{ 392 int ret; 393 394 ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode); 395 if (ret < 0) 396 return ret; 397 398 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 399 AN877_ADC_TRANSFER_SYNC); 400} 401 402static int ad9467_scale_fill(struct adi_axi_adc_conv *conv) 403{ 404 const struct adi_axi_adc_chip_info *info = conv->chip_info; 405 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 406 unsigned int i, val1, val2; 407 408 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 409 sizeof(*st->scales), GFP_KERNEL); 410 if (!st->scales) 411 return -ENOMEM; 412 413 for (i = 0; i < info->num_scales; i++) { 414 __ad9467_get_scale(conv, i, &val1, &val2); 415 st->scales[i][0] = val1; 416 st->scales[i][1] = val2; 417 } 418 419 return 0; 420} 421 422static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv) 423{ 424 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 425 426 return ad9467_outputmode_set(st->spi, st->output_mode); 427} 428 429static int ad9467_reset(struct device *dev) 430{ 431 struct gpio_desc *gpio; 432 433 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 434 if (IS_ERR_OR_NULL(gpio)) 435 return PTR_ERR_OR_ZERO(gpio); 436 437 fsleep(1); 438 gpiod_set_value_cansleep(gpio, 0); 439 fsleep(10 * USEC_PER_MSEC); 440 441 return 0; 442} 443 444static int ad9467_probe(struct spi_device *spi) 445{ 446 const struct ad9467_chip_info *info; 447 struct adi_axi_adc_conv *conv; 448 struct ad9467_state *st; 449 unsigned int id; 450 int ret; 451 452 info = of_device_get_match_data(&spi->dev); 453 if (!info) 454 return -ENODEV; 455 456 conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st)); 457 if (IS_ERR(conv)) 458 return PTR_ERR(conv); 459 460 st = adi_axi_adc_conv_priv(conv); 461 st->spi = spi; 462 463 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 464 if (IS_ERR(st->clk)) 465 return PTR_ERR(st->clk); 466 467 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 468 GPIOD_OUT_LOW); 469 if (IS_ERR(st->pwrdown_gpio)) 470 return PTR_ERR(st->pwrdown_gpio); 471 472 ret = ad9467_reset(&spi->dev); 473 if (ret) 474 return ret; 475 476 spi_set_drvdata(spi, st); 477 478 conv->chip_info = &info->axi_adc_info; 479 480 ret = ad9467_scale_fill(conv); 481 if (ret) 482 return ret; 483 484 id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID); 485 if (id != conv->chip_info->id) { 486 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 487 id, conv->chip_info->id); 488 return -ENODEV; 489 } 490 491 conv->reg_access = ad9467_reg_access; 492 conv->write_raw = ad9467_write_raw; 493 conv->read_raw = ad9467_read_raw; 494 conv->read_avail = ad9467_read_avail; 495 conv->preenable_setup = ad9467_preenable_setup; 496 497 st->output_mode = info->default_output_mode | 498 AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 499 500 return 0; 501} 502 503static const struct of_device_id ad9467_of_match[] = { 504 { .compatible = "adi,ad9265", .data = &ad9467_chip_tbl[ID_AD9265], }, 505 { .compatible = "adi,ad9434", .data = &ad9467_chip_tbl[ID_AD9434], }, 506 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], }, 507 {} 508}; 509MODULE_DEVICE_TABLE(of, ad9467_of_match); 510 511static struct spi_driver ad9467_driver = { 512 .driver = { 513 .name = "ad9467", 514 .of_match_table = ad9467_of_match, 515 }, 516 .probe = ad9467_probe, 517}; 518module_spi_driver(ad9467_driver); 519 520MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 521MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 522MODULE_LICENSE("GPL v2"); 523