1// SPDX-License-Identifier: GPL-2.0 2/* ad7949.c - Analog Devices ADC driver 14/16 bits 4/8 channels 3 * 4 * Copyright (C) 2018 CMC NV 5 * 6 * https://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf 7 */ 8 9#include <linux/delay.h> 10#include <linux/iio/iio.h> 11#include <linux/module.h> 12#include <linux/regulator/consumer.h> 13#include <linux/spi/spi.h> 14 15#define AD7949_MASK_CHANNEL_SEL GENMASK(9, 7) 16#define AD7949_MASK_TOTAL GENMASK(13, 0) 17#define AD7949_OFFSET_CHANNEL_SEL 7 18#define AD7949_CFG_READ_BACK 0x1 19#define AD7949_CFG_REG_SIZE_BITS 14 20 21enum { 22 ID_AD7949 = 0, 23 ID_AD7682, 24 ID_AD7689, 25}; 26 27struct ad7949_adc_spec { 28 u8 num_channels; 29 u8 resolution; 30}; 31 32static const struct ad7949_adc_spec ad7949_adc_spec[] = { 33 [ID_AD7949] = { .num_channels = 8, .resolution = 14 }, 34 [ID_AD7682] = { .num_channels = 4, .resolution = 16 }, 35 [ID_AD7689] = { .num_channels = 8, .resolution = 16 }, 36}; 37 38/** 39 * struct ad7949_adc_chip - AD ADC chip 40 * @lock: protects write sequences 41 * @vref: regulator generating Vref 42 * @indio_dev: reference to iio structure 43 * @spi: reference to spi structure 44 * @resolution: resolution of the chip 45 * @cfg: copy of the configuration register 46 * @current_channel: current channel in use 47 * @buffer: buffer to send / receive data to / from device 48 */ 49struct ad7949_adc_chip { 50 struct mutex lock; 51 struct regulator *vref; 52 struct iio_dev *indio_dev; 53 struct spi_device *spi; 54 u8 resolution; 55 u16 cfg; 56 unsigned int current_channel; 57 u16 buffer ____cacheline_aligned; 58}; 59 60static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val, 61 u16 mask) 62{ 63 int ret; 64 int bits_per_word = ad7949_adc->resolution; 65 int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS; 66 struct spi_message msg; 67 struct spi_transfer tx[] = { 68 { 69 .tx_buf = &ad7949_adc->buffer, 70 .len = 2, 71 .bits_per_word = bits_per_word, 72 }, 73 }; 74 75 ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask); 76 ad7949_adc->buffer = ad7949_adc->cfg << shift; 77 spi_message_init_with_transfers(&msg, tx, 1); 78 ret = spi_sync(ad7949_adc->spi, &msg); 79 80 /* 81 * This delay is to avoid a new request before the required time to 82 * send a new command to the device 83 */ 84 udelay(2); 85 return ret; 86} 87 88static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val, 89 unsigned int channel) 90{ 91 int ret; 92 int i; 93 int bits_per_word = ad7949_adc->resolution; 94 int mask = GENMASK(ad7949_adc->resolution - 1, 0); 95 struct spi_message msg; 96 struct spi_transfer tx[] = { 97 { 98 .rx_buf = &ad7949_adc->buffer, 99 .len = 2, 100 .bits_per_word = bits_per_word, 101 }, 102 }; 103 104 /* 105 * 1: write CFG for sample N and read old data (sample N-2) 106 * 2: if CFG was not changed since sample N-1 then we'll get good data 107 * at the next xfer, so we bail out now, otherwise we write something 108 * and we read garbage (sample N-1 configuration). 109 */ 110 for (i = 0; i < 2; i++) { 111 ret = ad7949_spi_write_cfg(ad7949_adc, 112 channel << AD7949_OFFSET_CHANNEL_SEL, 113 AD7949_MASK_CHANNEL_SEL); 114 if (ret) 115 return ret; 116 if (channel == ad7949_adc->current_channel) 117 break; 118 } 119 120 /* 3: write something and read actual data */ 121 ad7949_adc->buffer = 0; 122 spi_message_init_with_transfers(&msg, tx, 1); 123 ret = spi_sync(ad7949_adc->spi, &msg); 124 if (ret) 125 return ret; 126 127 /* 128 * This delay is to avoid a new request before the required time to 129 * send a new command to the device 130 */ 131 udelay(2); 132 133 ad7949_adc->current_channel = channel; 134 135 *val = ad7949_adc->buffer & mask; 136 137 return 0; 138} 139 140#define AD7949_ADC_CHANNEL(chan) { \ 141 .type = IIO_VOLTAGE, \ 142 .indexed = 1, \ 143 .channel = (chan), \ 144 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 145 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 146} 147 148static const struct iio_chan_spec ad7949_adc_channels[] = { 149 AD7949_ADC_CHANNEL(0), 150 AD7949_ADC_CHANNEL(1), 151 AD7949_ADC_CHANNEL(2), 152 AD7949_ADC_CHANNEL(3), 153 AD7949_ADC_CHANNEL(4), 154 AD7949_ADC_CHANNEL(5), 155 AD7949_ADC_CHANNEL(6), 156 AD7949_ADC_CHANNEL(7), 157}; 158 159static int ad7949_spi_read_raw(struct iio_dev *indio_dev, 160 struct iio_chan_spec const *chan, 161 int *val, int *val2, long mask) 162{ 163 struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev); 164 int ret; 165 166 if (!val) 167 return -EINVAL; 168 169 switch (mask) { 170 case IIO_CHAN_INFO_RAW: 171 mutex_lock(&ad7949_adc->lock); 172 ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel); 173 mutex_unlock(&ad7949_adc->lock); 174 175 if (ret < 0) 176 return ret; 177 178 return IIO_VAL_INT; 179 180 case IIO_CHAN_INFO_SCALE: 181 ret = regulator_get_voltage(ad7949_adc->vref); 182 if (ret < 0) 183 return ret; 184 185 *val = ret / 5000; 186 return IIO_VAL_INT; 187 } 188 189 return -EINVAL; 190} 191 192static int ad7949_spi_reg_access(struct iio_dev *indio_dev, 193 unsigned int reg, unsigned int writeval, 194 unsigned int *readval) 195{ 196 struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev); 197 int ret = 0; 198 199 if (readval) 200 *readval = ad7949_adc->cfg; 201 else 202 ret = ad7949_spi_write_cfg(ad7949_adc, 203 writeval & AD7949_MASK_TOTAL, AD7949_MASK_TOTAL); 204 205 return ret; 206} 207 208static const struct iio_info ad7949_spi_info = { 209 .read_raw = ad7949_spi_read_raw, 210 .debugfs_reg_access = ad7949_spi_reg_access, 211}; 212 213static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc) 214{ 215 int ret; 216 int val; 217 218 /* Sequencer disabled, CFG readback disabled, IN0 as default channel */ 219 ad7949_adc->current_channel = 0; 220 ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL); 221 222 /* 223 * Do two dummy conversions to apply the first configuration setting. 224 * Required only after the start up of the device. 225 */ 226 ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel); 227 ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel); 228 229 return ret; 230} 231 232static int ad7949_spi_probe(struct spi_device *spi) 233{ 234 struct device *dev = &spi->dev; 235 const struct ad7949_adc_spec *spec; 236 struct ad7949_adc_chip *ad7949_adc; 237 struct iio_dev *indio_dev; 238 int ret; 239 240 indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc)); 241 if (!indio_dev) { 242 dev_err(dev, "can not allocate iio device\n"); 243 return -ENOMEM; 244 } 245 246 indio_dev->info = &ad7949_spi_info; 247 indio_dev->name = spi_get_device_id(spi)->name; 248 indio_dev->modes = INDIO_DIRECT_MODE; 249 indio_dev->channels = ad7949_adc_channels; 250 spi_set_drvdata(spi, indio_dev); 251 252 ad7949_adc = iio_priv(indio_dev); 253 ad7949_adc->indio_dev = indio_dev; 254 ad7949_adc->spi = spi; 255 256 spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data]; 257 indio_dev->num_channels = spec->num_channels; 258 ad7949_adc->resolution = spec->resolution; 259 260 ad7949_adc->vref = devm_regulator_get(dev, "vref"); 261 if (IS_ERR(ad7949_adc->vref)) { 262 dev_err(dev, "fail to request regulator\n"); 263 return PTR_ERR(ad7949_adc->vref); 264 } 265 266 ret = regulator_enable(ad7949_adc->vref); 267 if (ret < 0) { 268 dev_err(dev, "fail to enable regulator\n"); 269 return ret; 270 } 271 272 mutex_init(&ad7949_adc->lock); 273 274 ret = ad7949_spi_init(ad7949_adc); 275 if (ret) { 276 dev_err(dev, "enable to init this device: %d\n", ret); 277 goto err; 278 } 279 280 ret = iio_device_register(indio_dev); 281 if (ret) { 282 dev_err(dev, "fail to register iio device: %d\n", ret); 283 goto err; 284 } 285 286 return 0; 287 288err: 289 mutex_destroy(&ad7949_adc->lock); 290 regulator_disable(ad7949_adc->vref); 291 292 return ret; 293} 294 295static int ad7949_spi_remove(struct spi_device *spi) 296{ 297 struct iio_dev *indio_dev = spi_get_drvdata(spi); 298 struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev); 299 300 iio_device_unregister(indio_dev); 301 mutex_destroy(&ad7949_adc->lock); 302 regulator_disable(ad7949_adc->vref); 303 304 return 0; 305} 306 307static const struct of_device_id ad7949_spi_of_id[] = { 308 { .compatible = "adi,ad7949" }, 309 { .compatible = "adi,ad7682" }, 310 { .compatible = "adi,ad7689" }, 311 { } 312}; 313MODULE_DEVICE_TABLE(of, ad7949_spi_of_id); 314 315static const struct spi_device_id ad7949_spi_id[] = { 316 { "ad7949", ID_AD7949 }, 317 { "ad7682", ID_AD7682 }, 318 { "ad7689", ID_AD7689 }, 319 { } 320}; 321MODULE_DEVICE_TABLE(spi, ad7949_spi_id); 322 323static struct spi_driver ad7949_spi_driver = { 324 .driver = { 325 .name = "ad7949", 326 .of_match_table = ad7949_spi_of_id, 327 }, 328 .probe = ad7949_spi_probe, 329 .remove = ad7949_spi_remove, 330 .id_table = ad7949_spi_id, 331}; 332module_spi_driver(ad7949_spi_driver); 333 334MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@essensium.com>"); 335MODULE_DESCRIPTION("Analog Devices 14/16-bit 8-channel ADC driver"); 336MODULE_LICENSE("GPL v2"); 337