1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Analog Devices AD7768-1 SPI ADC driver
4 *
5 * Copyright 2017 Analog Devices Inc.
6 */
7#include <linux/bitfield.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/gpio/consumer.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/regulator/consumer.h>
16#include <linux/sysfs.h>
17#include <linux/spi/spi.h>
18
19#include <linux/iio/buffer.h>
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/trigger.h>
23#include <linux/iio/triggered_buffer.h>
24#include <linux/iio/trigger_consumer.h>
25
26/* AD7768 registers definition */
27#define AD7768_REG_CHIP_TYPE		0x3
28#define AD7768_REG_PROD_ID_L		0x4
29#define AD7768_REG_PROD_ID_H		0x5
30#define AD7768_REG_CHIP_GRADE		0x6
31#define AD7768_REG_SCRATCH_PAD		0x0A
32#define AD7768_REG_VENDOR_L		0x0C
33#define AD7768_REG_VENDOR_H		0x0D
34#define AD7768_REG_INTERFACE_FORMAT	0x14
35#define AD7768_REG_POWER_CLOCK		0x15
36#define AD7768_REG_ANALOG		0x16
37#define AD7768_REG_ANALOG2		0x17
38#define AD7768_REG_CONVERSION		0x18
39#define AD7768_REG_DIGITAL_FILTER	0x19
40#define AD7768_REG_SINC3_DEC_RATE_MSB	0x1A
41#define AD7768_REG_SINC3_DEC_RATE_LSB	0x1B
42#define AD7768_REG_DUTY_CYCLE_RATIO	0x1C
43#define AD7768_REG_SYNC_RESET		0x1D
44#define AD7768_REG_GPIO_CONTROL		0x1E
45#define AD7768_REG_GPIO_WRITE		0x1F
46#define AD7768_REG_GPIO_READ		0x20
47#define AD7768_REG_OFFSET_HI		0x21
48#define AD7768_REG_OFFSET_MID		0x22
49#define AD7768_REG_OFFSET_LO		0x23
50#define AD7768_REG_GAIN_HI		0x24
51#define AD7768_REG_GAIN_MID		0x25
52#define AD7768_REG_GAIN_LO		0x26
53#define AD7768_REG_SPI_DIAG_ENABLE	0x28
54#define AD7768_REG_ADC_DIAG_ENABLE	0x29
55#define AD7768_REG_DIG_DIAG_ENABLE	0x2A
56#define AD7768_REG_ADC_DATA		0x2C
57#define AD7768_REG_MASTER_STATUS	0x2D
58#define AD7768_REG_SPI_DIAG_STATUS	0x2E
59#define AD7768_REG_ADC_DIAG_STATUS	0x2F
60#define AD7768_REG_DIG_DIAG_STATUS	0x30
61#define AD7768_REG_MCLK_COUNTER		0x31
62
63/* AD7768_REG_POWER_CLOCK */
64#define AD7768_PWR_MCLK_DIV_MSK		GENMASK(5, 4)
65#define AD7768_PWR_MCLK_DIV(x)		FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
66#define AD7768_PWR_PWRMODE_MSK		GENMASK(1, 0)
67#define AD7768_PWR_PWRMODE(x)		FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
68
69/* AD7768_REG_DIGITAL_FILTER */
70#define AD7768_DIG_FIL_FIL_MSK		GENMASK(6, 4)
71#define AD7768_DIG_FIL_FIL(x)		FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
72#define AD7768_DIG_FIL_DEC_MSK		GENMASK(2, 0)
73#define AD7768_DIG_FIL_DEC_RATE(x)	FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
74
75/* AD7768_REG_CONVERSION */
76#define AD7768_CONV_MODE_MSK		GENMASK(2, 0)
77#define AD7768_CONV_MODE(x)		FIELD_PREP(AD7768_CONV_MODE_MSK, x)
78
79#define AD7768_RD_FLAG_MSK(x)		(BIT(6) | ((x) & 0x3F))
80#define AD7768_WR_FLAG_MSK(x)		((x) & 0x3F)
81
82enum ad7768_conv_mode {
83	AD7768_CONTINUOUS,
84	AD7768_ONE_SHOT,
85	AD7768_SINGLE,
86	AD7768_PERIODIC,
87	AD7768_STANDBY
88};
89
90enum ad7768_pwrmode {
91	AD7768_ECO_MODE = 0,
92	AD7768_MED_MODE = 2,
93	AD7768_FAST_MODE = 3
94};
95
96enum ad7768_mclk_div {
97	AD7768_MCLK_DIV_16,
98	AD7768_MCLK_DIV_8,
99	AD7768_MCLK_DIV_4,
100	AD7768_MCLK_DIV_2
101};
102
103enum ad7768_dec_rate {
104	AD7768_DEC_RATE_32 = 0,
105	AD7768_DEC_RATE_64 = 1,
106	AD7768_DEC_RATE_128 = 2,
107	AD7768_DEC_RATE_256 = 3,
108	AD7768_DEC_RATE_512 = 4,
109	AD7768_DEC_RATE_1024 = 5,
110	AD7768_DEC_RATE_8 = 9,
111	AD7768_DEC_RATE_16 = 10
112};
113
114struct ad7768_clk_configuration {
115	enum ad7768_mclk_div mclk_div;
116	enum ad7768_dec_rate dec_rate;
117	unsigned int clk_div;
118	enum ad7768_pwrmode pwrmode;
119};
120
121static const struct ad7768_clk_configuration ad7768_clk_config[] = {
122	{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16,  AD7768_FAST_MODE },
123	{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32,  AD7768_FAST_MODE },
124	{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
125	{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
126	{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
127	{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
128	{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
129	{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
130	{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
131	{ AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
132	{ AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
133};
134
135static const struct iio_chan_spec ad7768_channels[] = {
136	{
137		.type = IIO_VOLTAGE,
138		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
139		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
140		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
141		.indexed = 1,
142		.channel = 0,
143		.scan_index = 0,
144		.scan_type = {
145			.sign = 'u',
146			.realbits = 24,
147			.storagebits = 32,
148			.shift = 8,
149			.endianness = IIO_BE,
150		},
151	},
152};
153
154struct ad7768_state {
155	struct spi_device *spi;
156	struct regulator *vref;
157	struct mutex lock;
158	struct clk *mclk;
159	unsigned int mclk_freq;
160	unsigned int samp_freq;
161	struct completion completion;
162	struct iio_trigger *trig;
163	struct gpio_desc *gpio_sync_in;
164	/*
165	 * DMA (thus cache coherency maintenance) requires the
166	 * transfer buffers to live in their own cache lines.
167	 */
168	union {
169		struct {
170			__be32 chan;
171			s64 timestamp;
172		} scan;
173		__be32 d32;
174		u8 d8[2];
175	} data ____cacheline_aligned;
176};
177
178static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
179			       unsigned int len)
180{
181	unsigned int shift;
182	int ret;
183
184	shift = 32 - (8 * len);
185	st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
186
187	ret = spi_write_then_read(st->spi, st->data.d8, 1,
188				  &st->data.d32, len);
189	if (ret < 0)
190		return ret;
191
192	return (be32_to_cpu(st->data.d32) >> shift);
193}
194
195static int ad7768_spi_reg_write(struct ad7768_state *st,
196				unsigned int addr,
197				unsigned int val)
198{
199	st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
200	st->data.d8[1] = val & 0xFF;
201
202	return spi_write(st->spi, st->data.d8, 2);
203}
204
205static int ad7768_set_mode(struct ad7768_state *st,
206			   enum ad7768_conv_mode mode)
207{
208	int regval;
209
210	regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
211	if (regval < 0)
212		return regval;
213
214	regval &= ~AD7768_CONV_MODE_MSK;
215	regval |= AD7768_CONV_MODE(mode);
216
217	return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
218}
219
220static int ad7768_scan_direct(struct iio_dev *indio_dev)
221{
222	struct ad7768_state *st = iio_priv(indio_dev);
223	int readval, ret;
224
225	reinit_completion(&st->completion);
226
227	ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
228	if (ret < 0)
229		return ret;
230
231	ret = wait_for_completion_timeout(&st->completion,
232					  msecs_to_jiffies(1000));
233	if (!ret)
234		return -ETIMEDOUT;
235
236	readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
237	if (readval < 0)
238		return readval;
239	/*
240	 * Any SPI configuration of the AD7768-1 can only be
241	 * performed in continuous conversion mode.
242	 */
243	ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
244	if (ret < 0)
245		return ret;
246
247	return readval;
248}
249
250static int ad7768_reg_access(struct iio_dev *indio_dev,
251			     unsigned int reg,
252			     unsigned int writeval,
253			     unsigned int *readval)
254{
255	struct ad7768_state *st = iio_priv(indio_dev);
256	int ret;
257
258	mutex_lock(&st->lock);
259	if (readval) {
260		ret = ad7768_spi_reg_read(st, reg, 1);
261		if (ret < 0)
262			goto err_unlock;
263		*readval = ret;
264		ret = 0;
265	} else {
266		ret = ad7768_spi_reg_write(st, reg, writeval);
267	}
268err_unlock:
269	mutex_unlock(&st->lock);
270
271	return ret;
272}
273
274static int ad7768_set_dig_fil(struct ad7768_state *st,
275			      enum ad7768_dec_rate dec_rate)
276{
277	unsigned int mode;
278	int ret;
279
280	if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
281		mode = AD7768_DIG_FIL_FIL(dec_rate);
282	else
283		mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
284
285	ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
286	if (ret < 0)
287		return ret;
288
289	/* A sync-in pulse is required every time the filter dec rate changes */
290	gpiod_set_value(st->gpio_sync_in, 1);
291	gpiod_set_value(st->gpio_sync_in, 0);
292
293	return 0;
294}
295
296static int ad7768_set_freq(struct ad7768_state *st,
297			   unsigned int freq)
298{
299	unsigned int diff_new, diff_old, pwr_mode, i, idx;
300	int res, ret;
301
302	diff_old = U32_MAX;
303	idx = 0;
304
305	res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
306
307	/* Find the closest match for the desired sampling frequency */
308	for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
309		diff_new = abs(res - ad7768_clk_config[i].clk_div);
310		if (diff_new < diff_old) {
311			diff_old = diff_new;
312			idx = i;
313		}
314	}
315
316	/*
317	 * Set both the mclk_div and pwrmode with a single write to the
318	 * POWER_CLOCK register
319	 */
320	pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
321		   AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
322	ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
323	if (ret < 0)
324		return ret;
325
326	ret =  ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
327	if (ret < 0)
328		return ret;
329
330	st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
331					  ad7768_clk_config[idx].clk_div);
332
333	return 0;
334}
335
336static ssize_t ad7768_sampling_freq_avail(struct device *dev,
337					  struct device_attribute *attr,
338					  char *buf)
339{
340	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
341	struct ad7768_state *st = iio_priv(indio_dev);
342	unsigned int freq;
343	int i, len = 0;
344
345	for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
346		freq = DIV_ROUND_CLOSEST(st->mclk_freq,
347					 ad7768_clk_config[i].clk_div);
348		len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
349	}
350
351	buf[len - 1] = '\n';
352
353	return len;
354}
355
356static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
357
358static int ad7768_read_raw(struct iio_dev *indio_dev,
359			   struct iio_chan_spec const *chan,
360			   int *val, int *val2, long info)
361{
362	struct ad7768_state *st = iio_priv(indio_dev);
363	int scale_uv, ret;
364
365	switch (info) {
366	case IIO_CHAN_INFO_RAW:
367		ret = iio_device_claim_direct_mode(indio_dev);
368		if (ret)
369			return ret;
370
371		ret = ad7768_scan_direct(indio_dev);
372		if (ret >= 0)
373			*val = ret;
374
375		iio_device_release_direct_mode(indio_dev);
376		if (ret < 0)
377			return ret;
378
379		return IIO_VAL_INT;
380
381	case IIO_CHAN_INFO_SCALE:
382		scale_uv = regulator_get_voltage(st->vref);
383		if (scale_uv < 0)
384			return scale_uv;
385
386		*val = (scale_uv * 2) / 1000;
387		*val2 = chan->scan_type.realbits;
388
389		return IIO_VAL_FRACTIONAL_LOG2;
390
391	case IIO_CHAN_INFO_SAMP_FREQ:
392		*val = st->samp_freq;
393
394		return IIO_VAL_INT;
395	}
396
397	return -EINVAL;
398}
399
400static int ad7768_write_raw(struct iio_dev *indio_dev,
401			    struct iio_chan_spec const *chan,
402			    int val, int val2, long info)
403{
404	struct ad7768_state *st = iio_priv(indio_dev);
405
406	switch (info) {
407	case IIO_CHAN_INFO_SAMP_FREQ:
408		return ad7768_set_freq(st, val);
409	default:
410		return -EINVAL;
411	}
412}
413
414static struct attribute *ad7768_attributes[] = {
415	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
416	NULL
417};
418
419static const struct attribute_group ad7768_group = {
420	.attrs = ad7768_attributes,
421};
422
423static const struct iio_info ad7768_info = {
424	.attrs = &ad7768_group,
425	.read_raw = &ad7768_read_raw,
426	.write_raw = &ad7768_write_raw,
427	.debugfs_reg_access = &ad7768_reg_access,
428};
429
430static int ad7768_setup(struct ad7768_state *st)
431{
432	int ret;
433
434	/*
435	 * Two writes to the SPI_RESET[1:0] bits are required to initiate
436	 * a software reset. The bits must first be set to 11, and then
437	 * to 10. When the sequence is detected, the reset occurs.
438	 * See the datasheet, page 70.
439	 */
440	ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
441	if (ret)
442		return ret;
443
444	ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
445	if (ret)
446		return ret;
447
448	st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
449					  GPIOD_OUT_LOW);
450	if (IS_ERR(st->gpio_sync_in))
451		return PTR_ERR(st->gpio_sync_in);
452
453	/* Set the default sampling frequency to 32000 kSPS */
454	return ad7768_set_freq(st, 32000);
455}
456
457static irqreturn_t ad7768_trigger_handler(int irq, void *p)
458{
459	struct iio_poll_func *pf = p;
460	struct iio_dev *indio_dev = pf->indio_dev;
461	struct ad7768_state *st = iio_priv(indio_dev);
462	int ret;
463
464	mutex_lock(&st->lock);
465
466	ret = spi_read(st->spi, &st->data.scan.chan, 3);
467	if (ret < 0)
468		goto err_unlock;
469
470	iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
471					   iio_get_time_ns(indio_dev));
472
473err_unlock:
474	iio_trigger_notify_done(indio_dev->trig);
475	mutex_unlock(&st->lock);
476
477	return IRQ_HANDLED;
478}
479
480static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
481{
482	struct iio_dev *indio_dev = dev_id;
483	struct ad7768_state *st = iio_priv(indio_dev);
484
485	if (iio_buffer_enabled(indio_dev))
486		iio_trigger_poll(st->trig);
487	else
488		complete(&st->completion);
489
490	return IRQ_HANDLED;
491};
492
493static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
494{
495	struct ad7768_state *st = iio_priv(indio_dev);
496
497	/*
498	 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
499	 * continuous read mode. Subsequent data reads do not require an
500	 * initial 8-bit write to query the ADC_DATA register.
501	 */
502	return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
503}
504
505static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
506{
507	struct ad7768_state *st = iio_priv(indio_dev);
508
509	/*
510	 * To exit continuous read mode, perform a single read of the ADC_DATA
511	 * reg (0x2C), which allows further configuration of the device.
512	 */
513	return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
514}
515
516static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
517	.postenable = &ad7768_buffer_postenable,
518	.predisable = &ad7768_buffer_predisable,
519};
520
521static const struct iio_trigger_ops ad7768_trigger_ops = {
522	.validate_device = iio_trigger_validate_own_device,
523};
524
525static void ad7768_regulator_disable(void *data)
526{
527	struct ad7768_state *st = data;
528
529	regulator_disable(st->vref);
530}
531
532static void ad7768_clk_disable(void *data)
533{
534	struct ad7768_state *st = data;
535
536	clk_disable_unprepare(st->mclk);
537}
538
539static int ad7768_probe(struct spi_device *spi)
540{
541	struct ad7768_state *st;
542	struct iio_dev *indio_dev;
543	int ret;
544
545	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
546	if (!indio_dev)
547		return -ENOMEM;
548
549	st = iio_priv(indio_dev);
550	st->spi = spi;
551
552	st->vref = devm_regulator_get(&spi->dev, "vref");
553	if (IS_ERR(st->vref))
554		return PTR_ERR(st->vref);
555
556	ret = regulator_enable(st->vref);
557	if (ret) {
558		dev_err(&spi->dev, "Failed to enable specified vref supply\n");
559		return ret;
560	}
561
562	ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
563	if (ret)
564		return ret;
565
566	st->mclk = devm_clk_get(&spi->dev, "mclk");
567	if (IS_ERR(st->mclk))
568		return PTR_ERR(st->mclk);
569
570	ret = clk_prepare_enable(st->mclk);
571	if (ret < 0)
572		return ret;
573
574	ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st);
575	if (ret)
576		return ret;
577
578	st->mclk_freq = clk_get_rate(st->mclk);
579
580	spi_set_drvdata(spi, indio_dev);
581	mutex_init(&st->lock);
582
583	indio_dev->channels = ad7768_channels;
584	indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
585	indio_dev->name = spi_get_device_id(spi)->name;
586	indio_dev->info = &ad7768_info;
587	indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED;
588
589	ret = ad7768_setup(st);
590	if (ret < 0) {
591		dev_err(&spi->dev, "AD7768 setup failed\n");
592		return ret;
593	}
594
595	st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
596					  indio_dev->name, indio_dev->id);
597	if (!st->trig)
598		return -ENOMEM;
599
600	st->trig->ops = &ad7768_trigger_ops;
601	st->trig->dev.parent = &spi->dev;
602	iio_trigger_set_drvdata(st->trig, indio_dev);
603	ret = devm_iio_trigger_register(&spi->dev, st->trig);
604	if (ret)
605		return ret;
606
607	indio_dev->trig = iio_trigger_get(st->trig);
608
609	init_completion(&st->completion);
610
611	ret = devm_request_irq(&spi->dev, spi->irq,
612			       &ad7768_interrupt,
613			       IRQF_TRIGGER_RISING | IRQF_ONESHOT,
614			       indio_dev->name, indio_dev);
615	if (ret)
616		return ret;
617
618	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
619					      &iio_pollfunc_store_time,
620					      &ad7768_trigger_handler,
621					      &ad7768_buffer_ops);
622	if (ret)
623		return ret;
624
625	return devm_iio_device_register(&spi->dev, indio_dev);
626}
627
628static const struct spi_device_id ad7768_id_table[] = {
629	{ "ad7768-1", 0 },
630	{}
631};
632MODULE_DEVICE_TABLE(spi, ad7768_id_table);
633
634static const struct of_device_id ad7768_of_match[] = {
635	{ .compatible = "adi,ad7768-1" },
636	{ },
637};
638MODULE_DEVICE_TABLE(of, ad7768_of_match);
639
640static struct spi_driver ad7768_driver = {
641	.driver = {
642		.name = "ad7768-1",
643		.of_match_table = ad7768_of_match,
644	},
645	.probe = ad7768_probe,
646	.id_table = ad7768_id_table,
647};
648module_spi_driver(ad7768_driver);
649
650MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
651MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
652MODULE_LICENSE("GPL v2");
653