1// SPDX-License-Identifier: GPL-2.0 2/* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21#include <linux/module.h> 22#include <linux/i2c.h> 23#include <linux/iio/iio.h> 24#include <linux/iio/sysfs.h> 25#include <linux/iio/buffer.h> 26#include <linux/iio/trigger.h> 27#include <linux/iio/trigger_consumer.h> 28#include <linux/iio/triggered_buffer.h> 29#include <linux/iio/events.h> 30#include <linux/delay.h> 31#include <linux/of_device.h> 32#include <linux/of_irq.h> 33#include <linux/pm_runtime.h> 34#include <linux/regulator/consumer.h> 35 36#define MMA8452_STATUS 0x00 37#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 38#define MMA8452_OUT_X 0x01 /* MSB first */ 39#define MMA8452_OUT_Y 0x03 40#define MMA8452_OUT_Z 0x05 41#define MMA8452_INT_SRC 0x0c 42#define MMA8452_WHO_AM_I 0x0d 43#define MMA8452_DATA_CFG 0x0e 44#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 45#define MMA8452_DATA_CFG_FS_2G 0 46#define MMA8452_DATA_CFG_FS_4G 1 47#define MMA8452_DATA_CFG_FS_8G 2 48#define MMA8452_DATA_CFG_HPF_MASK BIT(4) 49#define MMA8452_HP_FILTER_CUTOFF 0x0f 50#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 51#define MMA8452_FF_MT_CFG 0x15 52#define MMA8452_FF_MT_CFG_OAE BIT(6) 53#define MMA8452_FF_MT_CFG_ELE BIT(7) 54#define MMA8452_FF_MT_SRC 0x16 55#define MMA8452_FF_MT_SRC_XHE BIT(1) 56#define MMA8452_FF_MT_SRC_YHE BIT(3) 57#define MMA8452_FF_MT_SRC_ZHE BIT(5) 58#define MMA8452_FF_MT_THS 0x17 59#define MMA8452_FF_MT_THS_MASK 0x7f 60#define MMA8452_FF_MT_COUNT 0x18 61#define MMA8452_FF_MT_CHAN_SHIFT 3 62#define MMA8452_TRANSIENT_CFG 0x1d 63#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 64#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 65#define MMA8452_TRANSIENT_CFG_ELE BIT(4) 66#define MMA8452_TRANSIENT_SRC 0x1e 67#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 68#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 69#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 70#define MMA8452_TRANSIENT_THS 0x1f 71#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 72#define MMA8452_TRANSIENT_COUNT 0x20 73#define MMA8452_TRANSIENT_CHAN_SHIFT 1 74#define MMA8452_CTRL_REG1 0x2a 75#define MMA8452_CTRL_ACTIVE BIT(0) 76#define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 77#define MMA8452_CTRL_DR_SHIFT 3 78#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 79#define MMA8452_CTRL_REG2 0x2b 80#define MMA8452_CTRL_REG2_RST BIT(6) 81#define MMA8452_CTRL_REG2_MODS_SHIFT 3 82#define MMA8452_CTRL_REG2_MODS_MASK 0x1b 83#define MMA8452_CTRL_REG4 0x2d 84#define MMA8452_CTRL_REG5 0x2e 85#define MMA8452_OFF_X 0x2f 86#define MMA8452_OFF_Y 0x30 87#define MMA8452_OFF_Z 0x31 88 89#define MMA8452_MAX_REG 0x31 90 91#define MMA8452_INT_DRDY BIT(0) 92#define MMA8452_INT_FF_MT BIT(2) 93#define MMA8452_INT_TRANS BIT(5) 94 95#define MMA8451_DEVICE_ID 0x1a 96#define MMA8452_DEVICE_ID 0x2a 97#define MMA8453_DEVICE_ID 0x3a 98#define MMA8652_DEVICE_ID 0x4a 99#define MMA8653_DEVICE_ID 0x5a 100#define FXLS8471_DEVICE_ID 0x6a 101 102#define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 103 104struct mma8452_data { 105 struct i2c_client *client; 106 struct mutex lock; 107 u8 ctrl_reg1; 108 u8 data_cfg; 109 const struct mma_chip_info *chip_info; 110 int sleep_val; 111 struct regulator *vdd_reg; 112 struct regulator *vddio_reg; 113 114 /* Ensure correct alignment of time stamp when present */ 115 struct { 116 __be16 channels[3]; 117 s64 ts __aligned(8); 118 } buffer; 119}; 120 121 /** 122 * struct mma8452_event_regs - chip specific data related to events 123 * @ev_cfg: event config register address 124 * @ev_cfg_ele: latch bit in event config register 125 * @ev_cfg_chan_shift: number of the bit to enable events in X 126 * direction; in event config register 127 * @ev_src: event source register address 128 * @ev_ths: event threshold register address 129 * @ev_ths_mask: mask for the threshold value 130 * @ev_count: event count (period) register address 131 * 132 * Since not all chips supported by the driver support comparing high pass 133 * filtered data for events (interrupts), different interrupt sources are 134 * used for different chips and the relevant registers are included here. 135 */ 136struct mma8452_event_regs { 137 u8 ev_cfg; 138 u8 ev_cfg_ele; 139 u8 ev_cfg_chan_shift; 140 u8 ev_src; 141 u8 ev_ths; 142 u8 ev_ths_mask; 143 u8 ev_count; 144}; 145 146static const struct mma8452_event_regs ff_mt_ev_regs = { 147 .ev_cfg = MMA8452_FF_MT_CFG, 148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 150 .ev_src = MMA8452_FF_MT_SRC, 151 .ev_ths = MMA8452_FF_MT_THS, 152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 153 .ev_count = MMA8452_FF_MT_COUNT 154}; 155 156static const struct mma8452_event_regs trans_ev_regs = { 157 .ev_cfg = MMA8452_TRANSIENT_CFG, 158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 160 .ev_src = MMA8452_TRANSIENT_SRC, 161 .ev_ths = MMA8452_TRANSIENT_THS, 162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 163 .ev_count = MMA8452_TRANSIENT_COUNT, 164}; 165 166/** 167 * struct mma_chip_info - chip specific data 168 * @chip_id: WHO_AM_I register's value 169 * @channels: struct iio_chan_spec matching the device's 170 * capabilities 171 * @num_channels: number of channels 172 * @mma_scales: scale factors for converting register values 173 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 174 * per mode: m/s^2 and micro m/s^2 175 * @all_events: all events supported by this chip 176 * @enabled_events: event flags enabled and handled by this driver 177 */ 178struct mma_chip_info { 179 const char *name; 180 u8 chip_id; 181 const struct iio_chan_spec *channels; 182 int num_channels; 183 const int mma_scales[3][2]; 184 int all_events; 185 int enabled_events; 186}; 187 188enum { 189 idx_x, 190 idx_y, 191 idx_z, 192 idx_ts, 193}; 194 195static int mma8452_drdy(struct mma8452_data *data) 196{ 197 int tries = 150; 198 199 while (tries-- > 0) { 200 int ret = i2c_smbus_read_byte_data(data->client, 201 MMA8452_STATUS); 202 if (ret < 0) 203 return ret; 204 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 205 return 0; 206 207 if (data->sleep_val <= 20) 208 usleep_range(data->sleep_val * 250, 209 data->sleep_val * 500); 210 else 211 msleep(20); 212 } 213 214 dev_err(&data->client->dev, "data not ready\n"); 215 216 return -EIO; 217} 218 219static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 220{ 221#ifdef CONFIG_PM 222 int ret; 223 224 if (on) { 225 ret = pm_runtime_get_sync(&client->dev); 226 } else { 227 pm_runtime_mark_last_busy(&client->dev); 228 ret = pm_runtime_put_autosuspend(&client->dev); 229 } 230 231 if (ret < 0) { 232 dev_err(&client->dev, 233 "failed to change power state to %d\n", on); 234 if (on) 235 pm_runtime_put_noidle(&client->dev); 236 237 return ret; 238 } 239#endif 240 241 return 0; 242} 243 244static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 245{ 246 int ret = mma8452_drdy(data); 247 248 if (ret < 0) 249 return ret; 250 251 ret = mma8452_set_runtime_pm_state(data->client, true); 252 if (ret) 253 return ret; 254 255 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 256 3 * sizeof(__be16), (u8 *)buf); 257 258 ret = mma8452_set_runtime_pm_state(data->client, false); 259 260 return ret; 261} 262 263static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 264 int n) 265{ 266 size_t len = 0; 267 268 while (n-- > 0) 269 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 270 vals[n][0], vals[n][1]); 271 272 /* replace trailing space by newline */ 273 buf[len - 1] = '\n'; 274 275 return len; 276} 277 278static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 279 int val, int val2) 280{ 281 while (n-- > 0) 282 if (val == vals[n][0] && val2 == vals[n][1]) 283 return n; 284 285 return -EINVAL; 286} 287 288static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 289{ 290 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 291 MMA8452_CTRL_DR_SHIFT; 292} 293 294static const int mma8452_samp_freq[8][2] = { 295 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 296 {6, 250000}, {1, 560000} 297}; 298 299/* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 300static const unsigned int mma8452_time_step_us[4][8] = { 301 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 302 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 303 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 304 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 305}; 306 307/* Datasheet table "High-Pass Filter Cutoff Options" */ 308static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 309 { /* normal */ 310 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 312 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 313 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 318 }, 319 { /* low noise low power */ 320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 322 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 323 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 324 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 327 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 328 }, 329 { /* high resolution */ 330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 338 }, 339 { /* low power */ 340 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 341 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 342 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 343 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 344 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 347 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 348 } 349}; 350 351/* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 352static const u16 mma8452_os_ratio[4][8] = { 353 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 354 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 355 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 356 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 357 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 358}; 359 360static int mma8452_get_power_mode(struct mma8452_data *data) 361{ 362 int reg; 363 364 reg = i2c_smbus_read_byte_data(data->client, 365 MMA8452_CTRL_REG2); 366 if (reg < 0) 367 return reg; 368 369 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 370 MMA8452_CTRL_REG2_MODS_SHIFT); 371} 372 373static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376{ 377 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 378 ARRAY_SIZE(mma8452_samp_freq)); 379} 380 381static ssize_t mma8452_show_scale_avail(struct device *dev, 382 struct device_attribute *attr, 383 char *buf) 384{ 385 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 386 to_i2c_client(dev))); 387 388 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 389 ARRAY_SIZE(data->chip_info->mma_scales)); 390} 391 392static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 393 struct device_attribute *attr, 394 char *buf) 395{ 396 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 397 struct mma8452_data *data = iio_priv(indio_dev); 398 int i, j; 399 400 i = mma8452_get_odr_index(data); 401 j = mma8452_get_power_mode(data); 402 if (j < 0) 403 return j; 404 405 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 406 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 407} 408 409static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 410 struct device_attribute *attr, 411 char *buf) 412{ 413 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 414 struct mma8452_data *data = iio_priv(indio_dev); 415 int i = mma8452_get_odr_index(data); 416 int j; 417 u16 val = 0; 418 size_t len = 0; 419 420 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 421 if (val == mma8452_os_ratio[j][i]) 422 continue; 423 424 val = mma8452_os_ratio[j][i]; 425 426 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 427 } 428 buf[len - 1] = '\n'; 429 430 return len; 431} 432 433static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 434static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 435 mma8452_show_scale_avail, NULL, 0); 436static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 437 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 438static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 439 mma8452_show_os_ratio_avail, NULL, 0); 440 441static int mma8452_get_samp_freq_index(struct mma8452_data *data, 442 int val, int val2) 443{ 444 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 445 ARRAY_SIZE(mma8452_samp_freq), 446 val, val2); 447} 448 449static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 450{ 451 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 452 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 453} 454 455static int mma8452_get_hp_filter_index(struct mma8452_data *data, 456 int val, int val2) 457{ 458 int i, j; 459 460 i = mma8452_get_odr_index(data); 461 j = mma8452_get_power_mode(data); 462 if (j < 0) 463 return j; 464 465 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 466 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 467} 468 469static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 470{ 471 int j, i, ret; 472 473 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 474 if (ret < 0) 475 return ret; 476 477 i = mma8452_get_odr_index(data); 478 j = mma8452_get_power_mode(data); 479 if (j < 0) 480 return j; 481 482 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 483 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 484 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 485 486 return 0; 487} 488 489static int mma8452_read_raw(struct iio_dev *indio_dev, 490 struct iio_chan_spec const *chan, 491 int *val, int *val2, long mask) 492{ 493 struct mma8452_data *data = iio_priv(indio_dev); 494 __be16 buffer[3]; 495 int i, ret; 496 497 switch (mask) { 498 case IIO_CHAN_INFO_RAW: 499 ret = iio_device_claim_direct_mode(indio_dev); 500 if (ret) 501 return ret; 502 503 mutex_lock(&data->lock); 504 ret = mma8452_read(data, buffer); 505 mutex_unlock(&data->lock); 506 iio_device_release_direct_mode(indio_dev); 507 if (ret < 0) 508 return ret; 509 510 *val = sign_extend32(be16_to_cpu( 511 buffer[chan->scan_index]) >> chan->scan_type.shift, 512 chan->scan_type.realbits - 1); 513 514 return IIO_VAL_INT; 515 case IIO_CHAN_INFO_SCALE: 516 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 517 *val = data->chip_info->mma_scales[i][0]; 518 *val2 = data->chip_info->mma_scales[i][1]; 519 520 return IIO_VAL_INT_PLUS_MICRO; 521 case IIO_CHAN_INFO_SAMP_FREQ: 522 i = mma8452_get_odr_index(data); 523 *val = mma8452_samp_freq[i][0]; 524 *val2 = mma8452_samp_freq[i][1]; 525 526 return IIO_VAL_INT_PLUS_MICRO; 527 case IIO_CHAN_INFO_CALIBBIAS: 528 ret = i2c_smbus_read_byte_data(data->client, 529 MMA8452_OFF_X + 530 chan->scan_index); 531 if (ret < 0) 532 return ret; 533 534 *val = sign_extend32(ret, 7); 535 536 return IIO_VAL_INT; 537 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 538 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 539 ret = mma8452_read_hp_filter(data, val, val2); 540 if (ret < 0) 541 return ret; 542 } else { 543 *val = 0; 544 *val2 = 0; 545 } 546 547 return IIO_VAL_INT_PLUS_MICRO; 548 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 549 ret = mma8452_get_power_mode(data); 550 if (ret < 0) 551 return ret; 552 553 i = mma8452_get_odr_index(data); 554 555 *val = mma8452_os_ratio[ret][i]; 556 return IIO_VAL_INT; 557 } 558 559 return -EINVAL; 560} 561 562static int mma8452_calculate_sleep(struct mma8452_data *data) 563{ 564 int ret, i = mma8452_get_odr_index(data); 565 566 if (mma8452_samp_freq[i][0] > 0) 567 ret = 1000 / mma8452_samp_freq[i][0]; 568 else 569 ret = 1000; 570 571 return ret == 0 ? 1 : ret; 572} 573 574static int mma8452_standby(struct mma8452_data *data) 575{ 576 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 577 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 578} 579 580static int mma8452_active(struct mma8452_data *data) 581{ 582 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 583 data->ctrl_reg1); 584} 585 586/* returns >0 if active, 0 if in standby and <0 on error */ 587static int mma8452_is_active(struct mma8452_data *data) 588{ 589 int reg; 590 591 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 592 if (reg < 0) 593 return reg; 594 595 return reg & MMA8452_CTRL_ACTIVE; 596} 597 598static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 599{ 600 int ret; 601 int is_active; 602 603 mutex_lock(&data->lock); 604 605 is_active = mma8452_is_active(data); 606 if (is_active < 0) { 607 ret = is_active; 608 goto fail; 609 } 610 611 /* config can only be changed when in standby */ 612 if (is_active > 0) { 613 ret = mma8452_standby(data); 614 if (ret < 0) 615 goto fail; 616 } 617 618 ret = i2c_smbus_write_byte_data(data->client, reg, val); 619 if (ret < 0) 620 goto fail; 621 622 if (is_active > 0) { 623 ret = mma8452_active(data); 624 if (ret < 0) 625 goto fail; 626 } 627 628 ret = 0; 629fail: 630 mutex_unlock(&data->lock); 631 632 return ret; 633} 634 635static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 636{ 637 int reg; 638 639 reg = i2c_smbus_read_byte_data(data->client, 640 MMA8452_CTRL_REG2); 641 if (reg < 0) 642 return reg; 643 644 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 645 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 646 647 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 648} 649 650/* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 651static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 652{ 653 int val; 654 655 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 656 if (val < 0) 657 return val; 658 659 return !(val & MMA8452_FF_MT_CFG_OAE); 660} 661 662static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 663{ 664 int val; 665 666 if ((state && mma8452_freefall_mode_enabled(data)) || 667 (!state && !(mma8452_freefall_mode_enabled(data)))) 668 return 0; 669 670 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 671 if (val < 0) 672 return val; 673 674 if (state) { 675 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 676 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 677 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 678 val &= ~MMA8452_FF_MT_CFG_OAE; 679 } else { 680 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 681 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 682 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 683 val |= MMA8452_FF_MT_CFG_OAE; 684 } 685 686 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 687} 688 689static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 690 int val, int val2) 691{ 692 int i, reg; 693 694 i = mma8452_get_hp_filter_index(data, val, val2); 695 if (i < 0) 696 return i; 697 698 reg = i2c_smbus_read_byte_data(data->client, 699 MMA8452_HP_FILTER_CUTOFF); 700 if (reg < 0) 701 return reg; 702 703 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 704 reg |= i; 705 706 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 707} 708 709static int mma8452_write_raw(struct iio_dev *indio_dev, 710 struct iio_chan_spec const *chan, 711 int val, int val2, long mask) 712{ 713 struct mma8452_data *data = iio_priv(indio_dev); 714 int i, ret; 715 716 ret = iio_device_claim_direct_mode(indio_dev); 717 if (ret) 718 return ret; 719 720 switch (mask) { 721 case IIO_CHAN_INFO_SAMP_FREQ: 722 i = mma8452_get_samp_freq_index(data, val, val2); 723 if (i < 0) { 724 ret = i; 725 break; 726 } 727 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 728 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 729 730 data->sleep_val = mma8452_calculate_sleep(data); 731 732 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 733 data->ctrl_reg1); 734 break; 735 case IIO_CHAN_INFO_SCALE: 736 i = mma8452_get_scale_index(data, val, val2); 737 if (i < 0) { 738 ret = i; 739 break; 740 } 741 742 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 743 data->data_cfg |= i; 744 745 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 746 data->data_cfg); 747 break; 748 case IIO_CHAN_INFO_CALIBBIAS: 749 if (val < -128 || val > 127) { 750 ret = -EINVAL; 751 break; 752 } 753 754 ret = mma8452_change_config(data, 755 MMA8452_OFF_X + chan->scan_index, 756 val); 757 break; 758 759 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 760 if (val == 0 && val2 == 0) { 761 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 762 } else { 763 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 764 ret = mma8452_set_hp_filter_frequency(data, val, val2); 765 if (ret < 0) 766 break; 767 } 768 769 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 770 data->data_cfg); 771 break; 772 773 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 774 ret = mma8452_get_odr_index(data); 775 776 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 777 if (mma8452_os_ratio[i][ret] == val) { 778 ret = mma8452_set_power_mode(data, i); 779 break; 780 } 781 } 782 break; 783 default: 784 ret = -EINVAL; 785 break; 786 } 787 788 iio_device_release_direct_mode(indio_dev); 789 return ret; 790} 791 792static int mma8452_get_event_regs(struct mma8452_data *data, 793 const struct iio_chan_spec *chan, enum iio_event_direction dir, 794 const struct mma8452_event_regs **ev_reg) 795{ 796 if (!chan) 797 return -EINVAL; 798 799 switch (chan->type) { 800 case IIO_ACCEL: 801 switch (dir) { 802 case IIO_EV_DIR_RISING: 803 if ((data->chip_info->all_events 804 & MMA8452_INT_TRANS) && 805 (data->chip_info->enabled_events 806 & MMA8452_INT_TRANS)) 807 *ev_reg = &trans_ev_regs; 808 else 809 *ev_reg = &ff_mt_ev_regs; 810 return 0; 811 case IIO_EV_DIR_FALLING: 812 *ev_reg = &ff_mt_ev_regs; 813 return 0; 814 default: 815 return -EINVAL; 816 } 817 default: 818 return -EINVAL; 819 } 820} 821 822static int mma8452_read_event_value(struct iio_dev *indio_dev, 823 const struct iio_chan_spec *chan, 824 enum iio_event_type type, 825 enum iio_event_direction dir, 826 enum iio_event_info info, 827 int *val, int *val2) 828{ 829 struct mma8452_data *data = iio_priv(indio_dev); 830 int ret, us, power_mode; 831 const struct mma8452_event_regs *ev_regs; 832 833 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 834 if (ret) 835 return ret; 836 837 switch (info) { 838 case IIO_EV_INFO_VALUE: 839 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 840 if (ret < 0) 841 return ret; 842 843 *val = ret & ev_regs->ev_ths_mask; 844 845 return IIO_VAL_INT; 846 847 case IIO_EV_INFO_PERIOD: 848 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 849 if (ret < 0) 850 return ret; 851 852 power_mode = mma8452_get_power_mode(data); 853 if (power_mode < 0) 854 return power_mode; 855 856 us = ret * mma8452_time_step_us[power_mode][ 857 mma8452_get_odr_index(data)]; 858 *val = us / USEC_PER_SEC; 859 *val2 = us % USEC_PER_SEC; 860 861 return IIO_VAL_INT_PLUS_MICRO; 862 863 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 864 ret = i2c_smbus_read_byte_data(data->client, 865 MMA8452_TRANSIENT_CFG); 866 if (ret < 0) 867 return ret; 868 869 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 870 *val = 0; 871 *val2 = 0; 872 } else { 873 ret = mma8452_read_hp_filter(data, val, val2); 874 if (ret < 0) 875 return ret; 876 } 877 878 return IIO_VAL_INT_PLUS_MICRO; 879 880 default: 881 return -EINVAL; 882 } 883} 884 885static int mma8452_write_event_value(struct iio_dev *indio_dev, 886 const struct iio_chan_spec *chan, 887 enum iio_event_type type, 888 enum iio_event_direction dir, 889 enum iio_event_info info, 890 int val, int val2) 891{ 892 struct mma8452_data *data = iio_priv(indio_dev); 893 int ret, reg, steps; 894 const struct mma8452_event_regs *ev_regs; 895 896 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 897 if (ret) 898 return ret; 899 900 switch (info) { 901 case IIO_EV_INFO_VALUE: 902 if (val < 0 || val > ev_regs->ev_ths_mask) 903 return -EINVAL; 904 905 return mma8452_change_config(data, ev_regs->ev_ths, val); 906 907 case IIO_EV_INFO_PERIOD: 908 ret = mma8452_get_power_mode(data); 909 if (ret < 0) 910 return ret; 911 912 steps = (val * USEC_PER_SEC + val2) / 913 mma8452_time_step_us[ret][ 914 mma8452_get_odr_index(data)]; 915 916 if (steps < 0 || steps > 0xff) 917 return -EINVAL; 918 919 return mma8452_change_config(data, ev_regs->ev_count, steps); 920 921 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 922 reg = i2c_smbus_read_byte_data(data->client, 923 MMA8452_TRANSIENT_CFG); 924 if (reg < 0) 925 return reg; 926 927 if (val == 0 && val2 == 0) { 928 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 929 } else { 930 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 931 ret = mma8452_set_hp_filter_frequency(data, val, val2); 932 if (ret < 0) 933 return ret; 934 } 935 936 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 937 938 default: 939 return -EINVAL; 940 } 941} 942 943static int mma8452_read_event_config(struct iio_dev *indio_dev, 944 const struct iio_chan_spec *chan, 945 enum iio_event_type type, 946 enum iio_event_direction dir) 947{ 948 struct mma8452_data *data = iio_priv(indio_dev); 949 int ret; 950 const struct mma8452_event_regs *ev_regs; 951 952 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 953 if (ret) 954 return ret; 955 956 switch (dir) { 957 case IIO_EV_DIR_FALLING: 958 return mma8452_freefall_mode_enabled(data); 959 case IIO_EV_DIR_RISING: 960 ret = i2c_smbus_read_byte_data(data->client, 961 ev_regs->ev_cfg); 962 if (ret < 0) 963 return ret; 964 965 return !!(ret & BIT(chan->scan_index + 966 ev_regs->ev_cfg_chan_shift)); 967 default: 968 return -EINVAL; 969 } 970} 971 972static int mma8452_write_event_config(struct iio_dev *indio_dev, 973 const struct iio_chan_spec *chan, 974 enum iio_event_type type, 975 enum iio_event_direction dir, 976 int state) 977{ 978 struct mma8452_data *data = iio_priv(indio_dev); 979 int val, ret; 980 const struct mma8452_event_regs *ev_regs; 981 982 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 983 if (ret) 984 return ret; 985 986 ret = mma8452_set_runtime_pm_state(data->client, state); 987 if (ret) 988 return ret; 989 990 switch (dir) { 991 case IIO_EV_DIR_FALLING: 992 return mma8452_set_freefall_mode(data, state); 993 case IIO_EV_DIR_RISING: 994 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 995 if (val < 0) 996 return val; 997 998 if (state) { 999 if (mma8452_freefall_mode_enabled(data)) { 1000 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 1001 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 1002 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 1003 val |= MMA8452_FF_MT_CFG_OAE; 1004 } 1005 val |= BIT(chan->scan_index + 1006 ev_regs->ev_cfg_chan_shift); 1007 } else { 1008 if (mma8452_freefall_mode_enabled(data)) 1009 return 0; 1010 1011 val &= ~BIT(chan->scan_index + 1012 ev_regs->ev_cfg_chan_shift); 1013 } 1014 1015 val |= ev_regs->ev_cfg_ele; 1016 1017 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1018 default: 1019 return -EINVAL; 1020 } 1021} 1022 1023static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1024{ 1025 struct mma8452_data *data = iio_priv(indio_dev); 1026 s64 ts = iio_get_time_ns(indio_dev); 1027 int src; 1028 1029 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1030 if (src < 0) 1031 return; 1032 1033 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1034 iio_push_event(indio_dev, 1035 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1036 IIO_EV_TYPE_MAG, 1037 IIO_EV_DIR_RISING), 1038 ts); 1039 1040 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1041 iio_push_event(indio_dev, 1042 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1043 IIO_EV_TYPE_MAG, 1044 IIO_EV_DIR_RISING), 1045 ts); 1046 1047 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1048 iio_push_event(indio_dev, 1049 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1050 IIO_EV_TYPE_MAG, 1051 IIO_EV_DIR_RISING), 1052 ts); 1053} 1054 1055static irqreturn_t mma8452_interrupt(int irq, void *p) 1056{ 1057 struct iio_dev *indio_dev = p; 1058 struct mma8452_data *data = iio_priv(indio_dev); 1059 int ret = IRQ_NONE; 1060 int src; 1061 1062 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1063 if (src < 0) 1064 return IRQ_NONE; 1065 1066 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1067 return IRQ_NONE; 1068 1069 if (src & MMA8452_INT_DRDY) { 1070 iio_trigger_poll_chained(indio_dev->trig); 1071 ret = IRQ_HANDLED; 1072 } 1073 1074 if (src & MMA8452_INT_FF_MT) { 1075 if (mma8452_freefall_mode_enabled(data)) { 1076 s64 ts = iio_get_time_ns(indio_dev); 1077 1078 iio_push_event(indio_dev, 1079 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1080 IIO_MOD_X_AND_Y_AND_Z, 1081 IIO_EV_TYPE_MAG, 1082 IIO_EV_DIR_FALLING), 1083 ts); 1084 } 1085 ret = IRQ_HANDLED; 1086 } 1087 1088 if (src & MMA8452_INT_TRANS) { 1089 mma8452_transient_interrupt(indio_dev); 1090 ret = IRQ_HANDLED; 1091 } 1092 1093 return ret; 1094} 1095 1096static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1097{ 1098 struct iio_poll_func *pf = p; 1099 struct iio_dev *indio_dev = pf->indio_dev; 1100 struct mma8452_data *data = iio_priv(indio_dev); 1101 int ret; 1102 1103 ret = mma8452_read(data, data->buffer.channels); 1104 if (ret < 0) 1105 goto done; 1106 1107 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, 1108 iio_get_time_ns(indio_dev)); 1109 1110done: 1111 iio_trigger_notify_done(indio_dev->trig); 1112 1113 return IRQ_HANDLED; 1114} 1115 1116static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1117 unsigned int reg, unsigned int writeval, 1118 unsigned int *readval) 1119{ 1120 int ret; 1121 struct mma8452_data *data = iio_priv(indio_dev); 1122 1123 if (reg > MMA8452_MAX_REG) 1124 return -EINVAL; 1125 1126 if (!readval) 1127 return mma8452_change_config(data, reg, writeval); 1128 1129 ret = i2c_smbus_read_byte_data(data->client, reg); 1130 if (ret < 0) 1131 return ret; 1132 1133 *readval = ret; 1134 1135 return 0; 1136} 1137 1138static const struct iio_event_spec mma8452_freefall_event[] = { 1139 { 1140 .type = IIO_EV_TYPE_MAG, 1141 .dir = IIO_EV_DIR_FALLING, 1142 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1143 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1144 BIT(IIO_EV_INFO_PERIOD) | 1145 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1146 }, 1147}; 1148 1149static const struct iio_event_spec mma8652_freefall_event[] = { 1150 { 1151 .type = IIO_EV_TYPE_MAG, 1152 .dir = IIO_EV_DIR_FALLING, 1153 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1154 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1155 BIT(IIO_EV_INFO_PERIOD) 1156 }, 1157}; 1158 1159static const struct iio_event_spec mma8452_transient_event[] = { 1160 { 1161 .type = IIO_EV_TYPE_MAG, 1162 .dir = IIO_EV_DIR_RISING, 1163 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1164 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1165 BIT(IIO_EV_INFO_PERIOD) | 1166 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1167 }, 1168}; 1169 1170static const struct iio_event_spec mma8452_motion_event[] = { 1171 { 1172 .type = IIO_EV_TYPE_MAG, 1173 .dir = IIO_EV_DIR_RISING, 1174 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1175 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1176 BIT(IIO_EV_INFO_PERIOD) 1177 }, 1178}; 1179 1180/* 1181 * Threshold is configured in fixed 8G/127 steps regardless of 1182 * currently selected scale for measurement. 1183 */ 1184static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1185 1186static struct attribute *mma8452_event_attributes[] = { 1187 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1188 NULL, 1189}; 1190 1191static struct attribute_group mma8452_event_attribute_group = { 1192 .attrs = mma8452_event_attributes, 1193}; 1194 1195#define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1196 .type = IIO_ACCEL, \ 1197 .modified = 1, \ 1198 .channel2 = modifier, \ 1199 .scan_index = -1, \ 1200 .event_spec = mma8452_freefall_event, \ 1201 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1202} 1203 1204#define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1205 .type = IIO_ACCEL, \ 1206 .modified = 1, \ 1207 .channel2 = modifier, \ 1208 .scan_index = -1, \ 1209 .event_spec = mma8652_freefall_event, \ 1210 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1211} 1212 1213#define MMA8452_CHANNEL(axis, idx, bits) { \ 1214 .type = IIO_ACCEL, \ 1215 .modified = 1, \ 1216 .channel2 = IIO_MOD_##axis, \ 1217 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1218 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1219 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1220 BIT(IIO_CHAN_INFO_SCALE) | \ 1221 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1222 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1223 .scan_index = idx, \ 1224 .scan_type = { \ 1225 .sign = 's', \ 1226 .realbits = (bits), \ 1227 .storagebits = 16, \ 1228 .shift = 16 - (bits), \ 1229 .endianness = IIO_BE, \ 1230 }, \ 1231 .event_spec = mma8452_transient_event, \ 1232 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1233} 1234 1235#define MMA8652_CHANNEL(axis, idx, bits) { \ 1236 .type = IIO_ACCEL, \ 1237 .modified = 1, \ 1238 .channel2 = IIO_MOD_##axis, \ 1239 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1240 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1241 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1242 BIT(IIO_CHAN_INFO_SCALE) | \ 1243 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1244 .scan_index = idx, \ 1245 .scan_type = { \ 1246 .sign = 's', \ 1247 .realbits = (bits), \ 1248 .storagebits = 16, \ 1249 .shift = 16 - (bits), \ 1250 .endianness = IIO_BE, \ 1251 }, \ 1252 .event_spec = mma8452_motion_event, \ 1253 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1254} 1255 1256static const struct iio_chan_spec mma8451_channels[] = { 1257 MMA8452_CHANNEL(X, idx_x, 14), 1258 MMA8452_CHANNEL(Y, idx_y, 14), 1259 MMA8452_CHANNEL(Z, idx_z, 14), 1260 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1261 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1262}; 1263 1264static const struct iio_chan_spec mma8452_channels[] = { 1265 MMA8452_CHANNEL(X, idx_x, 12), 1266 MMA8452_CHANNEL(Y, idx_y, 12), 1267 MMA8452_CHANNEL(Z, idx_z, 12), 1268 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1269 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1270}; 1271 1272static const struct iio_chan_spec mma8453_channels[] = { 1273 MMA8452_CHANNEL(X, idx_x, 10), 1274 MMA8452_CHANNEL(Y, idx_y, 10), 1275 MMA8452_CHANNEL(Z, idx_z, 10), 1276 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1277 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1278}; 1279 1280static const struct iio_chan_spec mma8652_channels[] = { 1281 MMA8652_CHANNEL(X, idx_x, 12), 1282 MMA8652_CHANNEL(Y, idx_y, 12), 1283 MMA8652_CHANNEL(Z, idx_z, 12), 1284 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1285 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1286}; 1287 1288static const struct iio_chan_spec mma8653_channels[] = { 1289 MMA8652_CHANNEL(X, idx_x, 10), 1290 MMA8652_CHANNEL(Y, idx_y, 10), 1291 MMA8652_CHANNEL(Z, idx_z, 10), 1292 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1293 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1294}; 1295 1296enum { 1297 mma8451, 1298 mma8452, 1299 mma8453, 1300 mma8652, 1301 mma8653, 1302 fxls8471, 1303}; 1304 1305static const struct mma_chip_info mma_chip_info_table[] = { 1306 [mma8451] = { 1307 .name = "mma8451", 1308 .chip_id = MMA8451_DEVICE_ID, 1309 .channels = mma8451_channels, 1310 .num_channels = ARRAY_SIZE(mma8451_channels), 1311 /* 1312 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1313 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1314 * bit. 1315 * The userspace interface uses m/s^2 and we declare micro units 1316 * So scale factor for 12 bit here is given by: 1317 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1318 */ 1319 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1320 /* 1321 * Although we enable the interrupt sources once and for 1322 * all here the event detection itself is not enabled until 1323 * userspace asks for it by mma8452_write_event_config() 1324 */ 1325 .all_events = MMA8452_INT_DRDY | 1326 MMA8452_INT_TRANS | 1327 MMA8452_INT_FF_MT, 1328 .enabled_events = MMA8452_INT_TRANS | 1329 MMA8452_INT_FF_MT, 1330 }, 1331 [mma8452] = { 1332 .name = "mma8452", 1333 .chip_id = MMA8452_DEVICE_ID, 1334 .channels = mma8452_channels, 1335 .num_channels = ARRAY_SIZE(mma8452_channels), 1336 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1337 /* 1338 * Although we enable the interrupt sources once and for 1339 * all here the event detection itself is not enabled until 1340 * userspace asks for it by mma8452_write_event_config() 1341 */ 1342 .all_events = MMA8452_INT_DRDY | 1343 MMA8452_INT_TRANS | 1344 MMA8452_INT_FF_MT, 1345 .enabled_events = MMA8452_INT_TRANS | 1346 MMA8452_INT_FF_MT, 1347 }, 1348 [mma8453] = { 1349 .name = "mma8453", 1350 .chip_id = MMA8453_DEVICE_ID, 1351 .channels = mma8453_channels, 1352 .num_channels = ARRAY_SIZE(mma8453_channels), 1353 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1354 /* 1355 * Although we enable the interrupt sources once and for 1356 * all here the event detection itself is not enabled until 1357 * userspace asks for it by mma8452_write_event_config() 1358 */ 1359 .all_events = MMA8452_INT_DRDY | 1360 MMA8452_INT_TRANS | 1361 MMA8452_INT_FF_MT, 1362 .enabled_events = MMA8452_INT_TRANS | 1363 MMA8452_INT_FF_MT, 1364 }, 1365 [mma8652] = { 1366 .name = "mma8652", 1367 .chip_id = MMA8652_DEVICE_ID, 1368 .channels = mma8652_channels, 1369 .num_channels = ARRAY_SIZE(mma8652_channels), 1370 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1371 .all_events = MMA8452_INT_DRDY | 1372 MMA8452_INT_FF_MT, 1373 .enabled_events = MMA8452_INT_FF_MT, 1374 }, 1375 [mma8653] = { 1376 .name = "mma8653", 1377 .chip_id = MMA8653_DEVICE_ID, 1378 .channels = mma8653_channels, 1379 .num_channels = ARRAY_SIZE(mma8653_channels), 1380 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1381 /* 1382 * Although we enable the interrupt sources once and for 1383 * all here the event detection itself is not enabled until 1384 * userspace asks for it by mma8452_write_event_config() 1385 */ 1386 .all_events = MMA8452_INT_DRDY | 1387 MMA8452_INT_FF_MT, 1388 .enabled_events = MMA8452_INT_FF_MT, 1389 }, 1390 [fxls8471] = { 1391 .name = "fxls8471", 1392 .chip_id = FXLS8471_DEVICE_ID, 1393 .channels = mma8451_channels, 1394 .num_channels = ARRAY_SIZE(mma8451_channels), 1395 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1396 /* 1397 * Although we enable the interrupt sources once and for 1398 * all here the event detection itself is not enabled until 1399 * userspace asks for it by mma8452_write_event_config() 1400 */ 1401 .all_events = MMA8452_INT_DRDY | 1402 MMA8452_INT_TRANS | 1403 MMA8452_INT_FF_MT, 1404 .enabled_events = MMA8452_INT_TRANS | 1405 MMA8452_INT_FF_MT, 1406 }, 1407}; 1408 1409static struct attribute *mma8452_attributes[] = { 1410 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1411 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1412 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1413 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1414 NULL 1415}; 1416 1417static const struct attribute_group mma8452_group = { 1418 .attrs = mma8452_attributes, 1419}; 1420 1421static const struct iio_info mma8452_info = { 1422 .attrs = &mma8452_group, 1423 .read_raw = &mma8452_read_raw, 1424 .write_raw = &mma8452_write_raw, 1425 .event_attrs = &mma8452_event_attribute_group, 1426 .read_event_value = &mma8452_read_event_value, 1427 .write_event_value = &mma8452_write_event_value, 1428 .read_event_config = &mma8452_read_event_config, 1429 .write_event_config = &mma8452_write_event_config, 1430 .debugfs_reg_access = &mma8452_reg_access_dbg, 1431}; 1432 1433static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1434 1435static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1436 bool state) 1437{ 1438 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1439 struct mma8452_data *data = iio_priv(indio_dev); 1440 int reg, ret; 1441 1442 ret = mma8452_set_runtime_pm_state(data->client, state); 1443 if (ret) 1444 return ret; 1445 1446 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1447 if (reg < 0) 1448 return reg; 1449 1450 if (state) 1451 reg |= MMA8452_INT_DRDY; 1452 else 1453 reg &= ~MMA8452_INT_DRDY; 1454 1455 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1456} 1457 1458static const struct iio_trigger_ops mma8452_trigger_ops = { 1459 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1460 .validate_device = iio_trigger_validate_own_device, 1461}; 1462 1463static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1464{ 1465 struct mma8452_data *data = iio_priv(indio_dev); 1466 struct iio_trigger *trig; 1467 int ret; 1468 1469 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1470 indio_dev->name, 1471 indio_dev->id); 1472 if (!trig) 1473 return -ENOMEM; 1474 1475 trig->dev.parent = &data->client->dev; 1476 trig->ops = &mma8452_trigger_ops; 1477 iio_trigger_set_drvdata(trig, indio_dev); 1478 1479 ret = iio_trigger_register(trig); 1480 if (ret) 1481 return ret; 1482 1483 indio_dev->trig = iio_trigger_get(trig); 1484 1485 return 0; 1486} 1487 1488static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1489{ 1490 if (indio_dev->trig) 1491 iio_trigger_unregister(indio_dev->trig); 1492} 1493 1494static int mma8452_reset(struct i2c_client *client) 1495{ 1496 int i; 1497 int ret; 1498 1499 /* 1500 * Find on fxls8471, after config reset bit, it reset immediately, 1501 * and will not give ACK, so here do not check the return value. 1502 * The following code will read the reset register, and check whether 1503 * this reset works. 1504 */ 1505 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1506 MMA8452_CTRL_REG2_RST); 1507 1508 for (i = 0; i < 10; i++) { 1509 usleep_range(100, 200); 1510 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1511 if (ret == -EIO) 1512 continue; /* I2C comm reset */ 1513 if (ret < 0) 1514 return ret; 1515 if (!(ret & MMA8452_CTRL_REG2_RST)) 1516 return 0; 1517 } 1518 1519 return -ETIMEDOUT; 1520} 1521 1522static const struct of_device_id mma8452_dt_ids[] = { 1523 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1524 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1525 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1526 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1527 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1528 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1529 { } 1530}; 1531MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1532 1533static int mma8452_probe(struct i2c_client *client, 1534 const struct i2c_device_id *id) 1535{ 1536 struct mma8452_data *data; 1537 struct iio_dev *indio_dev; 1538 int ret; 1539 1540 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1541 if (!indio_dev) 1542 return -ENOMEM; 1543 1544 data = iio_priv(indio_dev); 1545 data->client = client; 1546 mutex_init(&data->lock); 1547 1548 data->chip_info = device_get_match_data(&client->dev); 1549 if (!data->chip_info) { 1550 if (id) { 1551 data->chip_info = &mma_chip_info_table[id->driver_data]; 1552 } else { 1553 dev_err(&client->dev, "unknown device model\n"); 1554 return -ENODEV; 1555 } 1556 } 1557 1558 data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); 1559 if (IS_ERR(data->vdd_reg)) 1560 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg), 1561 "failed to get VDD regulator!\n"); 1562 1563 data->vddio_reg = devm_regulator_get(&client->dev, "vddio"); 1564 if (IS_ERR(data->vddio_reg)) 1565 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg), 1566 "failed to get VDDIO regulator!\n"); 1567 1568 ret = regulator_enable(data->vdd_reg); 1569 if (ret) { 1570 dev_err(&client->dev, "failed to enable VDD regulator!\n"); 1571 return ret; 1572 } 1573 1574 ret = regulator_enable(data->vddio_reg); 1575 if (ret) { 1576 dev_err(&client->dev, "failed to enable VDDIO regulator!\n"); 1577 goto disable_regulator_vdd; 1578 } 1579 1580 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1581 if (ret < 0) 1582 goto disable_regulators; 1583 1584 switch (ret) { 1585 case MMA8451_DEVICE_ID: 1586 case MMA8452_DEVICE_ID: 1587 case MMA8453_DEVICE_ID: 1588 case MMA8652_DEVICE_ID: 1589 case MMA8653_DEVICE_ID: 1590 case FXLS8471_DEVICE_ID: 1591 if (ret == data->chip_info->chip_id) 1592 break; 1593 fallthrough; 1594 default: 1595 ret = -ENODEV; 1596 goto disable_regulators; 1597 } 1598 1599 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1600 data->chip_info->name, data->chip_info->chip_id); 1601 1602 i2c_set_clientdata(client, indio_dev); 1603 indio_dev->info = &mma8452_info; 1604 indio_dev->name = data->chip_info->name; 1605 indio_dev->modes = INDIO_DIRECT_MODE; 1606 indio_dev->channels = data->chip_info->channels; 1607 indio_dev->num_channels = data->chip_info->num_channels; 1608 indio_dev->available_scan_masks = mma8452_scan_masks; 1609 1610 ret = mma8452_reset(client); 1611 if (ret < 0) 1612 goto disable_regulators; 1613 1614 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1615 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1616 data->data_cfg); 1617 if (ret < 0) 1618 goto disable_regulators; 1619 1620 /* 1621 * By default set transient threshold to max to avoid events if 1622 * enabling without configuring threshold. 1623 */ 1624 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1625 MMA8452_TRANSIENT_THS_MASK); 1626 if (ret < 0) 1627 goto disable_regulators; 1628 1629 if (client->irq) { 1630 int irq2; 1631 1632 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1633 1634 if (irq2 == client->irq) { 1635 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1636 } else { 1637 ret = i2c_smbus_write_byte_data(client, 1638 MMA8452_CTRL_REG5, 1639 data->chip_info->all_events); 1640 if (ret < 0) 1641 goto disable_regulators; 1642 1643 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1644 } 1645 1646 ret = i2c_smbus_write_byte_data(client, 1647 MMA8452_CTRL_REG4, 1648 data->chip_info->enabled_events); 1649 if (ret < 0) 1650 goto disable_regulators; 1651 1652 ret = mma8452_trigger_setup(indio_dev); 1653 if (ret < 0) 1654 goto disable_regulators; 1655 } 1656 1657 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1658 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1659 1660 data->sleep_val = mma8452_calculate_sleep(data); 1661 1662 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1663 data->ctrl_reg1); 1664 if (ret < 0) 1665 goto trigger_cleanup; 1666 1667 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1668 mma8452_trigger_handler, NULL); 1669 if (ret < 0) 1670 goto trigger_cleanup; 1671 1672 if (client->irq) { 1673 ret = devm_request_threaded_irq(&client->dev, 1674 client->irq, 1675 NULL, mma8452_interrupt, 1676 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1677 client->name, indio_dev); 1678 if (ret) 1679 goto buffer_cleanup; 1680 } 1681 1682 ret = pm_runtime_set_active(&client->dev); 1683 if (ret < 0) 1684 goto buffer_cleanup; 1685 1686 pm_runtime_enable(&client->dev); 1687 pm_runtime_set_autosuspend_delay(&client->dev, 1688 MMA8452_AUTO_SUSPEND_DELAY_MS); 1689 pm_runtime_use_autosuspend(&client->dev); 1690 1691 ret = iio_device_register(indio_dev); 1692 if (ret < 0) 1693 goto buffer_cleanup; 1694 1695 ret = mma8452_set_freefall_mode(data, false); 1696 if (ret < 0) 1697 goto unregister_device; 1698 1699 return 0; 1700 1701unregister_device: 1702 iio_device_unregister(indio_dev); 1703 1704buffer_cleanup: 1705 iio_triggered_buffer_cleanup(indio_dev); 1706 1707trigger_cleanup: 1708 mma8452_trigger_cleanup(indio_dev); 1709 1710disable_regulators: 1711 regulator_disable(data->vddio_reg); 1712 1713disable_regulator_vdd: 1714 regulator_disable(data->vdd_reg); 1715 1716 return ret; 1717} 1718 1719static int mma8452_remove(struct i2c_client *client) 1720{ 1721 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1722 struct mma8452_data *data = iio_priv(indio_dev); 1723 1724 iio_device_unregister(indio_dev); 1725 1726 pm_runtime_disable(&client->dev); 1727 pm_runtime_set_suspended(&client->dev); 1728 pm_runtime_put_noidle(&client->dev); 1729 1730 iio_triggered_buffer_cleanup(indio_dev); 1731 mma8452_trigger_cleanup(indio_dev); 1732 mma8452_standby(iio_priv(indio_dev)); 1733 1734 regulator_disable(data->vddio_reg); 1735 regulator_disable(data->vdd_reg); 1736 1737 return 0; 1738} 1739 1740#ifdef CONFIG_PM 1741static int mma8452_runtime_suspend(struct device *dev) 1742{ 1743 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1744 struct mma8452_data *data = iio_priv(indio_dev); 1745 int ret; 1746 1747 mutex_lock(&data->lock); 1748 ret = mma8452_standby(data); 1749 mutex_unlock(&data->lock); 1750 if (ret < 0) { 1751 dev_err(&data->client->dev, "powering off device failed\n"); 1752 return -EAGAIN; 1753 } 1754 1755 ret = regulator_disable(data->vddio_reg); 1756 if (ret) { 1757 dev_err(dev, "failed to disable VDDIO regulator\n"); 1758 return ret; 1759 } 1760 1761 ret = regulator_disable(data->vdd_reg); 1762 if (ret) { 1763 dev_err(dev, "failed to disable VDD regulator\n"); 1764 return ret; 1765 } 1766 1767 return 0; 1768} 1769 1770static int mma8452_runtime_resume(struct device *dev) 1771{ 1772 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1773 struct mma8452_data *data = iio_priv(indio_dev); 1774 int ret, sleep_val; 1775 1776 ret = regulator_enable(data->vdd_reg); 1777 if (ret) { 1778 dev_err(dev, "failed to enable VDD regulator\n"); 1779 return ret; 1780 } 1781 1782 ret = regulator_enable(data->vddio_reg); 1783 if (ret) { 1784 dev_err(dev, "failed to enable VDDIO regulator\n"); 1785 regulator_disable(data->vdd_reg); 1786 return ret; 1787 } 1788 1789 ret = mma8452_active(data); 1790 if (ret < 0) 1791 goto runtime_resume_failed; 1792 1793 ret = mma8452_get_odr_index(data); 1794 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1795 if (sleep_val < 20) 1796 usleep_range(sleep_val * 1000, 20000); 1797 else 1798 msleep_interruptible(sleep_val); 1799 1800 return 0; 1801 1802runtime_resume_failed: 1803 regulator_disable(data->vddio_reg); 1804 regulator_disable(data->vdd_reg); 1805 1806 return ret; 1807} 1808#endif 1809 1810static const struct dev_pm_ops mma8452_pm_ops = { 1811 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1812 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1813 mma8452_runtime_resume, NULL) 1814}; 1815 1816static const struct i2c_device_id mma8452_id[] = { 1817 { "mma8451", mma8451 }, 1818 { "mma8452", mma8452 }, 1819 { "mma8453", mma8453 }, 1820 { "mma8652", mma8652 }, 1821 { "mma8653", mma8653 }, 1822 { "fxls8471", fxls8471 }, 1823 { } 1824}; 1825MODULE_DEVICE_TABLE(i2c, mma8452_id); 1826 1827static struct i2c_driver mma8452_driver = { 1828 .driver = { 1829 .name = "mma8452", 1830 .of_match_table = mma8452_dt_ids, 1831 .pm = &mma8452_pm_ops, 1832 }, 1833 .probe = mma8452_probe, 1834 .remove = mma8452_remove, 1835 .id_table = mma8452_id, 1836}; 1837module_i2c_driver(mma8452_driver); 1838 1839MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1840MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1841MODULE_LICENSE("GPL"); 1842