1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * SL82C105/Winbond 553 IDE driver 4 * 5 * Maintainer unknown. 6 * 7 * Drive tuning added from Rebel.com's kernel sources 8 * -- Russell King (15/11/98) linux@arm.linux.org.uk 9 * 10 * Merge in Russell's HW workarounds, fix various problems 11 * with the timing registers setup. 12 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org 13 * 14 * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com> 15 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 16 */ 17 18#include <linux/types.h> 19#include <linux/module.h> 20#include <linux/kernel.h> 21#include <linux/pci.h> 22#include <linux/ide.h> 23 24#include <asm/io.h> 25 26#define DRV_NAME "sl82c105" 27 28/* 29 * SL82C105 PCI config register 0x40 bits. 30 */ 31#define CTRL_IDE_IRQB (1 << 30) 32#define CTRL_IDE_IRQA (1 << 28) 33#define CTRL_LEGIRQ (1 << 11) 34#define CTRL_P1F16 (1 << 5) 35#define CTRL_P1EN (1 << 4) 36#define CTRL_P0F16 (1 << 1) 37#define CTRL_P0EN (1 << 0) 38 39/* 40 * Convert a PIO mode and cycle time to the required on/off times 41 * for the interface. This has protection against runaway timings. 42 */ 43static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) 44{ 45 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 46 unsigned int cmd_on, cmd_off; 47 u8 iordy = 0; 48 49 cmd_on = (t->active + 29) / 30; 50 cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; 51 52 if (cmd_on == 0) 53 cmd_on = 1; 54 55 if (cmd_off == 0) 56 cmd_off = 1; 57 58 if (ide_pio_need_iordy(drive, pio)) 59 iordy = 0x40; 60 61 return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; 62} 63 64/* 65 * Configure the chipset for PIO mode. 66 */ 67static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 68{ 69 struct pci_dev *dev = to_pci_dev(hwif->dev); 70 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 71 int reg = 0x44 + drive->dn * 4; 72 u16 drv_ctrl; 73 const u8 pio = drive->pio_mode - XFER_PIO_0; 74 75 drv_ctrl = get_pio_timings(drive, pio); 76 77 /* 78 * Store the PIO timings so that we can restore them 79 * in case DMA will be turned off... 80 */ 81 timings &= 0xffff0000; 82 timings |= drv_ctrl; 83 ide_set_drivedata(drive, (void *)timings); 84 85 pci_write_config_word(dev, reg, drv_ctrl); 86 pci_read_config_word (dev, reg, &drv_ctrl); 87 88 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, 89 ide_xfer_verbose(pio + XFER_PIO_0), 90 ide_pio_cycle_time(drive, pio), drv_ctrl); 91} 92 93/* 94 * Configure the chipset for DMA mode. 95 */ 96static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 97{ 98 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; 99 unsigned long timings = (unsigned long)ide_get_drivedata(drive); 100 u16 drv_ctrl; 101 const u8 speed = drive->dma_mode; 102 103 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; 104 105 /* 106 * Store the DMA timings so that we can actually program 107 * them when DMA will be turned on... 108 */ 109 timings &= 0x0000ffff; 110 timings |= (unsigned long)drv_ctrl << 16; 111 ide_set_drivedata(drive, (void *)timings); 112} 113 114static int sl82c105_test_irq(ide_hwif_t *hwif) 115{ 116 struct pci_dev *dev = to_pci_dev(hwif->dev); 117 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; 118 119 pci_read_config_dword(dev, 0x40, &val); 120 121 return (val & mask) ? 1 : 0; 122} 123 124/* 125 * The SL82C105 holds off all IDE interrupts while in DMA mode until 126 * all DMA activity is completed. Sometimes this causes problems (eg, 127 * when the drive wants to report an error condition). 128 * 129 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller 130 * state machine. We need to kick this to work around various bugs. 131 */ 132static inline void sl82c105_reset_host(struct pci_dev *dev) 133{ 134 u16 val; 135 136 pci_read_config_word(dev, 0x7e, &val); 137 pci_write_config_word(dev, 0x7e, val | (1 << 2)); 138 pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); 139} 140 141/* 142 * If we get an IRQ timeout, it might be that the DMA state machine 143 * got confused. Fix from Todd Inglett. Details from Winbond. 144 * 145 * This function is called when the IDE timer expires, the drive 146 * indicates that it is READY, and we were waiting for DMA to complete. 147 */ 148static void sl82c105_dma_lost_irq(ide_drive_t *drive) 149{ 150 ide_hwif_t *hwif = drive->hwif; 151 struct pci_dev *dev = to_pci_dev(hwif->dev); 152 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; 153 u8 dma_cmd; 154 155 printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n"); 156 157 /* 158 * Check the raw interrupt from the drive. 159 */ 160 pci_read_config_dword(dev, 0x40, &val); 161 if (val & mask) 162 printk(KERN_INFO "sl82c105: drive was requesting IRQ, " 163 "but host lost it\n"); 164 165 /* 166 * Was DMA enabled? If so, disable it - we're resetting the 167 * host. The IDE layer will be handling the drive for us. 168 */ 169 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 170 if (dma_cmd & 1) { 171 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 172 printk(KERN_INFO "sl82c105: DMA was enabled\n"); 173 } 174 175 sl82c105_reset_host(dev); 176} 177 178/* 179 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. 180 * Winbond recommend that the DMA state machine is reset prior to 181 * setting the bus master DMA enable bit. 182 * 183 * The generic IDE core will have disabled the BMEN bit before this 184 * function is called. 185 */ 186static void sl82c105_dma_start(ide_drive_t *drive) 187{ 188 ide_hwif_t *hwif = drive->hwif; 189 struct pci_dev *dev = to_pci_dev(hwif->dev); 190 int reg = 0x44 + drive->dn * 4; 191 192 pci_write_config_word(dev, reg, 193 (unsigned long)ide_get_drivedata(drive) >> 16); 194 195 sl82c105_reset_host(dev); 196 ide_dma_start(drive); 197} 198 199static void sl82c105_dma_clear(ide_drive_t *drive) 200{ 201 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 202 203 sl82c105_reset_host(dev); 204} 205 206static int sl82c105_dma_end(ide_drive_t *drive) 207{ 208 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 209 int reg = 0x44 + drive->dn * 4; 210 int ret = ide_dma_end(drive); 211 212 pci_write_config_word(dev, reg, 213 (unsigned long)ide_get_drivedata(drive)); 214 215 return ret; 216} 217 218/* 219 * ATA reset will clear the 16 bits mode in the control 220 * register, we need to reprogram it 221 */ 222static void sl82c105_resetproc(ide_drive_t *drive) 223{ 224 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 225 u32 val; 226 227 pci_read_config_dword(dev, 0x40, &val); 228 val |= (CTRL_P1F16 | CTRL_P0F16); 229 pci_write_config_dword(dev, 0x40, val); 230} 231 232/* 233 * Return the revision of the Winbond bridge 234 * which this function is part of. 235 */ 236static u8 sl82c105_bridge_revision(struct pci_dev *dev) 237{ 238 struct pci_dev *bridge; 239 240 /* 241 * The bridge should be part of the same device, but function 0. 242 */ 243 bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 244 dev->bus->number, 245 PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 246 if (!bridge) 247 return -1; 248 249 /* 250 * Make sure it is a Winbond 553 and is an ISA bridge. 251 */ 252 if (bridge->vendor != PCI_VENDOR_ID_WINBOND || 253 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || 254 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { 255 pci_dev_put(bridge); 256 return -1; 257 } 258 /* 259 * We need to find function 0's revision, not function 1 260 */ 261 pci_dev_put(bridge); 262 263 return bridge->revision; 264} 265 266/* 267 * Enable the PCI device 268 * 269 * --BenH: It's arch fixup code that should enable channels that 270 * have not been enabled by firmware. I decided we can still enable 271 * channel 0 here at least, but channel 1 has to be enabled by 272 * firmware or arch code. We still set both to 16 bits mode. 273 */ 274static int init_chipset_sl82c105(struct pci_dev *dev) 275{ 276 u32 val; 277 278 pci_read_config_dword(dev, 0x40, &val); 279 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; 280 pci_write_config_dword(dev, 0x40, val); 281 282 return 0; 283} 284 285static const struct ide_port_ops sl82c105_port_ops = { 286 .set_pio_mode = sl82c105_set_pio_mode, 287 .set_dma_mode = sl82c105_set_dma_mode, 288 .resetproc = sl82c105_resetproc, 289 .test_irq = sl82c105_test_irq, 290}; 291 292static const struct ide_dma_ops sl82c105_dma_ops = { 293 .dma_host_set = ide_dma_host_set, 294 .dma_setup = ide_dma_setup, 295 .dma_start = sl82c105_dma_start, 296 .dma_end = sl82c105_dma_end, 297 .dma_test_irq = ide_dma_test_irq, 298 .dma_lost_irq = sl82c105_dma_lost_irq, 299 .dma_timer_expiry = ide_dma_sff_timer_expiry, 300 .dma_clear = sl82c105_dma_clear, 301 .dma_sff_read_status = ide_dma_sff_read_status, 302}; 303 304static const struct ide_port_info sl82c105_chipset = { 305 .name = DRV_NAME, 306 .init_chipset = init_chipset_sl82c105, 307 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, 308 .port_ops = &sl82c105_port_ops, 309 .dma_ops = &sl82c105_dma_ops, 310 .host_flags = IDE_HFLAG_IO_32BIT | 311 IDE_HFLAG_UNMASK_IRQS | 312 IDE_HFLAG_SERIALIZE_DMA | 313 IDE_HFLAG_NO_AUTODMA, 314 .pio_mask = ATA_PIO5, 315 .mwdma_mask = ATA_MWDMA2, 316}; 317 318static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) 319{ 320 struct ide_port_info d = sl82c105_chipset; 321 u8 rev = sl82c105_bridge_revision(dev); 322 323 if (rev <= 5) { 324 /* 325 * Never ever EVER under any circumstances enable 326 * DMA when the bridge is this old. 327 */ 328 printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge " 329 "revision %d, BM-DMA disabled\n", rev); 330 d.dma_ops = NULL; 331 d.mwdma_mask = 0; 332 d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA; 333 } 334 335 return ide_pci_init_one(dev, &d, NULL); 336} 337 338static const struct pci_device_id sl82c105_pci_tbl[] = { 339 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, 340 { 0, }, 341}; 342MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); 343 344static struct pci_driver sl82c105_pci_driver = { 345 .name = "W82C105_IDE", 346 .id_table = sl82c105_pci_tbl, 347 .probe = sl82c105_init_one, 348 .remove = ide_pci_remove, 349 .suspend = ide_pci_suspend, 350 .resume = ide_pci_resume, 351}; 352 353static int __init sl82c105_ide_init(void) 354{ 355 return ide_pci_register_driver(&sl82c105_pci_driver); 356} 357 358static void __exit sl82c105_ide_exit(void) 359{ 360 pci_unregister_driver(&sl82c105_pci_driver); 361} 362 363module_init(sl82c105_ide_init); 364module_exit(sl82c105_ide_exit); 365 366MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); 367MODULE_LICENSE("GPL"); 368